JP2006041453A5 - - Google Patents
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- Publication number
- JP2006041453A5 JP2006041453A5 JP2004261247A JP2004261247A JP2006041453A5 JP 2006041453 A5 JP2006041453 A5 JP 2006041453A5 JP 2004261247 A JP2004261247 A JP 2004261247A JP 2004261247 A JP2004261247 A JP 2004261247A JP 2006041453 A5 JP2006041453 A5 JP 2006041453A5
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- film
- substrate
- forming method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000004888 barrier function Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 238000007772 electroless plating Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052729 chemical element Inorganic materials 0.000 description 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004261247A JP2006041453A (ja) | 2004-06-22 | 2004-09-08 | 配線形成方法及び配線形成装置 |
| US10/941,882 US20050282378A1 (en) | 2004-06-22 | 2004-09-16 | Interconnects forming method and interconnects forming apparatus |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004184239 | 2004-06-22 | ||
| JP2004261247A JP2006041453A (ja) | 2004-06-22 | 2004-09-08 | 配線形成方法及び配線形成装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006041453A JP2006041453A (ja) | 2006-02-09 |
| JP2006041453A5 true JP2006041453A5 (enExample) | 2007-07-19 |
Family
ID=35481169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004261247A Withdrawn JP2006041453A (ja) | 2004-06-22 | 2004-09-08 | 配線形成方法及び配線形成装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20050282378A1 (enExample) |
| JP (1) | JP2006041453A (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6764940B1 (en) | 2001-03-13 | 2004-07-20 | Novellus Systems, Inc. | Method for depositing a diffusion barrier for copper interconnect applications |
| US7842605B1 (en) | 2003-04-11 | 2010-11-30 | Novellus Systems, Inc. | Atomic layer profiling of diffusion barrier and metal seed layers |
| US8298933B2 (en) * | 2003-04-11 | 2012-10-30 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
| US7727881B1 (en) | 2004-11-03 | 2010-06-01 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
| US7727880B1 (en) | 2004-11-03 | 2010-06-01 | Novellus Systems, Inc. | Protective self-aligned buffer layers for damascene interconnects |
| US7510634B1 (en) | 2006-11-10 | 2009-03-31 | Novellus Systems, Inc. | Apparatus and methods for deposition and/or etch selectivity |
| JP2008140880A (ja) * | 2006-11-30 | 2008-06-19 | Tokyo Electron Ltd | 薄膜の形成方法、成膜装置及び記憶媒体 |
| US7682966B1 (en) | 2007-02-01 | 2010-03-23 | Novellus Systems, Inc. | Multistep method of depositing metal seed layers |
| US7932179B2 (en) * | 2007-07-27 | 2011-04-26 | Micron Technology, Inc. | Method for fabricating semiconductor device having backside redistribution layers |
| US20090032964A1 (en) * | 2007-07-31 | 2009-02-05 | Micron Technology, Inc. | System and method for providing semiconductor device features using a protective layer |
| US8268722B2 (en) * | 2009-06-03 | 2012-09-18 | Novellus Systems, Inc. | Interfacial capping layers for interconnects |
| JP5824808B2 (ja) * | 2011-01-07 | 2015-12-02 | 富士通株式会社 | 半導体装置及びその製造方法 |
| US8524599B2 (en) | 2011-03-17 | 2013-09-03 | Micron Technology, Inc. | Methods of forming at least one conductive element and methods of forming a semiconductor structure |
| CN103582932B (zh) | 2011-06-03 | 2017-01-18 | 诺发系统公司 | 用于互连的包含金属和硅的盖层 |
| US9087777B2 (en) * | 2013-03-14 | 2015-07-21 | United Test And Assembly Center Ltd. | Semiconductor packages and methods of packaging semiconductor devices |
| JP6186780B2 (ja) * | 2013-03-18 | 2017-08-30 | 富士通株式会社 | 半導体装置およびその製造方法 |
| US9633896B1 (en) | 2015-10-09 | 2017-04-25 | Lam Research Corporation | Methods for formation of low-k aluminum-containing etch stop films |
| JP6762831B2 (ja) * | 2016-03-31 | 2020-09-30 | 東京エレクトロン株式会社 | ハードマスクの形成方法、ハードマスクの形成装置及び記憶媒体 |
| US10224202B2 (en) | 2016-03-31 | 2019-03-05 | Tokyo Electron Limited | Forming method of hard mask, forming apparatus of hard mask and recording medium |
| TWI764388B (zh) * | 2020-04-27 | 2022-05-11 | 台灣積體電路製造股份有限公司 | 積體電路晶片及其形成方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5272104A (en) * | 1993-03-11 | 1993-12-21 | Harris Corporation | Bonded wafer process incorporating diamond insulator |
| US6303505B1 (en) * | 1998-07-09 | 2001-10-16 | Advanced Micro Devices, Inc. | Copper interconnect with improved electromigration resistance |
| US6153523A (en) * | 1998-12-09 | 2000-11-28 | Advanced Micro Devices, Inc. | Method of forming high density capping layers for copper interconnects with improved adhesion |
| US6046108A (en) * | 1999-06-25 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby |
| US6611060B1 (en) * | 1999-10-04 | 2003-08-26 | Kabushiki Kaisha Toshiba | Semiconductor device having a damascene type wiring layer |
| EP1335038A4 (en) * | 2000-10-26 | 2008-05-14 | Ebara Corp | DEVICE AND METHOD FOR ELECTRO-PLATING |
| US7193323B2 (en) * | 2003-11-18 | 2007-03-20 | International Business Machines Corporation | Electroplated CoWP composite structures as copper barrier layers |
-
2004
- 2004-09-08 JP JP2004261247A patent/JP2006041453A/ja not_active Withdrawn
- 2004-09-16 US US10/941,882 patent/US20050282378A1/en not_active Abandoned
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