JP2006041453A - 配線形成方法及び配線形成装置 - Google Patents

配線形成方法及び配線形成装置 Download PDF

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Publication number
JP2006041453A
JP2006041453A JP2004261247A JP2004261247A JP2006041453A JP 2006041453 A JP2006041453 A JP 2006041453A JP 2004261247 A JP2004261247 A JP 2004261247A JP 2004261247 A JP2004261247 A JP 2004261247A JP 2006041453 A JP2006041453 A JP 2006041453A
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JP
Japan
Prior art keywords
wiring
film
substrate
insulating film
barrier film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004261247A
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English (en)
Japanese (ja)
Other versions
JP2006041453A5 (enExample
Inventor
Akira Fukunaga
明 福永
Manabu Tsujimura
学 辻村
Hiroaki Inoue
裕章 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Priority to JP2004261247A priority Critical patent/JP2006041453A/ja
Priority to US10/941,882 priority patent/US20050282378A1/en
Publication of JP2006041453A publication Critical patent/JP2006041453A/ja
Publication of JP2006041453A5 publication Critical patent/JP2006041453A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004261247A 2004-06-22 2004-09-08 配線形成方法及び配線形成装置 Withdrawn JP2006041453A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004261247A JP2006041453A (ja) 2004-06-22 2004-09-08 配線形成方法及び配線形成装置
US10/941,882 US20050282378A1 (en) 2004-06-22 2004-09-16 Interconnects forming method and interconnects forming apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004184239 2004-06-22
JP2004261247A JP2006041453A (ja) 2004-06-22 2004-09-08 配線形成方法及び配線形成装置

Publications (2)

Publication Number Publication Date
JP2006041453A true JP2006041453A (ja) 2006-02-09
JP2006041453A5 JP2006041453A5 (enExample) 2007-07-19

Family

ID=35481169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004261247A Withdrawn JP2006041453A (ja) 2004-06-22 2004-09-08 配線形成方法及び配線形成装置

Country Status (2)

Country Link
US (1) US20050282378A1 (enExample)
JP (1) JP2006041453A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140880A (ja) * 2006-11-30 2008-06-19 Tokyo Electron Ltd 薄膜の形成方法、成膜装置及び記憶媒体
JP2012146752A (ja) * 2011-01-07 2012-08-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2014183127A (ja) * 2013-03-18 2014-09-29 Fujitsu Ltd 半導体装置およびその製造方法
JP2017188644A (ja) * 2016-03-31 2017-10-12 東京エレクトロン株式会社 ハードマスクの形成方法、ハードマスクの形成装置及び記憶媒体

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6764940B1 (en) 2001-03-13 2004-07-20 Novellus Systems, Inc. Method for depositing a diffusion barrier for copper interconnect applications
US7842605B1 (en) 2003-04-11 2010-11-30 Novellus Systems, Inc. Atomic layer profiling of diffusion barrier and metal seed layers
US8298933B2 (en) * 2003-04-11 2012-10-30 Novellus Systems, Inc. Conformal films on semiconductor substrates
US7727881B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
US7727880B1 (en) 2004-11-03 2010-06-01 Novellus Systems, Inc. Protective self-aligned buffer layers for damascene interconnects
US7510634B1 (en) 2006-11-10 2009-03-31 Novellus Systems, Inc. Apparatus and methods for deposition and/or etch selectivity
US7682966B1 (en) 2007-02-01 2010-03-23 Novellus Systems, Inc. Multistep method of depositing metal seed layers
US7932179B2 (en) * 2007-07-27 2011-04-26 Micron Technology, Inc. Method for fabricating semiconductor device having backside redistribution layers
US20090032964A1 (en) * 2007-07-31 2009-02-05 Micron Technology, Inc. System and method for providing semiconductor device features using a protective layer
US8268722B2 (en) * 2009-06-03 2012-09-18 Novellus Systems, Inc. Interfacial capping layers for interconnects
US8524599B2 (en) 2011-03-17 2013-09-03 Micron Technology, Inc. Methods of forming at least one conductive element and methods of forming a semiconductor structure
CN103582932B (zh) 2011-06-03 2017-01-18 诺发系统公司 用于互连的包含金属和硅的盖层
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US9633896B1 (en) 2015-10-09 2017-04-25 Lam Research Corporation Methods for formation of low-k aluminum-containing etch stop films
US10224202B2 (en) 2016-03-31 2019-03-05 Tokyo Electron Limited Forming method of hard mask, forming apparatus of hard mask and recording medium
TWI764388B (zh) * 2020-04-27 2022-05-11 台灣積體電路製造股份有限公司 積體電路晶片及其形成方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272104A (en) * 1993-03-11 1993-12-21 Harris Corporation Bonded wafer process incorporating diamond insulator
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6153523A (en) * 1998-12-09 2000-11-28 Advanced Micro Devices, Inc. Method of forming high density capping layers for copper interconnects with improved adhesion
US6046108A (en) * 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US6611060B1 (en) * 1999-10-04 2003-08-26 Kabushiki Kaisha Toshiba Semiconductor device having a damascene type wiring layer
EP1335038A4 (en) * 2000-10-26 2008-05-14 Ebara Corp DEVICE AND METHOD FOR ELECTRO-PLATING
US7193323B2 (en) * 2003-11-18 2007-03-20 International Business Machines Corporation Electroplated CoWP composite structures as copper barrier layers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140880A (ja) * 2006-11-30 2008-06-19 Tokyo Electron Ltd 薄膜の形成方法、成膜装置及び記憶媒体
JP2012146752A (ja) * 2011-01-07 2012-08-02 Fujitsu Ltd 半導体装置及びその製造方法
JP2014183127A (ja) * 2013-03-18 2014-09-29 Fujitsu Ltd 半導体装置およびその製造方法
JP2017188644A (ja) * 2016-03-31 2017-10-12 東京エレクトロン株式会社 ハードマスクの形成方法、ハードマスクの形成装置及び記憶媒体

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Publication number Publication date
US20050282378A1 (en) 2005-12-22

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