JP2005531919A5 - - Google Patents

Download PDF

Info

Publication number
JP2005531919A5
JP2005531919A5 JP2003579272A JP2003579272A JP2005531919A5 JP 2005531919 A5 JP2005531919 A5 JP 2005531919A5 JP 2003579272 A JP2003579272 A JP 2003579272A JP 2003579272 A JP2003579272 A JP 2003579272A JP 2005531919 A5 JP2005531919 A5 JP 2005531919A5
Authority
JP
Japan
Prior art keywords
sidewall
layer
dielectric
forming
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003579272A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005531919A (ja
Filing date
Publication date
Priority claimed from US10/101,298 external-priority patent/US6753242B2/en
Application filed filed Critical
Publication of JP2005531919A publication Critical patent/JP2005531919A/ja
Publication of JP2005531919A5 publication Critical patent/JP2005531919A5/ja
Pending legal-status Critical Current

Links

JP2003579272A 2002-03-19 2003-03-14 集積回路装置およびその製造方法 Pending JP2005531919A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/101,298 US6753242B2 (en) 2002-03-19 2002-03-19 Integrated circuit device and method therefor
PCT/US2003/007835 WO2003081660A1 (en) 2002-03-19 2003-03-14 Integrated circuit device and method therefor

Publications (2)

Publication Number Publication Date
JP2005531919A JP2005531919A (ja) 2005-10-20
JP2005531919A5 true JP2005531919A5 (enExample) 2006-06-01

Family

ID=28039985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003579272A Pending JP2005531919A (ja) 2002-03-19 2003-03-14 集積回路装置およびその製造方法

Country Status (8)

Country Link
US (2) US6753242B2 (enExample)
EP (1) EP1485948A1 (enExample)
JP (1) JP2005531919A (enExample)
KR (1) KR100961404B1 (enExample)
CN (1) CN100339961C (enExample)
AU (1) AU2003225792A1 (enExample)
TW (1) TWI283029B (enExample)
WO (1) WO2003081660A1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100488099B1 (ko) * 2002-11-18 2005-05-06 한국전자통신연구원 쇼오트 채널 모오스 트랜지스터 및 그 제조 방법
US6884712B2 (en) * 2003-02-07 2005-04-26 Chartered Semiconductor Manufacturing, Ltd. Method of manufacturing semiconductor local interconnect and contact
US6913980B2 (en) * 2003-06-30 2005-07-05 Texas Instruments Incorporated Process method of source drain spacer engineering to improve transistor capacitance
JP2005109381A (ja) * 2003-10-02 2005-04-21 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US7229885B2 (en) * 2004-01-06 2007-06-12 International Business Machines Corporation Formation of a disposable spacer to post dope a gate conductor
US7064396B2 (en) * 2004-03-01 2006-06-20 Freescale Semiconductor, Inc. Integrated circuit with multiple spacer insulating region widths
US8896048B1 (en) * 2004-06-04 2014-11-25 Spansion Llc Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
KR100541657B1 (ko) * 2004-06-29 2006-01-11 삼성전자주식회사 멀티 게이트 트랜지스터의 제조방법 및 이에 의해 제조된멀티 게이트 트랜지스터
US7170130B2 (en) * 2004-08-11 2007-01-30 Spansion Llc Memory cell with reduced DIBL and Vss resistance
KR100668954B1 (ko) * 2004-12-15 2007-01-12 동부일렉트로닉스 주식회사 박막트랜지스터 제조 방법
KR100685575B1 (ko) * 2004-12-28 2007-02-22 주식회사 하이닉스반도체 반도체 소자의 스텝 채널 형성 방법
US7544553B2 (en) * 2005-03-30 2009-06-09 Infineon Technologies Ag Integration scheme for fully silicided gate
US20070007578A1 (en) * 2005-07-07 2007-01-11 Li Chi N B Sub zero spacer for shallow MDD junction to improve BVDSS in NVM bitcell
US8159030B2 (en) * 2005-11-30 2012-04-17 Globalfoundries Inc. Strained MOS device and methods for its fabrication
KR100741908B1 (ko) * 2005-12-30 2007-07-24 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7317222B2 (en) * 2006-01-27 2008-01-08 Freescale Semiconductor, Inc. Memory cell using a dielectric having non-uniform thickness
JP4799217B2 (ja) * 2006-03-03 2011-10-26 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2008098567A (ja) * 2006-10-16 2008-04-24 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US7700473B2 (en) * 2007-04-09 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Gated semiconductor device and method of fabricating same
US7745344B2 (en) * 2007-10-29 2010-06-29 Freescale Semiconductor, Inc. Method for integrating NVM circuitry with logic circuitry
KR101815527B1 (ko) * 2010-10-07 2018-01-05 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN102420116B (zh) * 2011-06-07 2013-12-04 上海华力微电子有限公司 消除栅极凹形缺陷的方法
JP5715551B2 (ja) * 2011-11-25 2015-05-07 株式会社東芝 半導体装置およびその製造方法
CN104752223B (zh) * 2013-12-31 2017-12-29 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9647116B1 (en) 2015-10-28 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating self-aligned contact in a semiconductor device
US11653498B2 (en) 2017-11-30 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with improved data retention
CN114121788A (zh) * 2021-11-24 2022-03-01 华虹半导体(无锡)有限公司 或非闪存器件的制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960270A (en) * 1997-08-11 1999-09-28 Motorola, Inc. Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
US6066567A (en) 1997-12-18 2000-05-23 Advanced Micro Devices, Inc. Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process
US6087271A (en) 1997-12-18 2000-07-11 Advanced Micro Devices, Inc. Methods for removal of an anti-reflective coating following a resist protect etching process
US5902125A (en) 1997-12-29 1999-05-11 Texas Instruments--Acer Incorporated Method to form stacked-Si gate pMOSFETs with elevated and extended S/D junction
US5972762A (en) 1998-01-05 1999-10-26 Texas Instruments--Acer Incorporated Method of forming mosfets with recessed self-aligned silicide gradual S/D junction
US6245682B1 (en) 1999-03-11 2001-06-12 Taiwan Semiconductor Manufacturing Company Removal of SiON ARC film after poly photo and etch
US6271133B1 (en) * 1999-04-12 2001-08-07 Chartered Semiconductor Manufacturing Ltd. Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication
JP2003519910A (ja) 1999-12-30 2003-06-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 埋れ反射防止膜を除去するための改良された方法
US6156126A (en) 2000-01-18 2000-12-05 United Microelectronics Corp. Method for reducing or avoiding the formation of a silicon recess in SDE junction regions
US6372589B1 (en) * 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
US6368947B1 (en) * 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6555865B2 (en) * 2001-07-10 2003-04-29 Samsung Electronics Co. Ltd. Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
US6818504B2 (en) * 2001-08-10 2004-11-16 Hynix Semiconductor America, Inc. Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications
US6812515B2 (en) * 2001-11-26 2004-11-02 Hynix Semiconductor, Inc. Polysilicon layers structure and method of forming same

Similar Documents

Publication Publication Date Title
JP2005531919A5 (enExample)
CN100483691C (zh) 快闪存储器件及其制造方法
KR0154161B1 (ko) 반도체소자의 캐패시터 제조방법
JP2008504679A5 (enExample)
CN101312214B (zh) 半导体装置及其制造方法
TW201401442A (zh) 半導體元件的製造方法
TWI661540B (zh) 記憶元件的製造方法
CN105870324B (zh) 薄膜存储器技术的l形电容器
TW200849486A (en) Memory structure and method of making the same
TW201436098A (zh) 半導體結構及其製造方法
CN103839817A (zh) 半导体器件及其制造方法
CN103730435A (zh) 半导体结构及其制造方法
KR101001466B1 (ko) 비휘발성 메모리 소자의 제조 방법
CN110707089B (zh) 半导体器件的制备方法
CN104051338B (zh) 半导体结构及其制造方法
CN110459507B (zh) 一种半导体存储装置的形成方法
CN100559568C (zh) 非易失性存储器件的制造方法
JP4391354B2 (ja) 側壁方式を用いたフラッシュメモリの形成方法
KR100526476B1 (ko) 스플릿 게이트형 플래쉬 메모리 소자의제조방법
KR100950752B1 (ko) 반도체 소자 및 그의 제조방법
TW201624622A (zh) 非揮發性記憶胞、ｎａｎｄ型非揮發性記憶體及其製造方法
US9397183B2 (en) Semiconductor memory device with ONO stack
CN105280590B (zh) 半导体结构及其制造方法
CN111029407A (zh) 场效应晶体管及其制造方法
TWI753670B (zh) 半導體裝置