JP2005524235A5 - - Google Patents

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Publication number
JP2005524235A5
JP2005524235A5 JP2004500540A JP2004500540A JP2005524235A5 JP 2005524235 A5 JP2005524235 A5 JP 2005524235A5 JP 2004500540 A JP2004500540 A JP 2004500540A JP 2004500540 A JP2004500540 A JP 2004500540A JP 2005524235 A5 JP2005524235 A5 JP 2005524235A5
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JP
Japan
Prior art keywords
wafer
housing
gas
edge
flow
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Pending
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JP2004500540A
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English (en)
Japanese (ja)
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JP2005524235A (ja
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Priority claimed from US10/401,074 external-priority patent/US6936546B2/en
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Publication of JP2005524235A publication Critical patent/JP2005524235A/ja
Publication of JP2005524235A5 publication Critical patent/JP2005524235A5/ja
Pending legal-status Critical Current

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JP2004500540A 2002-04-26 2003-04-24 処理工程内で半導体基板の縁部近傍領域に薄膜を成形するための方法及び装置 Pending JP2005524235A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US37615402P 2002-04-26 2002-04-26
US10/401,074 US6936546B2 (en) 2002-04-26 2003-03-27 Apparatus for shaping thin films in the near-edge regions of in-process semiconductor substrates
PCT/US2003/012615 WO2003092337A2 (en) 2002-04-26 2003-04-24 Method and apparatus for shaping thin films in the near-edge regions of in-process semiconductor substrates

Publications (2)

Publication Number Publication Date
JP2005524235A JP2005524235A (ja) 2005-08-11
JP2005524235A5 true JP2005524235A5 (https=) 2006-06-15

Family

ID=29254649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004500540A Pending JP2005524235A (ja) 2002-04-26 2003-04-24 処理工程内で半導体基板の縁部近傍領域に薄膜を成形するための方法及び装置

Country Status (6)

Country Link
US (2) US6936546B2 (https=)
EP (1) EP1500129A4 (https=)
JP (1) JP2005524235A (https=)
KR (1) KR20050010770A (https=)
AU (1) AU2003225127A1 (https=)
WO (1) WO2003092337A2 (https=)

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