JP2005217382A - キャパシタ装置とそれを備えた半導体装置、及びキャパシタ装置の製造方法 - Google Patents
キャパシタ装置とそれを備えた半導体装置、及びキャパシタ装置の製造方法 Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 172
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 title claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000011888 foil Substances 0.000 claims description 16
- 229910000679 solder Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 239000011889 copper foil Substances 0.000 description 18
- 239000000758 substrate Substances 0.000 description 7
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
【解決手段】 一対の端子20a,20cを備えたキャパシタ部品20が、その下面が絶縁膜16で被覆されない状態で絶縁膜16に埋設され、一対の端子20a,20c上の絶縁膜16に形成されたビアホール16xを介して、一対の端子20a,20cの上面に接続された上側配線パターン22が絶縁膜16の上面にそれぞれ形成され、一対の端子20a,20cの下面に接続された下側配線パターン24が絶縁膜16の下面側にそれぞれ形成されていることを含む。
【選択図】 図5
Description
図6は本発明の第2実施形態のキャパシタ装置を示す断面図である。第2の実施形態は、第1実施形態の図5のキャパシタ装置に接続端子を設けた形態である。図6に示すように、第2実施形態のキャパシタ装置1aでは、図5のキャパシタ装置1の両面側の第1接続部22x及び第2接続部24x上などに開口部26xが設けられたソルダレジスト膜26がそれぞれ形成されている。さらに、キャパシタ装置1aの両面側の第1及び第2接続部22x,24x上などに接続端子28が設けられている。接続端子28は、例えばはんだボールが搭載されて形成される。
図8は本発明の第3実施形態のキャパシタ装置(その1)を示す断面図、図9は本発明の第3実施形態のキャパシタ装置(その2)を示す断面図、図10は図9のキャパシタ装置上に半導体チップが実装された半導体装置を示す断面図である。
Claims (14)
- 絶縁膜と、
両端側に端子をそれぞれ備え、該両端側の端子が水平方向に配置されるキャパシタ部品であって、前記キャパシタ部品の下面が前記絶縁膜で被覆されない状態で、前記絶縁膜に埋設された前記キャパシタ部品と、
前記両端側の端子上の前記絶縁膜の部分にそれぞれ形成されたビアホールと、
前記絶縁膜の上面側に形成され、前記ビアホールを介して前記両端側の端子の上面にそれぞれ接続された上側配線パターンと、
前記絶縁膜の下面側に形成され、前記両端側の端子の下面にそれぞれ接続された下側配線パターンとを有することを特徴とするキャパシタ装置。 - 前記両端側の端子の上の前記上側配線パターンの部分に第1接続部がそれぞれ画定され、前記両端側の端子の下の前記下側配線パターンの部分に第2接続部がそれぞれ画定されており、前記第1接続部及び第2接続部にそれぞれ接続端子が設けられていることを特徴とする請求項1に記載のキャパシタ装置。
- 前記キャパシタ部品の両端側の端子の側面外側部にはそれぞれはんだ層が接続されて形成されており、前記下側配線パターンは、はんだ層の下面にさらに接続されていることを特徴とする請求項1に記載のキャパシタ装置。
- 前記キャパシタ部品が埋設されていない前記絶縁膜の部分を貫通するビアホールがさらに形成されており、前記上側配線パターン及び前記下側配線パターンは、前記絶縁膜を貫通するビアホールを介して相互接続される配線パターンをそれぞれ含むことを特徴とする請求項1に記載のキャパシタ装置。
- 前記キャパシタ装置の両面側の前記上側配線パターン及び前記下側配線パターンに、絶縁膜の開口部を介して接続される配線層がそれぞれ一層以上形成されていることを特徴とする請求項1又は4に記載のキャパシタ装置。
- 前記キャパシタ部品の前記両端側の端子上の最上の前記配線層の部分に接続端子がそれぞれ設けられ、前記キャパシタ部品の前記両端側の端子の下の最下の前記配線層の部分に接続端子がそれぞれ設けられていることを特徴とする請求項5に記載のキャパシタ装置。
- 前記絶縁膜は、樹脂よりなることを特徴とする請求項1乃至6のいずれか一項に記載のキャパシタ装置。
- 請求項2に記載のキャパシタ装置と、
下面側に接続端子を備えた回路基板と、
前記回路基板の上面側に実装された半導体チップとを有し、
前記半導体チップが実装された前記回路基板の接続端子が、前記キャパシタ装置の上側の前記接続端子に接続されていることを特徴とする半導体装置。 - 請求項2又は6に記載のキャパシタ装置と、
前記キャパシタ装置の上側の前記接続端子に接続された半導体チップとを有することを特徴とする半導体装置。 - 支持体の上に剥離層を介して金属箔を形成する工程と、
前記金属箔上に、両端側に端子をそれぞれ備えたキャパシタ部品を前記両端側の端子が水平方向に配置されるようにして実装する工程と、
前記キャパシタ部品を被覆する絶縁膜を形成する工程と、
前記キャパシタ部品の両端側の端子上の前記絶縁膜の部分にビアホールをそれぞれ形成する工程と、
前記ビアホールを介して前記両端側の端子の上面にそれぞれ接続される上側配線パターンを前記絶縁膜の上面側に形成する工程と、
前記金属箔を前記剥離層との界面から剥離することにより、前記金属箔、前記キャパシタ部品、前記絶縁膜及び前記上側配線パターンにより構成されるキャパシタ部材を得る工程と、
前記キャパシタ部材の前記金属箔をパターニングすることにより、前記両端側の端子の下面にそれぞれ接続される下側配線パターンを前記絶縁膜の下面側に形成する工程とを有することを特徴とするキャパシタ装置の製造方法。 - 前記下側配線パターンを形成する工程の後に、前記上側配線パターン及び前記下側配線パターンに絶縁膜の開口部を介してそれぞれ接続される配線層を一層以上形成する工程をさらに有することを特徴とする請求項10に記載のキャパシタ装置の製造方法。
- 前記下側配線パターンを形成する工程の後に、前記上側配線パターン及び下側配線パターンの接続部に接続端子を形成する工程をさらに有することを特徴とする請求項10に記載のキャパシタ装置の製造方法。
- 前記配線層を一層以上形成する工程の後に、両面側の前記最上及び最下の前記配線層に接続される接続端子をそれぞれ形成する工程をさらに有することを特徴とする請求項11に記載のキャパシタ装置の製造方法。
- 前記支持体は金属板又は樹脂板よりなり、前記金属箔は銅よりなることを特徴とする請求項10乃至13のいずれか一項に記載のキャパシタ装置の製造方法。
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