JP2005116695A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2005116695A
JP2005116695A JP2003347274A JP2003347274A JP2005116695A JP 2005116695 A JP2005116695 A JP 2005116695A JP 2003347274 A JP2003347274 A JP 2003347274A JP 2003347274 A JP2003347274 A JP 2003347274A JP 2005116695 A JP2005116695 A JP 2005116695A
Authority
JP
Japan
Prior art keywords
impurity diffusion
transistor
diffusion region
gate electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2003347274A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005116695A5 (https=
Inventor
Kenji Kojima
健嗣 小島
Tatsuya Oguro
達也 大黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003347274A priority Critical patent/JP2005116695A/ja
Priority to US10/865,999 priority patent/US20050073009A1/en
Publication of JP2005116695A publication Critical patent/JP2005116695A/ja
Publication of JP2005116695A5 publication Critical patent/JP2005116695A5/ja
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2003347274A 2003-10-06 2003-10-06 半導体装置 Abandoned JP2005116695A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003347274A JP2005116695A (ja) 2003-10-06 2003-10-06 半導体装置
US10/865,999 US20050073009A1 (en) 2003-10-06 2004-06-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003347274A JP2005116695A (ja) 2003-10-06 2003-10-06 半導体装置

Publications (2)

Publication Number Publication Date
JP2005116695A true JP2005116695A (ja) 2005-04-28
JP2005116695A5 JP2005116695A5 (https=) 2006-02-02

Family

ID=34386399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003347274A Abandoned JP2005116695A (ja) 2003-10-06 2003-10-06 半導体装置

Country Status (2)

Country Link
US (1) US20050073009A1 (https=)
JP (1) JP2005116695A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013051175A1 (ja) * 2011-10-06 2013-04-11 パナソニック株式会社 半導体集積回路装置
JP2014132717A (ja) * 2013-01-07 2014-07-17 Seiko Epson Corp 静電気放電保護回路及び半導体回路装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8049282B2 (en) * 2006-09-21 2011-11-01 Agere Systems Inc. Bipolar device having buried contacts
US20080316659A1 (en) * 2007-06-19 2008-12-25 Ismail Hakki Oguzman High voltage esd protection featuring pnp bipolar junction transistor
JP5595751B2 (ja) * 2009-03-11 2014-09-24 ルネサスエレクトロニクス株式会社 Ｅｓｄ保護素子
JP2014203851A (ja) * 2013-04-01 2014-10-27 株式会社東芝 半導体装置及びその製造方法
JP2015095492A (ja) * 2013-11-08 2015-05-18 株式会社東芝 半導体装置
US20160086960A1 (en) * 2014-09-22 2016-03-24 Texas Instruments Incorporated Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance
JP2017055087A (ja) * 2015-09-11 2017-03-16 株式会社東芝 半導体装置
US20250151400A1 (en) * 2023-11-03 2025-05-08 International Business Machines Corporation Semiconductor structures with integrated electrostatic discharge clamp circuits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214627A (ja) * 1998-01-21 1999-08-06 Mitsubishi Electric Corp Ｅｓｄ保護素子及びその製造方法
US6226038B1 (en) * 1998-04-03 2001-05-01 Avid Technology, Inc. HDTV editing and effects previsualization using SDTV devices
US6589847B1 (en) * 2000-08-03 2003-07-08 Advanced Micro Devices, Inc. Tilted counter-doped implant to sharpen halo profile
JP4620282B2 (ja) * 2001-04-24 2011-01-26 ルネサスエレクトロニクス株式会社 半導体装置
US6822297B2 (en) * 2001-06-07 2004-11-23 Texas Instruments Incorporated Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013051175A1 (ja) * 2011-10-06 2013-04-11 パナソニック株式会社 半導体集積回路装置
JP2014132717A (ja) * 2013-01-07 2014-07-17 Seiko Epson Corp 静電気放電保護回路及び半導体回路装置

Also Published As

Publication number Publication date
US20050073009A1 (en) 2005-04-07

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