JP2005093839A - 電子回路装置の製造方法および電子回路装置 - Google Patents
電子回路装置の製造方法および電子回路装置 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000003287 optical effect Effects 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 238000003384 imaging method Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 4
- 238000005304 joining Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003909 pattern recognition Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910013641 LiNbO 3 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000002932 luster Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
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Abstract
【解決手段】一方主面上に電極11を有する回路素子10と、一方主面上に設けられた接続バンプ用電極2と認識バンプ用電極3とを有する基板1とを準備し、接続バンプ用電極2と認識バンプ用電極3とにそれぞれワイヤーボンディング法を用いて接続バンプ12と認識バンプ13とを形成する。光学的手段30を用いて撮影した認識バンプ13の画像に基づき、認識バンプ13の位置を検出し、その位置に基づき、回路素子10を接続バンプ12を介して基板1上に接合する。認識バンプ13の上部は凸形状であるため、電極3とのコントラストが得やすく、認識バンプ13の位置を正確に検出できる。
【選択図】 図7
Description
撮像した認識バンプの認識パターンの登録範囲内に認識バンプ用電極の端部が含まれないので、認識バンプの端部(縁部)を認識バンプ用電極の端部と誤認識される危険性を低減できるからである。
なお、接続バンプ用電極は接続バンプとほぼ同等の幅に形成すればよい。接続バンプを撮像した際、接続バンプ用電極の端部も同時に撮像されるので、接続バンプを認識バンプと誤認する危険性がない。また、接続バンプ用電極を狭ピッチ間隔で形成できるので、回路素子および基板を小型化できる。
α(L1 −d1 /2−δ)<L0 −d0 /2<α(L2 −d2 /2−δ)
とするのがよい。
図2の(a)は認識バンプ用電極E2および認識バンプB2を示し、(b)は接続バンプ用電極E1および接続バンプB1を示し、(c)は登録された認識パターンを示す。
図2に示すように、バンプ中心から最も近い電極エッジ部までの距離をL1 ,L2 とする。認識パターンにおいて、バンプのコントラストB0は登録エリアE0の中心に設定する。バンプ形成ずれをδとすると、バンプ外径から電極エッジ部端部までの最短距離は、
D1 =L1 −d1 /2−δ
D2 =L2 −d2 /2−δ
なお、D1 は接続バンプB1における最短距離、D2 は認識バンプB2における最短距離である。
認識パターンにおいて、バンプコントラストB0の外径から登録エリアE0端部までの最短距離は、
D0 =L0 −d0 /2
認識パターン撮像時のカメラ倍率をαとすると、以下の関係式が成り立つようにするのがよい。
αD1 <D0 <αD2
以上のようにバンプ、電極幅および認識パターンの大きさを設定すれば、認識パターンには電極端部が含まれず、バンプ位置ずれによる一致率の低下を防止できる。
回路素子および基板の小型化のため、認識バンプと接続バンプとが近い位置に形成されることがあるが、認識バンプを接続バンプより大きくすることで、接続バンプを認識バンプと誤認識する危険性をさらに低減できる。
なお、好ましくは認識バンプの大きさを接続バンプの1.5倍以上とするのがよい。
接続バンプは回路素子の外周に沿った位置に形成されるが、認識バンプは接続バンプの外側に形成されるので、回路素子を基板に搭載した時、回路素子と認識バンプとの干渉を防止でき、回路素子の接合性に影響を与えない。また、回路素子の対角線上に設けることで、角度補正、とりわけ小型回路素子における角度補正の精度が向上する。
バンプ形成時の基板の熱膨張がチップ搭載時に再現され、接続バンプとチップ電極との位置ずれを低減することができる。
この電子回路装置は、一方主面(上側主面)上に設けられた接続バンプ用電極2と認識バンプ用電極3とを有する基板1と、一方主面(下側主面)上にチップ電極11を有するチップ(回路素子)10とを備え、チップ10の電極11と接続バンプ用電極2とが接続バンプ12を介して接続されている。また、認識バンプ用電極3上には、認識バンプ13が固定されている。
図5に示すように、基板1上の電極2,3上に接続バンプ12および認識バンプ13を形成するワイヤーボンディング法は、次のように実施される。バンプ材質はAu,Al,Cuなどが使われる。
キャピラリ(ワイヤーボンディングツール)20の先端からワイヤ21を導出し、ワイヤ21の先端を電気トーチ(図示せず)によって溶融し、ボール22を形成する。ボール径は狙いのバンプ径によって異なるが、通常ワイヤ径(φ20〜30μm程度)の2〜3倍程度とするのがよい。ボール径を変更するには、主にスパーク条件で変更できる。スパーク条件(放電エネルギー等)を強くすると、Auワイヤ21先端の溶融する部分が長くなり、ボール径が大きくなる。この他に、キャピラリ20から導出するワイヤ21の長さを変えることで、ボール径を変更することもできる。
次に、最初に認識バンプ13を形成する場合には、図5の(a)のように大径なボール22を形成し、パターン認識で得られた認識バンプ用電極3上にキャピラリ20を移動させ、ボール22を押し付けるとともに、超音波を印加することで電極3上に接合する(図5の(b)参照)。この時の基板温度は25〜200℃程度、押圧荷重は400〜1200mN程度、超音波出力は50〜300mW程度、超音波印加時間は10〜50ms程度がよい。電極3に接合した後、キャピラリ20を引き上げる途中で、ワイヤ21が引きちぎられ、バンプ13が形成される。特に、ボール22が大径であるため、大径の認識バンプ13を形成できる。
後述する画像認識時の誤認識を防止するため、認識バンプ13のバンプ径は接続バンプ12のバンプ径の1.5倍以上とするのがよい。ここでは、接続バンプ12のバンプ径を60〜120μm、認識バンプ13のバンプ径を90〜180μmとした。接続バンプ数は1個のチップ当たり6〜100個程度である。
まず、登録するエリアを決定する。登録エリアは認識バンプ13のバンプ径の1〜3倍程度に設定する。
次に、既に形成されている認識バンプ13を用いて、図6に示すような認識パターンを登録する。認識パターンは二値化もしくは多値化画像として登録され、認識バンプ13と認識バンプ用電極3とが異なるコントラストにて登録される。このとき、登録された認識パターンには、認識バンプ用電極3の端部は含まれていない。
通常、認識パターンは2箇所以上登録する。角度補正精度を向上させるために、チップ10に対して略対角に位置する2つの認識バンプ13を登録することが望ましい。但し、角度補正の必要がない場合には、認識パターンを1箇所のみとしてもよい。
次に、認識バンプ13と実装中心位置との相対的な位置関係を登録する。
チップ10についても同様に、事前に認識パターンおよび認識パターンと実装中心位置の関係を登録する必要がある。チップ10の場合、認識パターンには電極などの特徴的な箇所を用いればよい。
基板1は搬送手段によって実装用ステージ32上に搬送され、吸着あるいは機械的に固定される。
実装用ステージ32の上部には、基板観察用のカメラ30が設けられ、このカメラ30によって実装位置が撮像される(図7の(a)参照)。撮像された領域において、事前に登録された認識パターンと類似する位置を検出する。
認識バンプ13はワイヤーボンディング法によって形成されているので、バンプ13の上部は凸形状を持つが、認識バンプ用電極3の上面は平坦であるため、撮像カメラ30の撮像画像には認識バンプ13と認識バンプ用電極3との明瞭なコントラストが得られる。そのため、認識バンプ13の位置を正確に検出できる。
チップ10に関しても同様の手法によりチップ中心を決定する。
認識バンプ12に基づいて決定した実装中心Oと、チップ中心とが一致するように位置補正を行うことで、各接続バンプ12の中心と各チップ電極11の中心とが一致する。
特に、バンプ12,13の形成時における基板温度とチップ10の搭載時における基板温度とをほぼ同じ温度とするのがよい。その場合には、バンプ形成時の基板1の熱膨張がチップ搭載時に再現され、基板1の接続バンプ12とチップ10の電極11との位置ずれを最小限とすることが可能になる。
本実施例では、認識バンプを接続バンプの外側でかつ回路素子の対角位置に形成したが、対角位置に限るものではない。認識バンプを接続バンプの外側に形成することで、角度補正の精度が向上しかつチップ実装時に認識バンプがチップと干渉するのを防止できる。
なお、認識バンプを接続バンプの内側、つまりチップ搭載部の範囲内に形成することもできる。この場合には、バンプ形成に要するエリアを小さくできるため、実装領域の小型化に寄与する。但し、チップ実装時に認識バンプがチップと干渉しないように、認識バンプの高さを接続バンプより低くするのがよい。
認識バンプ用電極の形状は、実施例のような円形のほか、四角形、長方形など如何なる形状であってもよい。また、認識バンプ用電極は島状電極に限らず、いずれかの接続バンプ用電極や別の電極とパターン接続されたものでもよい。
2 接続バンプ用電極
3 認識バンプ用電極
10 回路素子(チップ)
11 チップ電極
12 接続バンプ
13 認識バンプ
20 キャピラリ(ワイヤーボンディングツール)
21 ワイヤ
22 ボール
30 カメラ(光学的手段)
31 フリップチップボンダ
Claims (7)
- 一方主面上に電極を有する回路素子と、一方主面上に設けられた接続バンプ用電極と認識バンプ用電極とを有する基板とを準備する工程と、
上記接続バンプ用電極と上記認識バンプ用電極とにそれぞれワイヤーボンディング法を用いて接続バンプと認識バンプとを連続的に形成する工程と、
光学的手段を用いて撮影した上記認識バンプの画像に基づき、上記認識バンプの位置を検出する工程と、
上記認識バンプの位置に基づき、上記回路素子を上記接続バンプを介して上記基板上に接合する工程と、を有することを特徴とする電子回路装置の製造方法。 - 上記認識バンプ用電極は、上記光学的手段を用いて上記認識バンプを撮影する際、認識パターンとして登録される範囲内に上記認識バンプ用電極の端部が含まれない十分な幅寸法を有することを特徴とする請求項1に記載の電子回路装置の製造方法。
- 上記認識バンプ用電極とその登録パターンとはほぼ相似形であり、接続バンプ用電極におけるバンプ中心から最も近い電極エッジ部までの距離をL1 、接続バンプの径をd1 、認識バンプ用電極におけるバンプ中心から最も近い電極エッジ部までの距離をL2 、認識バンプの径をd2 、登録パターンにおける認識バンプのコントラストの径をd0 、登録パターンの幅を2L0 、バンプ形成精度を±δ、撮像時の光学的手段の倍率をαとすると、
α(L1 −d1 /2−δ)<L0 −d0 /2<α(L2 −d2 /2−δ)
としたことを特徴とする請求項1または2に記載の電子回路装置の製造方法。 - 上記認識バンプの直径を、上記接続バンプの直径より大きくしたことを特徴とする請求項1ないし3のいずれかに記載の電子回路装置の製造方法。
- 上記認識バンプは、上記回路素子の搭載部分の外側であって、かつ回路素子の対角線上に少なくとも2箇所に設けられていることを特徴とする請求項1ないし4のいずれかに記載の電子回路装置の製造方法。
- 上記接続バンプおよび上記認識バンプを形成する工程と、上記回路素子を上記接続バンプを介して上記基板上に接合する工程は、それぞれ上記基板が略同じ温度で実施されることを特徴とする請求項1ないし5のいずれかに記載の電子回路装置の製造方法。
- 請求項1ないし6のいずれかに記載の製造方法を用いて製造されたことを特徴とする電子回路装置。
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Cited By (6)
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US7514802B2 (en) | 2005-09-30 | 2009-04-07 | Panasonic Corporation | Wiring board |
US7642662B2 (en) | 2006-12-12 | 2010-01-05 | Shinko Electric Industries Co., Ltd. | Semiconductor device and method of manufacturing the same |
KR20140075593A (ko) | 2012-12-10 | 2014-06-19 | 삼성전자주식회사 | 인식 장치, 인식 방법, 실장 장치 및 실장 방법 |
JP2014183162A (ja) * | 2013-03-19 | 2014-09-29 | Panasonic Corp | 積層パッケージの製造システムおよび製造方法 |
US9319593B2 (en) | 2012-12-10 | 2016-04-19 | Samsung Electronics Co., Ltd. | Recognition apparatus, recognition method, mounting apparatus, and mounting method |
JP2018019286A (ja) * | 2016-07-28 | 2018-02-01 | 太陽誘電株式会社 | 電子デバイスおよびその製造方法 |
Families Citing this family (7)
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JP4615117B2 (ja) * | 2000-11-21 | 2011-01-19 | パナソニック株式会社 | 半導体ウエハへのバンプ形成方法及びバンプ形成装置 |
JP4709535B2 (ja) * | 2004-11-19 | 2011-06-22 | 株式会社東芝 | 半導体装置の製造装置 |
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Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1034463A (zh) | 1988-01-18 | 1989-08-02 | 雷伊化学公司 | 电子元件的互连 |
US5347428A (en) * | 1992-12-03 | 1994-09-13 | Irvine Sensors Corporation | Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip |
JPH0936164A (ja) * | 1995-07-21 | 1997-02-07 | Mitsubishi Electric Corp | 半導体製造装置および半導体装置の製造方法 |
JP3153755B2 (ja) | 1995-12-27 | 2001-04-09 | 松下電子工業株式会社 | 半導体装置の製造方法 |
US5696031A (en) * | 1996-11-20 | 1997-12-09 | Micron Technology, Inc. | Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
JP3284048B2 (ja) | 1996-05-31 | 2002-05-20 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
EP0954208A4 (en) * | 1996-12-27 | 2002-09-11 | Matsushita Electric Ind Co Ltd | METHOD AND DEVICE FOR FIXING AN ELECTRONIC COMPONENT ON A CIRCUIT BOARD |
SG71734A1 (en) * | 1997-11-21 | 2000-04-18 | Inst Materials Research & Eng | Area array stud bump flip chip and assembly process |
US6593168B1 (en) * | 2000-02-03 | 2003-07-15 | Advanced Micro Devices, Inc. | Method and apparatus for accurate alignment of integrated circuit in flip-chip configuration |
JP4601128B2 (ja) | 2000-06-26 | 2010-12-22 | 株式会社光波 | Led光源およびその製造方法 |
US6908845B2 (en) * | 2002-03-28 | 2005-06-21 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
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JP2014183162A (ja) * | 2013-03-19 | 2014-09-29 | Panasonic Corp | 積層パッケージの製造システムおよび製造方法 |
JP2018019286A (ja) * | 2016-07-28 | 2018-02-01 | 太陽誘電株式会社 | 電子デバイスおよびその製造方法 |
US10199562B2 (en) | 2016-07-28 | 2019-02-05 | Taiyo Yuden Co., Ltd. | Electronic device and method of fabricating the same |
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