CN100352027C - 电子电路器件的制造方法和电子电路器件 - Google Patents
电子电路器件的制造方法和电子电路器件 Download PDFInfo
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Abstract
提供了一种在其一主表面上具有电极的电路元件和在其一主表面上具有连接凸起电极和识别凸起电极的基片。用引线接合法,在连接凸起电极和识别凸起电极上形成连接凸起和识别凸起。根据由光学设备拾取识别凸起的图象,检测识别凸起的位置,并根据检测到的识别凸起的位置,通过连接凸起将电路元件连接至基片。因为识别凸起的上部成凸状,可以容易地获得相对于识别凸起电极的对比度,并可正确地检测到识别凸起的位置。
Description
(1)技术领域
本发明涉及电子电路器件的制造方法,其中,通过使用引线接合法形成的凸起将电路元件连接到基片上,并将电路元件与电路器件连接。
(2)背景技术
近年来,为了制造高性能、小型化和薄的(low-profile)便携式电话、个人电脑等等,倒装芯片法被越来越多地采用。凸起配备在基片或芯片上(电路元件)。
根据已知技术,为了用凸起将芯片安装在基片上,将一部分基片布线图记录为识别图并记录识别图和安装中心位置之间的相关位置以确定该芯片的安装位置。在将芯片安装在基片上时,为了实现好的导电,最好使芯片的电极的中心与连接凸起的中心相一致。
然而,当将烧结的陶瓷基片或树脂基片用作基片时,因为形成布线图的精确度约为30μm,这种参照布线图确定芯片的安装位置的技术引起芯片电极和连接凸起之间的空间位移。
日本未经审查的专利申请公开号9-181098提出一种半导体装置,其中,通过引线接合法在基片的电极上形成连接凸起,通过这些连接凸起安装芯片,在基片的芯片安装位置的外部与芯片相对的对角线上的两个位置上的形成识别标志,且通过识别标志识别基片和芯片之间的空间关系,以安装芯片。
然而,上述识别标志是通过例如在基片上涂上墨水形成的。即,识别标志和连接凸起是通过非常不同的过程形成的。并不总是在基片电极的固定位置上形成连接凸起,会发生一些位移。因此,识别标志和连接凸起之间的相对位置是变化的,并且即使将芯片参照识别标志安装,也不能减少芯片电极的中心与连接凸起的中心之间的空间位移。
日本未经审查的专利申请公开号2002-9347提出一种技术,其中识别标志和连接凸起是通过电镀法同时在基片的电极上形成的,且识别凸起被记录成识别图来确定安装芯片的位置。在此情况下,形成凸起的精确度为约±5μm,因为这比布线的精确度更高,所以有减少芯片电极的中心与连接凸起的中心之间的空间位移的优点。
为了执行识别凸起的图象识别,从光源将光施加在基片上,通过照相机捕获从基片反射的光,并可通过以二进制或多级方式表示反射光的强度来获得识别对象的对比度。这里,施加到基片上的光是通过外照明或环照明施加的与照相机具有同一轴的垂直光。
但电镀凸起具有实质上平坦的上表面。当将电镀凸起用作识别凸起时,从上表面反射的光具有与从识别凸起电极反射的光相同的强度。因此,即使以二进制形式表示由照相机拾取的反射光,也不能在识别凸起和识别凸起电极之间获得对比度,这引起不能精确地检测到识别凸起的位置的问题。
(3)发明内容
根据以上问题,本发明提供一种制造电子电路器件的方法,其中通过增加形成凸起的精确度减少了芯片的电极的中心与连接凸起的中心之间的空间位移,藉此,当执行识别凸起的图象识别时,很容易获得对比度。本发明还针对由此方法制造的电子电路器件。
根据本发明的第一方面,电子电路器件的制造方法包括以下步骤:准备在其一个主表面上具有电极的电路元件和具有在其一个主表面上提供的连接凸起电极及识别凸起电极的基片;通过使用引线接合法(最好是连续地)在连接凸起电极和识别凸起电极上分别形成连接凸起和识别凸起;根据使用光学设备拾取的识别凸起的图象,检测识别凸起的位置;并将根据检测到的识别凸起位置,通过连接凸起将电路元件连接到基片上。
本发明的一个特征是连接凸起和识别凸起是通过引线接合法形成的,且识别凸起被用作确定电路元件的安装位置的识别图形。连接凸起和识别凸起最好是连续地形成。“连续地”是意思是通过识别基片图形一次形成连接凸起和识别凸起。形成连接凸起和标识凸起的次序是可以变更的。可以先形成一种类型的凸起(例如:识别凸起),然后形成另一种类型的凸起(例如:连接凸起)。当连续地形成凸起时,形成凸起的精确度约为±10μm,比在将烧结的陶瓷基片和树脂基片用作基片时的±30μm的形成布线图形的正确度高。因此,可减少芯片的电极的中心与连接凸起的中心之间的空间位移。
本发明的另一特征是用于空间位移的识别凸起的形状与电镀凸起的形状不同,特别是上表面不是平的。在图1A所示的电镀凸起的情况下,当凸起和电极都是由金属制成且它们的上表面都是平的时候,即使它们的组成材料各不相同,因为金属光泽,返回到光学设备的反射光具有相同的强度。因此,对比度低。另一方面,众所周知,用导线凸起,初始球是通过在金属线(例如:金丝)尖端产生火花而形成的,且在将该球连接至电极后,通过扯开导线形成凸起。因此,如图1B所示,识别凸起的上部成凸状,并在凸起的上部将来自光学设备的垂直光反射开去。因此,从识别凸起反射到光学设备的光比来自识别凸起电极的反射光弱,从而它们之间的对比度很强。可以通过处理由光学设备拾取的反射光,正确地识别该识别凸起的位置,以产生二进制的或多级的表示。即,可以将电路元件精确地并正确地安装在基片上。
在本发明中,最好是识别凸起电极具有足够的宽度,这样在使用光学设备将识别凸起的图象拾取时,识别凸起电极的边缘部分不包含在被记录成识别图形的区域中。这是为了降低将识别凸起的端部(边缘部分)错误地认作识别凸起电极的端部的危险。
另外,连接凸起电极可能具有与连接凸起实质上相同宽度。当将连接凸起的图象拾取时,因为连接凸起电极的端部的图象被同时拾取,所以没有将连接凸起错误地认作识别凸起的危险。另外,因为所形成的连接凸起电极具有窄的间隔,所以可减小电路元件和基片的尺寸。
在本发明中,在几何上,识别凸起电极与记录的识别图形实质上相似。当从连接凸起电极中的连接凸起的中心到连接凸起电极的边缘部分(与连接凸起最近的)的距离为L1,连接凸起的直径为d1,从识别凸起电极中的识别凸起的中心到识别凸起电极的边缘部分(与识别凸起最近的)的距离为L2,识别凸起的直径为d2,记录的识别图形中的识别凸起的对比区域的直径为d0,记录的识别图形的宽度为2L0,制作凸起的精度为±d,且在拾取图象时光学设备的放大倍率为a时,最好保持以下关系:
a (L1-d1/2-d)<L0-d0/2<a(L2-d2/2-d)。
图2A示出识别凸起电极E2和识别凸起B2,图2B示出连接凸起电极E1和连接凸起电极B1,而图2C示出记录的识别图形。如图2A-2C所示,当到与凸起的中心最近的边缘的距离为L1和L2,将凸起的对比度B0设置在识别图形中记录的区域E0的中心,且当用于形成凸起的位移为d时,从凸起的外部直径至电极的端部的最短距离表示如下:
D1=L1-d1/2-d
D2=L2-d2/2-d
另外,D1为连接凸起B1所定义的最短距离,且D2为识别凸起B2所定义的最短的距离。在识别图形中,从凸起(对比度B0)的外部直径到记录的区域E0的端部的最短距离为:
D0=L0-d0/2。
当拾取识别图形的图象时照相机的放大倍率为a时,以下公式最好有效:
aD1<D0<aD2。
如上所述,在设置凸起的尺寸,电极的宽度和识别图形的尺寸时,电极的端部不包括在识别图形中,可以防止由凸起的空间位移引起的一致性的降级。
在本发明中,可以将识别凸起的直径做得比连接凸起的直径大。甚至在为了使电路元件和基片更小而使识别凸起和连接凸起形成得靠近对方时,通过将识别凸起做得比连接凸起大,从而降低了将连接凸起错误地认作识别凸起的危险。另外,最好将识别凸起做得比连接凸起大至少1.5倍。
在本发明中,最好在安装电路元件的区域外部和与电路元件相对的对角线上的两个或更多位置上提供识别凸起。因为连接凸起是沿电路元件的外边缘形成的,并且因为电路元件安装在基片上,所以可以防止电路元件和识别凸起之间的干扰并对电路元件的连接没有影响。另外,因为在相对于电路元件的对角线上提供了识别凸起,角度修正,特别是小电路元件的角度修正的精确度提高了。
在本发明中,基片最好在基本上同一温度时执行以下各步骤:形成连接凸起和识别凸起的步骤,和通过连接凸起将电路元件连接至基片的步骤。在安装芯片时重复形成凸起时基片的热膨胀,从而可减少连接凸起和芯片电极之间的空间位移。
在本发明中,当使用根据本发明的制造方法制造电子电路器件时,连接凸起和芯片电极之间的空间位移减少了,避免了基片和电路元件之间的传导故障,还可以生产具有高可靠性的电子电路器件。
根据本发明,在用引线接合法连续地形成连接凸起和识别凸起,并将识别凸起用作识别图形以确定电路元件的安装位置时,形成凸起的精确度提高了,并且可减少芯片的电极的中心与连接凸起的中心之间的空间位移。另外,因为用于空间识别的识别凸起是通过引线接合法形成的,可以容易地在图象识别中,获得识别凸起和识别凸起电极之间的对比度,并识别该识别凸起的位置。因此,可以将电路元件精确地和正确地安装在基片上。
本发明的其它特征和优点将从以下参照附图对本发明实施例的说明中明显地看出。
(4)附图说明
图1A和1B示出电镀凸起的图象识别和导线凸起的图象识别之间的不同;
图2A-2C示出凸起、电极和识别图形的尺寸是如何设置的;
图3为由根据本发明的制造方法制造的电子电路器件的第一实施例的剖视图;
图4为图3所示的电子电路器件的基片的顶视图;
图5A-5E示出如何用引线接合法形成凸起;
图6示出识别凸起的识别图形;和
图7A和7B示出空间识别过程和安装过程。
(5)具体实施方式
以下参照实施例描述本发明。图3和4示出由根据本发明的制造方法制造的电子电路器件的一个实施例。在该电子电路器件中,在其一主表面(上主表面)上设有连接凸起电极2和识别凸起电极3的基片1,并在其一主表面(下主表面)上设有芯片电极11的芯片(电路元件)10,并通过连接凸起12将芯片10的电极11连接到连接凸起电极2。另外,识别凸起13固定在识别凸起电极3上。
基片1是由诸如玻璃环氧树脂等等之类的树脂基片或由氧化铝等等制成的烧结的基片组成。在基片1的上表面上,沿芯片安装位置形成多个连接凸起电极2,并在芯片安装位置外部和沿芯片安装位置的对角线的两个位置上形成识别凸起电极。这些电极2和3可具有例如Au/Ni/Cu的多层结构或单层结构。材料不重要。连接凸起电极2的宽度在约80-120μm的范围内,布线的厚度在约15-50μm的范围内。形成布线图形中的宽度方向中的精确度约为±30μm。识别凸起电极3的布线宽度制成识别凸起13的直径的2-10倍大。当安装区域不需要大辐减少时,可以将宽度设置成10倍大或更大。这里,虽然识别凸起电极3是圆的,也可以将它们制成方的。识别凸起电极3的布线厚度大约与连接凸起电极2的相同。为了提高生产力,在基片1上形成多个连接凸起电极2和识别凸起电极3的相同图形,并在安装芯片后将图形分开。另外,虽然未示出,存在为了将表面安装部分安装在基片1上可提供其它电极的情况。
芯片10可以是由例如Si、GaAS等制成的半导体元件,或由例如LiTaO3、LiNbO3、石英等制成的表面波元件。芯片的一侧为1-3mm。芯片电极是由Al、Au等制成的,且电极的厚度约为1-2μm。芯片被预先分开。
接着,参照图5-7描述具有上述结构的电子电路器件的制造方法。
如图5A-5E所示,如下所述执行在基片1上的电极2和3上形成连接凸起12和识别凸起13的引线接合法。凸起的材料是Au、Al、Cu等。导线21从毛细管(导线接合上具)的尖端引出,并用电子焊枪将导线21的尖端熔化,以形成一个球22。可根据拟对准的凸起的直径调节球的直径。球的直径通常约为导线直径(直径约为20-30μm)的2-3倍大。可以通过改变电火花条件来改变球的直径。当电火花条件(放电能量等)增加时,在金丝尖端的熔化长度变长而球的直径变大。另外,可以通过改变从毛细管引出的导线21的长度改变球的直径。
首先,执行基片1的图形识别并确定形成凸起12和13的位置。然后,形成识别凸起13。如图5A所示形成大直径的球22,将毛细管20移到通过图形识别获得的识别凸起电极3的上方,并通过施加一个超声波将将球22按下并连接至电极3(见图5B)。此时,最好是基片1的温度为25-200℃左右,压力重量为400-1200mN左右,超声波的输出为50-300mW左右,施加超声波的时间为10-50ms。在将球22连接到电极3之后,将毛细管20拉起,将导线21扯出并形成凸起13。特别是因为球22具有大的直径,所以能形成具有大直径的识别凸起13。见图5C。
其次,如图5C所示,将毛细管20或基片1水平移动固定距离,在导线21的尖端形成具有小直径的球22,并将球22连接至连接凸起电极2以形成小直径的连接凸起12(见图5D和5E)。形成凸起的精确度约为±10μm。
为了防止以下将描述的图象识别步骤中的错误识别,识别凸起13的直径最好至少是连接凸起12的直径的1.5倍大。这里,连接凸起12的直径被制成60-120μm而识别凸起13的直径被制成90-180μm。连接凸起的数量为每个芯片6-100左右。
其次,为了确定在基片1上的芯片的安装位置,预先记录了识别图形及识别图形和安装中心位置之间的关系。首先确定用于记录的区域。将用于记录的区域设置成识别凸起13的直径的一至三倍大。然后,通过使用已形成的识别凸起13记录如图6所示的识别图形。将识别图形记录成二进制图象或多级图象,并记录识别凸起13和识别凸起电极3以具有不同的对比度。此时,识别凸起电极3的端部不包括在记录的识别图形中。通常,记录在两个或更多位置上的识别图形。为了提高角度修正的精确度,最好沿与芯片10相对的实质上的对角线记录两个识别凸起13。然而,当不需要角度修正时,可仅提供一个识别图形。然后,记录识别凸起13和安装中心位置之间的相对位置。还是关于芯片10,同样地,对拟记录的识别图形及识别图形和安装中心位置之间的关系进行记录。在芯片10的情况中,可将诸如电极等等之类的特征位置用作识别图形。
其次,参照图7A和7B对识别和安装方法进行描述。通过传输设备将基片1传输至安装板32并用抽气或任何合适的机械方法将其固定。在安装板的上方提供用于观察基片的照相机30,并通过照相机30拾取安装位置的图象(见图7A)。在拾取图象的区域中,检测到与预先记录的识别图形相近的位置。因为识别凸起13是通过引线接合法形成的,所以识别凸起13的上部为凸状。因此,因为识别凸起电极3的上表面是平的,可以在照相机30拾取的图象中获得识别凸起13和识别凸起电极3之间的清楚的对比度。因此,可以正确地检测到识别凸起13的位置。
在识别图形中,为了不包括识别凸起电极3的端部,将识别凸起电极3制成比连接凸起电极2大。这里,凸起、电极和识别图形的尺寸是根据图2A-2C所描述的计算公式确定的。因为电极不是这样包括在识别图象中的,所以没有由于凸起的位移而引起的一致率的下降。表1示出识别凸起和一致率之间的关系。另外,连接凸起和识别凸起都制成直径为100μm。
表1
识别凸起和一致率之间的关系
凸起的位移 | 5 | 10 | 20 | 30 | … | 80 |
连接凸起电极的宽度:100μm识别凸起电极的宽度:100μm | 88% | 75% | 50% | … | … | … |
连接凸起电极的宽度:100μm识别凸起电极的宽度:500μm | 90% | 90% | 90% | 90% | … | 89% |
(连接凸起和识别凸起都制成直径为100μm。)
如从表1清楚地理解到的那样,当将连接凸起电极2和识别凸起电极3的布线宽度都制成100μm时,一致率,在用于形成识别凸起13的位置位移20μm时,下降至50%。另一方面,当将连接凸起电极2的布线宽度制成100μm并将识别凸电极3的布线宽度制成500μm时,即使将用于形成识别凸起13的位置位移80μm,一致率仅下降至89%。因此,可以防止错误的识别。
基片上的安装中心O是根据检测到的识别凸起13和预先记录的识别图形和安装中心之间的空间关系确定的。关于芯片10,芯片的中心是以同一方式确定的。由于执行了空间修正,各连接凸起12的中心与各芯片电极11的中心相一致,这样根据识别凸起13确定的安装中心O可与芯片中心相一致。
如图7B所示,在空间修正后,通过使用倒装芯片接合器31将芯片10安装在基片1上。该安装的精确度为±15μm左右。此时,对基片加热,使其在约为室温至200℃的范围内,将芯片10加热至室温到300℃之间的一个温度,并将0.5-2N/bump的压力施加到芯片10。可以在安装期间将超声波施加到芯片10上。特别是安装芯片10时的基片温度最好与形成凸起12和13时的基片温度实质上相等。在该情况下,安装芯片时重复在形成凸起时基片的热膨胀,这样就可使基片1的连接凸起12和芯片10的电极11之间的位移最小化。
当在上述过程中在基片1上安装芯片10时,因为通过引线接合法形成的识别凸起13被用作用于确定芯片10的安装位置的识别图形,所以可将芯片电极11的中心制成与连接凸起2的中心相一致,并且当与将基片的布线图形用作识别图形的情况相比,可减少空间位移。
在以上实施例中,虽然在将识别凸起的尺寸制成比连接凸起的尺寸大时,错误识别连接凸起的危险低,还可将识别凸起制成和连接凸起一样小。另外,即使在将识别凸起制成比连接凸起小时,也可降低错误识别的危险。
在本实施例中,虽然识别凸起是在连接凸起的外部并沿与电路元件相对的对角线形成的,它们并不限于沿对角线。在连接凸起外部形成识别凸起时安装芯片时,可提高角度修正的精确度并防止识别凸起和芯片之间的干扰。另外,还可在连接凸起内部形成识别凸起;即,可在安装芯片的区域之内形成识别凸起。在此情况下,因为可使形成凸起所需的面积更小,有助于减少安装面积。然而,最好是使识别凸起低于连接凸起,这样在安装芯片时,在识别凸起和芯片之间就可以没有干扰了。
除了如本实施例中的圆形外,识别凸起的形状可以是诸如立方体、矩形之类的任何形状。另外,识别凸起电极不限于岛形电极,还可以是连接到凸起电极和其它电极中的任何一个的图形。
虽然本发明是就其特定实施例加以描述的,许多其它变化和修改及其它运用将对那些本领域的技术人员变得明显。因此,本发明不是由这里的特定揭示所限定的。
Claims (14)
1.一种电子电路器件的制造方法,其特征在于,包括以下步骤:
准备在其一主表面上具有电极的电路元件并准备在其一主表面上具有连接凸起电极和识别凸起电极的基片;
用引线接合法,在连接凸起电极和识别凸起电极上分别形成连接凸起和识别凸起;
根据由光学设备拾取识别凸起的图象,检测识别凸起的位置;和
根据检测到的识别凸起的位置,通过连接凸起将电路元件连接至基片。
2.如权利要求1所述的电子电路器件的制造方法,其特征在于,连续地执行所述形成步骤。
3.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述连接凸起都是在所述识别凸起形成之前形成的。
4.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述识别凸起都是在所述连接凸起形成之前形成的。
5.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述识别凸起电极具有足够的宽度,以使得在光学设备拾取识别凸起时,识别凸起电极的边缘部分不包括在记录成识别图形的区域内。
6.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述识别凸起电极比所述连接凸起电极大。
7.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述连接凸起电极具有与所述连接凸起实质上相同的宽度。
8.如权利要求1所述的电子电路器件的制造方法,其特征在于,在几何上,所述识别凸起电极与记录的识别图形实质上相似,当从连接凸起电极中的连接凸起的中心到与连接凸起最近的边缘部分的距离为L1,连接凸起的直径为d1,从识别凸起电极中的识别凸起的中心到与识别凸起电极最近的边缘部分的距离为L2,识别凸起的直径为d2,记录的识别图形中的识别凸起的对比区域的直径为d0,记录的识别图形的宽度为2L0,制作凸起的精度为±d,且在拾取图象时光学设备的放大倍率为a时,保持以下关系:
aD<D0<aD2
其中:
D=L1-d1/2-d
D2=L2-d2/2-d
D0=L0-d0/2
9.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述识别凸起的直径比所述连接凸起的直径大。
10.如权利要求9所述的电子电路器件的制造方法,其特征在于,所述识别凸起的所述直径至少是所述连接凸起的直径的1.5倍大。
11.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述识别凸起在安装电路元件的区域的外部并被设在电路元件的对角线上的两个或更多位置上。
12.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述形成连接凸起和识别凸起的步骤和通过连接凸起将电路元件连接至基片的步骤,在基片处在同一温度时执行。
13.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述电路元件为半导体元件或表面波元件。
14.如权利要求1所述的电子电路器件的制造方法,其特征在于,所述基片为树脂基片或烧结的基片。
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JP4615117B2 (ja) * | 2000-11-21 | 2011-01-19 | パナソニック株式会社 | 半導体ウエハへのバンプ形成方法及びバンプ形成装置 |
JP4709535B2 (ja) * | 2004-11-19 | 2011-06-22 | 株式会社東芝 | 半導体装置の製造装置 |
JP4068635B2 (ja) | 2005-09-30 | 2008-03-26 | 松下電器産業株式会社 | 配線基板 |
JP5049573B2 (ja) | 2006-12-12 | 2012-10-17 | 新光電気工業株式会社 | 半導体装置 |
US7875988B2 (en) * | 2007-07-31 | 2011-01-25 | Seiko Epson Corporation | Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
KR100924552B1 (ko) * | 2007-11-30 | 2009-11-02 | 주식회사 하이닉스반도체 | 반도체 패키지용 기판 및 이를 갖는 반도체 패키지 |
US20100133671A1 (en) * | 2008-12-02 | 2010-06-03 | Chung Hsing Tzu | Flip-chip package structure and the die attach method thereof |
KR101258394B1 (ko) | 2010-05-19 | 2013-04-30 | 파나소닉 주식회사 | 반도체 발광 소자의 실장 방법과 실장 장치 |
US9319593B2 (en) | 2012-12-10 | 2016-04-19 | Samsung Electronics Co., Ltd. | Recognition apparatus, recognition method, mounting apparatus, and mounting method |
JP2014116467A (ja) | 2012-12-10 | 2014-06-26 | Samsung R&D Institute Japan Co Ltd | 認識装置、認識方法、実装装置及び実装方法 |
JP6167412B2 (ja) * | 2013-03-19 | 2017-07-26 | パナソニックIpマネジメント株式会社 | 積層パッケージの製造システムおよび製造方法 |
JP6556105B2 (ja) * | 2016-07-28 | 2019-08-07 | 太陽誘電株式会社 | 電子デバイスの製造方法 |
CN106255346A (zh) * | 2016-08-24 | 2016-12-21 | 山东蓝色电子科技有限公司 | 一种层间互连工艺 |
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