JP2005038971A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2005038971A
JP2005038971A JP2003198663A JP2003198663A JP2005038971A JP 2005038971 A JP2005038971 A JP 2005038971A JP 2003198663 A JP2003198663 A JP 2003198663A JP 2003198663 A JP2003198663 A JP 2003198663A JP 2005038971 A JP2005038971 A JP 2005038971A
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Japan
Prior art keywords
wiring
insulating film
barrier layer
semiconductor device
alloy
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Withdrawn
Application number
JP2003198663A
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English (en)
Japanese (ja)
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JP2005038971A5 (enExample
Inventor
Hiroaki Inoue
裕章 井上
Akira Suzaki
明 須崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
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Ebara Corp
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Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Priority to JP2003198663A priority Critical patent/JP2005038971A/ja
Priority to US10/893,244 priority patent/US7157370B2/en
Publication of JP2005038971A publication Critical patent/JP2005038971A/ja
Publication of JP2005038971A5 publication Critical patent/JP2005038971A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2003198663A 2003-07-17 2003-07-17 半導体装置及びその製造方法 Withdrawn JP2005038971A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003198663A JP2005038971A (ja) 2003-07-17 2003-07-17 半導体装置及びその製造方法
US10/893,244 US7157370B2 (en) 2003-07-17 2004-07-19 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003198663A JP2005038971A (ja) 2003-07-17 2003-07-17 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2005038971A true JP2005038971A (ja) 2005-02-10
JP2005038971A5 JP2005038971A5 (enExample) 2006-08-24

Family

ID=34113600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003198663A Withdrawn JP2005038971A (ja) 2003-07-17 2003-07-17 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US7157370B2 (enExample)
JP (1) JP2005038971A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013145899A (ja) * 2006-05-22 2013-07-25 Samsung Electronics Co Ltd Ｍｉｍキャパシタを含む半導体集積回路素子およびその製造方法
JP2014236177A (ja) * 2013-06-05 2014-12-15 日本電信電話株式会社 配線構造とその形成方法

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TWI286814B (en) * 2003-04-28 2007-09-11 Fujitsu Ltd Fabrication process of a semiconductor device
JP2006202852A (ja) * 2005-01-18 2006-08-03 Toshiba Corp 半導体装置
US7138714B2 (en) * 2005-02-11 2006-11-21 International Business Machines Corporation Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines
TWI256105B (en) * 2005-02-17 2006-06-01 Touch Micro System Tech Method of forming chip type low-k dielectric layer
US7913644B2 (en) * 2005-09-30 2011-03-29 Lam Research Corporation Electroless deposition system
US7709269B2 (en) * 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US7592211B2 (en) * 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
WO2007089495A1 (en) * 2006-01-31 2007-08-09 Advanced Micro Devices, Inc. A semiconductor device comprising a metallization layer stack with a porous low-k material having an enhanced integrity
DE102006004429A1 (de) * 2006-01-31 2007-08-02 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem Metallisierungsschichtstapel mit einem porösen Material mit kleinem ε mit einer erhöhten Integrität
KR100727691B1 (ko) * 2006-06-20 2007-06-13 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 제조 방법
US20080054466A1 (en) * 2006-08-31 2008-03-06 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing semiconductor device
JP4539684B2 (ja) * 2007-06-21 2010-09-08 株式会社デンソー 炭化珪素半導体装置およびその製造方法
US20130217225A1 (en) * 2010-08-31 2013-08-22 Tokyo Electron Limited Method for manufacturing semiconductor device
US8518818B2 (en) 2011-09-16 2013-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse damascene process
US9209082B2 (en) * 2014-01-03 2015-12-08 International Business Machines Corporation Methods of localized hardening of dicing channel by applying localized heat in wafer kerf
EP3172761B1 (en) 2014-07-25 2021-09-22 Intel Corporation Tungsten alloys in semiconductor devices
US9431343B1 (en) 2015-03-11 2016-08-30 Samsung Electronics Co., Ltd. Stacked damascene structures for microelectronic devices
CN106409754B (zh) * 2015-07-29 2020-03-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其制造方法
WO2017087005A1 (en) * 2015-11-21 2017-05-26 Intel Corporation Metallization stacks with enclosed vias
US9899260B2 (en) * 2016-01-21 2018-02-20 Micron Technology, Inc. Method for fabricating a semiconductor device
US10535560B2 (en) * 2017-07-18 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure of semiconductor device
CN109411406A (zh) * 2017-08-18 2019-03-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10600656B2 (en) * 2017-11-21 2020-03-24 International Business Machines Corporation Directed self-assembly for copper patterning
WO2019135985A1 (en) * 2018-01-03 2019-07-11 Corning Incorporated Methods for making electrodes and providing electrical connections in sensors

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Publication number Priority date Publication date Assignee Title
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
US6815329B2 (en) * 2000-02-08 2004-11-09 International Business Machines Corporation Multilayer interconnect structure containing air gaps and method for making
US6555909B1 (en) * 2001-01-11 2003-04-29 Advanced Micro Devices, Inc. Seedless barrier layers in integrated circuits and a method of manufacture therefor
US6555467B2 (en) * 2001-09-28 2003-04-29 Sharp Laboratories Of America, Inc. Method of making air gaps copper interconnect
JP3778045B2 (ja) * 2001-10-09 2006-05-24 三菱電機株式会社 低誘電率材料の製造方法および低誘電率材料、並びにこの低誘電率材料を用いた絶縁膜および半導体装置
JP4555540B2 (ja) * 2002-07-08 2010-10-06 ルネサスエレクトロニクス株式会社 半導体装置
TWI313066B (en) * 2003-02-11 2009-08-01 United Microelectronics Corp Capacitor in an interconnect system and method of manufacturing thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013145899A (ja) * 2006-05-22 2013-07-25 Samsung Electronics Co Ltd Ｍｉｍキャパシタを含む半導体集積回路素子およびその製造方法
JP2014236177A (ja) * 2013-06-05 2014-12-15 日本電信電話株式会社 配線構造とその形成方法

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Publication number Publication date
US7157370B2 (en) 2007-01-02
US20050029669A1 (en) 2005-02-10

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