JP2005033160A - 半導体素子の銅配線形成方法 - Google Patents
半導体素子の銅配線形成方法 Download PDFInfo
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- JP2005033160A JP2005033160A JP2003389232A JP2003389232A JP2005033160A JP 2005033160 A JP2005033160 A JP 2005033160A JP 2003389232 A JP2003389232 A JP 2003389232A JP 2003389232 A JP2003389232 A JP 2003389232A JP 2005033160 A JP2005033160 A JP 2005033160A
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- copper
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- insulating film
- copper wiring
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 114
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 109
- 239000010949 copper Substances 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 88
- 238000009792 diffusion process Methods 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 43
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 238000005498 polishing Methods 0.000 claims abstract description 23
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 16
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 230000002265 prevention Effects 0.000 claims description 22
- 238000009413 insulation Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 229910052790 beryllium Inorganic materials 0.000 claims description 3
- 229910052793 cadmium Inorganic materials 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical class N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 2
- 239000005751 Copper oxide Substances 0.000 claims description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 229910000431 copper oxide Inorganic materials 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 60
- 239000000463 material Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000013508 migration Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical class [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910004012 SiCx Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
【解決手段】基板上に第1層間絶縁膜及び研磨停止層を形成する段階と、前記研磨停止層及び第1層間絶縁膜をエッチングしてダマシンパターンを形成する段階と、前記ダマシンパターンを含んだ前記研磨停止層上に銅拡散防止導電膜及び銅層を形成する段階と、前記ダマシンパターン内に銅配線を形成する段階と、前記銅配線を含んだ全体構造の表面に金属元素ドーピング層を形成する段階と、前記金属元素ドーピング層が形成された全体構造上に銅拡散防止絶縁膜及び第2層間絶縁膜を形成し、これらの絶縁膜蒸着時の熱によって前記銅配線と前記銅拡散防止絶縁膜との界面には銅合金層及び酸化金属層が形成され、前記銅配線の周辺層と前記銅拡散防止絶縁膜との界面には酸化金属層が形成される段階とを含む。
【選択図】 図2
Description
12 …第1層間絶縁膜
13 …研磨停止層
14 …ダマシンパターン
15 …銅拡散防止導電膜
16 …銅配線
17 …銅拡散防止絶縁膜
18 …第2層間絶縁膜
21 …基板
22 …第1層間絶縁膜
23 …研磨停止層
24 …ダマシンパターン
25 …銅拡散防止導電膜
26 …銅配線
27 …銅拡散防止絶縁膜
28 …第2層間絶縁膜
200 …金属元素ドーピング層
210 …銅合金層
220 …絶縁酸化金属層
Claims (8)
- 基板上に第1層間絶縁膜及び研磨停止層を形成する段階と、
前記研磨停止層及び第1層間絶縁膜をエッチングしてダマシンパターンを形成する段階と、
前記ダマシンパターンを含んだ前記研磨停止層上に銅拡散防止導電膜及び銅層を形成する段階と、
前記ダマシンパターン内に銅配線を形成する段階と、
前記銅配線を含んだ全体構造の表面に金属元素ドーピング層を形成する段階と、
前記金属元素ドーピング層が形成された全体構造上に銅拡散防止絶縁膜及び第2層間絶縁膜を形成し、これらの絶縁膜蒸着時の熱によって前記銅配線と前記銅拡散防止絶縁膜との界面には銅合金層及び酸化金属層が形成され、前記銅配線の周辺層と前記銅拡散防止絶縁膜との界面には酸化金属層が形成される段階とを含む半導体素子の銅配線形成方法。 - 前記金属元素ドーピング層は、インプランテーション法又はプラズマドーピング法で特定の金属元素をドーピングさせて形成するが、前記銅合金層の厚さが10〜500Åに形成されるようにその深さと濃度を調節して形成する請求項1記載の半導体素子の銅配線形成方法。
- 前記金属元素ドーピン層は特定の金属元素の濃度が0.5〜10%となるように形成する請求項1又は2記載の半導体素子の銅配線形成方法。
- 前記特定の金属元素はMg、Cd、Be、Sn、Pdのような金属元素である請求項2記載の半導体素子の銅配線形成方法。
- 前記銅配線表面に生成される銅酸化層を除去するために、前記金属元素ドーピング層を形成する前段階、形成する段階及び形成した後段階の少なくとも一つの段階でプラズマ処理を行う請求項1記載の半導体素子の銅配線形成方法。
- 前記プラズマ処理は窒素と水素を含有した混合ガス又はアンモニア系列のガスを用いて温度100〜350℃の範囲で行う請求項5記載の半導体素子の銅配線形成方法。
- 前記第2層間絶縁膜の形成後、前記銅合金層及び前記酸化金属層の形成のための熱処理工程を行う請求項1記載の半導体素子の銅配線形成方法。
- 前記熱処理工程は温度100〜500℃の範囲で行う請求項7記載の半導体素子の銅配線形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030046295A KR100546209B1 (ko) | 2003-07-09 | 2003-07-09 | 반도체 소자의 구리 배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
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JP2005033160A true JP2005033160A (ja) | 2005-02-03 |
JP4482313B2 JP4482313B2 (ja) | 2010-06-16 |
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Application Number | Title | Priority Date | Filing Date |
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JP2003389232A Expired - Lifetime JP4482313B2 (ja) | 2003-07-09 | 2003-11-19 | 半導体素子の銅配線形成方法 |
Country Status (3)
Country | Link |
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US (1) | US7087524B2 (ja) |
JP (1) | JP4482313B2 (ja) |
KR (1) | KR100546209B1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010045161A (ja) * | 2008-08-12 | 2010-02-25 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2013149990A (ja) * | 2010-02-26 | 2013-08-01 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7402519B2 (en) | 2005-06-03 | 2008-07-22 | Intel Corporation | Interconnects having sealing structures to enable selective metal capping layers |
JP2007180420A (ja) * | 2005-12-28 | 2007-07-12 | Fujitsu Ltd | 半導体装置の製造方法及び磁気ヘッドの製造方法 |
US20100059889A1 (en) * | 2006-12-20 | 2010-03-11 | Nxp, B.V. | Adhesion of diffusion barrier on copper-containing interconnect element |
US8764961B2 (en) * | 2008-01-15 | 2014-07-01 | Applied Materials, Inc. | Cu surface plasma treatment to improve gapfill window |
DE102008007001B4 (de) * | 2008-01-31 | 2016-09-22 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Vergrößern des Widerstandsverhaltens gegenüber Elektromigration in einer Verbindungsstruktur eines Halbleiterbauelements durch Bilden einer Legierung |
US8043976B2 (en) * | 2008-03-24 | 2011-10-25 | Air Products And Chemicals, Inc. | Adhesion to copper and copper electromigration resistance |
US8358007B2 (en) * | 2009-06-11 | 2013-01-22 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system employing low-k dielectrics and method of manufacture thereof |
WO2011132625A1 (en) | 2010-04-23 | 2011-10-27 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
CN102903666B (zh) * | 2011-07-25 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
US9425092B2 (en) * | 2013-03-15 | 2016-08-23 | Applied Materials, Inc. | Methods for producing interconnects in semiconductor devices |
US20140273436A1 (en) * | 2013-03-15 | 2014-09-18 | Globalfoundries Inc. | Methods of forming barrier layers for conductive copper structures |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1170784A4 (en) * | 1999-03-19 | 2004-09-29 | Tokyo Electron Ltd | SEMICONDUCTOR DEVICE AND ASSOCIATED PRODUCTION METHOD |
US6800554B2 (en) | 2000-12-18 | 2004-10-05 | Intel Corporation | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
US6815331B2 (en) * | 2001-05-17 | 2004-11-09 | Samsung Electronics Co., Ltd. | Method for forming metal wiring layer of semiconductor device |
-
2003
- 2003-07-09 KR KR1020030046295A patent/KR100546209B1/ko active IP Right Grant
- 2003-11-19 JP JP2003389232A patent/JP4482313B2/ja not_active Expired - Lifetime
- 2003-11-24 US US10/720,849 patent/US7087524B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010045161A (ja) * | 2008-08-12 | 2010-02-25 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2013149990A (ja) * | 2010-02-26 | 2013-08-01 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
US9911625B2 (en) | 2010-02-26 | 2018-03-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US10304696B2 (en) | 2010-02-26 | 2019-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US11049733B2 (en) | 2010-02-26 | 2021-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US11682562B2 (en) | 2010-02-26 | 2023-06-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US12033867B2 (en) | 2010-02-26 | 2024-07-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
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US20050009331A1 (en) | 2005-01-13 |
JP4482313B2 (ja) | 2010-06-16 |
US7087524B2 (en) | 2006-08-08 |
KR20050006472A (ko) | 2005-01-17 |
KR100546209B1 (ko) | 2006-01-24 |
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