JP2004235499A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2004235499A JP2004235499A JP2003023324A JP2003023324A JP2004235499A JP 2004235499 A JP2004235499 A JP 2004235499A JP 2003023324 A JP2003023324 A JP 2003023324A JP 2003023324 A JP2003023324 A JP 2003023324A JP 2004235499 A JP2004235499 A JP 2004235499A
- Authority
- JP
- Japan
- Prior art keywords
- potential
- power supply
- transistor
- supplied
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003023324A JP2004235499A (ja) | 2003-01-31 | 2003-01-31 | 半導体装置 |
| US10/768,394 US6985023B2 (en) | 2003-01-31 | 2004-01-30 | Selective switching of a transistor's back gate potential |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003023324A JP2004235499A (ja) | 2003-01-31 | 2003-01-31 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004235499A true JP2004235499A (ja) | 2004-08-19 |
| JP2004235499A5 JP2004235499A5 (enExample) | 2005-04-21 |
Family
ID=32952154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003023324A Pending JP2004235499A (ja) | 2003-01-31 | 2003-01-31 | 半導体装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6985023B2 (enExample) |
| JP (1) | JP2004235499A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009017640A (ja) * | 2007-07-03 | 2009-01-22 | Nec Electronics Corp | 昇圧回路、およびその昇圧回路を備える集積回路 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100321094A1 (en) * | 2010-08-29 | 2010-12-23 | Hao Luo | Method and circuit implementation for reducing the parameter fluctuations in integrated circuits |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2585450B2 (ja) | 1990-04-18 | 1997-02-26 | 東芝マイクロエレクトロニクス株式会社 | 半導体回路装置 |
| JPH07131332A (ja) | 1993-11-04 | 1995-05-19 | Pfu Ltd | Cmos回路 |
| JP3379050B2 (ja) | 1993-11-15 | 2003-02-17 | 富士通株式会社 | 半導体装置 |
| US5606287A (en) | 1994-06-17 | 1997-02-25 | Fujitsu Limited | Operational amplifier having stable operations for a wide range of source voltage, and current detector circuit employing a small number of elements |
| JP3180662B2 (ja) * | 1996-03-29 | 2001-06-25 | 日本電気株式会社 | 電源切り替え回路 |
| JP3814385B2 (ja) * | 1997-10-14 | 2006-08-30 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
| DE69823982D1 (de) * | 1998-05-29 | 2004-06-24 | St Microelectronics Srl | Monolithisch integrierter Umschalter für elektrisch programmierbare Speicherzellenvorrichtungen |
| JP2001186007A (ja) * | 1999-12-24 | 2001-07-06 | Sharp Corp | 金属酸化膜半導体トランジスタ回路およびそれを用いた半導体集積回路 |
-
2003
- 2003-01-31 JP JP2003023324A patent/JP2004235499A/ja active Pending
-
2004
- 2004-01-30 US US10/768,394 patent/US6985023B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009017640A (ja) * | 2007-07-03 | 2009-01-22 | Nec Electronics Corp | 昇圧回路、およびその昇圧回路を備える集積回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20040227566A1 (en) | 2004-11-18 |
| US6985023B2 (en) | 2006-01-10 |
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