JP2003512724A - 非浮遊ボディを備える電界効果トランジスタおよびバルクシリコンウェハ上に当該トランジスタを形成するための方法 - Google Patents

非浮遊ボディを備える電界効果トランジスタおよびバルクシリコンウェハ上に当該トランジスタを形成するための方法

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Publication number
JP2003512724A
JP2003512724A JP2001531145A JP2001531145A JP2003512724A JP 2003512724 A JP2003512724 A JP 2003512724A JP 2001531145 A JP2001531145 A JP 2001531145A JP 2001531145 A JP2001531145 A JP 2001531145A JP 2003512724 A JP2003512724 A JP 2003512724A
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JP
Japan
Prior art keywords
region
silicon substrate
central channel
substrate
source
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Withdrawn
Application number
JP2001531145A
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English (en)
Japanese (ja)
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JP2003512724A5 (enExample
Inventor
ジュ，ドン−ヒューク
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003512724A publication Critical patent/JP2003512724A/ja
Publication of JP2003512724A5 publication Critical patent/JP2003512724A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2001531145A 1999-10-20 2000-09-21 非浮遊ボディを備える電界効果トランジスタおよびバルクシリコンウェハ上に当該トランジスタを形成するための方法 Withdrawn JP2003512724A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/421,305 1999-10-20
US09/421,305 US6376286B1 (en) 1999-10-20 1999-10-20 Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
PCT/US2000/026165 WO2001029897A1 (en) 1999-10-20 2000-09-21 Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer

Publications (2)

Publication Number Publication Date
JP2003512724A true JP2003512724A (ja) 2003-04-02
JP2003512724A5 JP2003512724A5 (enExample) 2007-11-01

Family

ID=23669987

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001531145A Withdrawn JP2003512724A (ja) 1999-10-20 2000-09-21 非浮遊ボディを備える電界効果トランジスタおよびバルクシリコンウェハ上に当該トランジスタを形成するための方法

Country Status (6)

Country Link
US (1) US6376286B1 (enExample)
EP (1) EP1173892A1 (enExample)
JP (1) JP2003512724A (enExample)
KR (1) KR100670226B1 (enExample)
TW (1) TW476138B (enExample)
WO (1) WO2001029897A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252268A (ja) * 2004-03-05 2005-09-15 Samsung Electronics Co Ltd ベリード酸化膜を具備する半導体装置の製造方法及びこれを具備する半導体装置
JP2007519239A (ja) 2004-01-08 2007-07-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化ｓｏｉ構造
JP2013123077A (ja) * 2006-06-29 2013-06-20 Internatl Business Mach Corp <Ibm> フィンｆｅｔデバイスの構造およびその製造方法

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599789B1 (en) * 2000-11-15 2003-07-29 Micron Technology, Inc. Method of forming a field effect transistor
US6313008B1 (en) * 2001-01-25 2001-11-06 Chartered Semiconductor Manufacturing Inc. Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon
US7071043B2 (en) * 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
KR100525797B1 (ko) * 2003-06-18 2005-11-02 동부아남반도체 주식회사 소자분리막 구조 및 제조 방법
US6936522B2 (en) * 2003-06-26 2005-08-30 International Business Machines Corporation Selective silicon-on-insulator isolation structure and method
JP2008541421A (ja) * 2005-05-03 2008-11-20 エヌエックスピー ビー ヴィ 半導体デバイスの製造方法および該製造方法により得られた半導体デバイス
US7538389B2 (en) 2005-06-08 2009-05-26 Micron Technology, Inc. Capacitorless DRAM on bulk silicon
US20070059897A1 (en) 2005-09-09 2007-03-15 Armin Tilke Isolation for semiconductor devices
JP2007110005A (ja) * 2005-10-17 2007-04-26 Nec Electronics Corp 半導体装置の製造方法
US7625776B2 (en) * 2006-06-02 2009-12-01 Micron Technology, Inc. Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon
US7628932B2 (en) 2006-06-02 2009-12-08 Micron Technology, Inc. Wet etch suitable for creating square cuts in si
US7709341B2 (en) 2006-06-02 2010-05-04 Micron Technology, Inc. Methods of shaping vertical single crystal silicon walls and resulting structures
KR100780658B1 (ko) * 2006-12-27 2007-11-30 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP2009147000A (ja) * 2007-12-12 2009-07-02 Seiko Instruments Inc 半導体装置の製造方法
KR100971421B1 (ko) * 2008-04-21 2010-07-21 주식회사 하이닉스반도체 측벽이 리세스된 활성영역을 구비하는 반도체 장치 및 그제조 방법
US8106459B2 (en) 2008-05-06 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US8048723B2 (en) 2008-12-05 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs having dielectric punch-through stoppers
US20090325359A1 (en) * 2008-06-30 2009-12-31 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing a modified isolation structure
US8263462B2 (en) 2008-12-31 2012-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dielectric punch-through stoppers for forming FinFETs having dual fin heights
US8426268B2 (en) * 2009-02-03 2013-04-23 International Business Machines Corporation Embedded DRAM memory cell with additional patterning layer for improved strap formation
US8293616B2 (en) 2009-02-24 2012-10-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabrication of semiconductor devices with low capacitance
KR101640830B1 (ko) * 2009-08-17 2016-07-22 삼성전자주식회사 기판 구조체 및 그 제조 방법
US8648414B2 (en) * 2011-07-01 2014-02-11 Micron Technology, Inc. Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods
US9214932B2 (en) 2013-02-11 2015-12-15 Triquint Semiconductor, Inc. Body-biased switching device
US9203396B1 (en) 2013-02-22 2015-12-01 Triquint Semiconductor, Inc. Radio frequency switch device with source-follower
US9379698B2 (en) 2014-02-04 2016-06-28 Triquint Semiconductor, Inc. Field effect transistor switching circuit
US9500946B2 (en) * 2015-01-29 2016-11-22 Tel Epion Inc. Sidewall spacer patterning method using gas cluster ion beam
WO2018212777A1 (en) * 2017-05-19 2018-11-22 Intel Corporation Profile engineering of iii-n transistors to reduce contact resistance to 2deg

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577161A (en) 1980-06-16 1982-01-14 Toshiba Corp Mos semiconductor device
US4888300A (en) 1985-11-07 1989-12-19 Fairchild Camera And Instrument Corporation Submerged wall isolation of silicon islands
US4682407A (en) 1986-01-21 1987-07-28 Motorola, Inc. Means and method for stabilizing polycrystalline semiconductor layers
US4683637A (en) 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
US5097312A (en) * 1989-02-16 1992-03-17 Texas Instruments Incorporated Heterojunction bipolar transistor and integration of same with field effect device
KR920008834A (ko) 1990-10-09 1992-05-28 아이자와 스스무 박막 반도체 장치
US5391503A (en) * 1991-05-13 1995-02-21 Sony Corporation Method of forming a stacked semiconductor device wherein semiconductor layers and insulating films are sequentially stacked and forming openings through such films and etchings using one of the insulating films as a mask
JP3181695B2 (ja) 1992-07-08 2001-07-03 ローム株式会社 Ｓｏｉ基板を用いた半導体装置の製造方法
DE4340590A1 (de) * 1992-12-03 1994-06-09 Hewlett Packard Co Grabenisolation unter Verwendung dotierter Seitenwände
US5262346A (en) 1992-12-16 1993-11-16 International Business Machines Corporation Nitride polish stop for forming SOI wafers
JPH08125034A (ja) 1993-12-03 1996-05-17 Mitsubishi Electric Corp 半導体記憶装置
KR100329061B1 (ko) * 1994-03-15 2002-11-13 내셔널 세미콘덕터 코포레이션 평면화된트렌치및전계산화물분리방법
JP2560251B2 (ja) 1994-03-18 1996-12-04 工業技術院長 シリコン単結晶自己支持薄膜の製造法
US5466630A (en) 1994-03-21 1995-11-14 United Microelectronics Corp. Silicon-on-insulator technique with buried gap
US5489792A (en) 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
KR0135147B1 (ko) * 1994-07-21 1998-04-22 문정환 트랜지스터 제조방법
US5494837A (en) 1994-09-27 1996-02-27 Purdue Research Foundation Method of forming semiconductor-on-insulator electronic devices by growing monocrystalline semiconducting regions from trench sidewalls
US5705405A (en) * 1994-09-30 1998-01-06 Sgs-Thomson Microelectronics, Inc. Method of making the film transistor with all-around gate electrode
US5702989A (en) * 1996-02-08 1997-12-30 Taiwan Semiconductor Manufacturing Company Ltd. Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column
US5674760A (en) 1996-02-26 1997-10-07 United Microelectronics Corporation Method of forming isolation regions in a MOS transistor device
KR0176202B1 (ko) 1996-04-09 1999-04-15 김광호 에스.오.아이형 트랜지스터 및 그 제조방법
US5963789A (en) 1996-07-08 1999-10-05 Kabushiki Kaisha Toshiba Method for silicon island formation
US5907768A (en) * 1996-08-16 1999-05-25 Kobe Steel Usa Inc. Methods for fabricating microelectronic structures including semiconductor islands
US5804856A (en) 1996-11-27 1998-09-08 Advanced Mirco Devices, Inc. Depleted sidewall-poly LDD transistor
US5894152A (en) * 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
US5846857A (en) 1997-09-05 1998-12-08 Advanced Micro Devices, Inc. CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US5879975A (en) 1997-09-05 1999-03-09 Advanced Micro Devices, Inc. Heat treating nitrogen implanted gate electrode layer for improved gate electrode etch profile
US5976945A (en) * 1997-11-20 1999-11-02 Vanguard International Semiconductor Corporation Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
US5811855A (en) 1997-12-29 1998-09-22 United Technologies Corporation SOI combination body tie
US6004864A (en) * 1998-02-25 1999-12-21 Taiwan Semiconductor Manufacturing Company Ltd. Ion implant method for forming trench isolation for integrated circuit devices
US6008104A (en) * 1998-04-06 1999-12-28 Siemens Aktiengesellschaft Method of fabricating a trench capacitor with a deposited isolation collar
US5977579A (en) * 1998-12-03 1999-11-02 Micron Technology, Inc. Trench dram cell with vertical device and buried word lines
US6066527A (en) * 1999-07-26 2000-05-23 Infineon Technologies North America Corp. Buried strap poly etch back (BSPE) process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007519239A (ja) 2004-01-08 2007-07-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 直流ノード拡散領域の下に埋め込み酸化物を有さず、酸化物ホールを有する差別化ｓｏｉ構造
JP2005252268A (ja) * 2004-03-05 2005-09-15 Samsung Electronics Co Ltd ベリード酸化膜を具備する半導体装置の製造方法及びこれを具備する半導体装置
JP2013123077A (ja) * 2006-06-29 2013-06-20 Internatl Business Mach Corp <Ibm> フィンｆｅｔデバイスの構造およびその製造方法

Also Published As

Publication number Publication date
US20020025636A1 (en) 2002-02-28
WO2001029897A1 (en) 2001-04-26
EP1173892A1 (en) 2002-01-23
KR100670226B1 (ko) 2007-01-17
US6376286B1 (en) 2002-04-23
TW476138B (en) 2002-02-11
KR20010089659A (ko) 2001-10-08

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