Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment

Definitions

• the present invention relates generally to silicon on insulator (SOI) field effect transistor structures, and more specifically to such structures formed on a conventional silicon bulk wafer.
• SOI silicon on insulator
• MOS metal-oxide-semiconductor
• FETs field effect transistors
• MOS metal-oxide-semiconductor
• CMOS complimentary metal oxide semiconductor
• junction capacitance between the source/drain and the bulk substrate and "off state leakage from the drain to the source both increase power consumption. Junction capacitance also slows the speed at which a device using such transistors can operate.
• SOI field effect transistors suffer from floating body effects.
• the floating body effect occurs because the channel, or body, of the transistor is not connected to a fixed potential and, therefore the body takes on charge based on recent operation of the transistor.
• the floating body effect causes the current-to-voltage curve for the transistor to distort or kink, which in turn causes the threshold voltage for operating the transistor to fluctuate.
• passgate devices such as those used in dynamic random access memory (DRAM) wherein it is critical that the threshold voltage remain fixed such that the transistor remains in the "Off position to prevent charge leakage from the storage capacitor.
• a first object of this invention is to provide a method of forming a field effect transistor on a semiconductor substrate which includes etching an insulating trench around the perimeter of an active region of said transistor to isolate the active region from other structures on said substrate and etching an insulating undercut in the bottom of the insulating trench to isolate at least a portion of the bottom surface of the active region from the substrate Portions of the active region may be doped to form each of a source region and a drain region on opposing sides of a central channel region The insulating undercut may isolate at least a portion of both the source region and the drain region from the silicon substrate Furthermore, the insulating undercut may isolate at least a portion of the central channel region from the silicon substrate
• Etching the undercut includes a) forming a protective layer on the side walls and bottom of the trench, b) performing a vertical anisotropic etch of said layer to remove such layer to expose silicon substrate at the bottom of the trench, and c) performing an isotropic etch of the sihcon substrate to form said undercut
• the isotropic etch may be performed using a KOH wet etch
• a second object of this invention is to provide a field effect transistor formed on a semiconductor substrate which includes an active region, including a central channel region and a source region and a dram region disposed on opposite sides of said central channel region, a b ⁇ dge region, with a cross section area smaller than a cross section of the active region, consecutively coupling the central channel region with said semiconductor substrate, and an insulator isolating said active region and said b ⁇ dge region from other structures formed on said semiconductor substrate
• the central channel region, the bridge region, and the semiconductor substrate may all be the same conductivity and the source region and drain region may be of an opposite conductivity
• the insulator may extend under a bottom surface of the active region to at least partially isolate the source region and the dram region from the silicon substrate such that the semiconductor junctions between the source region and the silicon substrate and the drain region and the silicon substrate are at least one of reduced in size or eliminated
• the insulator may be silicon dioxide
• a third object of this invention is to provide a semiconductor device including a plurality of field effect transistors formed on a semiconductor substrate, each transistor including a) an active region, including a central channel region and a source region and a dram region each on opposing sides of the central channel region, b) a b ⁇ dge region, with a cross section area smaller than a cross section of the active body region, conductively coupling the central channel region with said semiconductor substrate, and c) an insulator isolating said active body region and said b ⁇ dge region from at least one other of said plurality of transistors
• the central channel region, the b ⁇ dge region, and the semiconductor substrate all may be the same conductivity and the source region and drain region may be of an opposite conductivity
• the insulator may extend under a bottom surface of the active region to at least partially isolate the source region and the dram region from the silicon substrate such that the semiconductor junctions between the source region and the silicon substrate and the drain region and the silicon substrate are at least one of reduced in size
• Fig. 1 is a perspective view, partially cut away, of a field effect transistor (FET) formed on silicon substrate in accordance with this invention.
• FET field effect transistor
• Fig. 2 is a cross sectional view of a first step in the fabrication of the FET of this invention.
• Fig. 3 is a cross sectional view of a second step in the fabrication of the FET of this invention.
• Fig. 4 is a cross sectional view of a third step in the fabrication of the FET of this invention.
• Fig. 5 is a cross sectional view of a fourth step in the fabrication of the FET of this invention.
• Fig. 6 is a cross sectional view of a fifth step in the fabrication of the FET of this invention.
• Fig. 7 is a cross sectional view of a sixth step in the fabrication of the FET of this invention.
• Fig. 8 is a cross sectional view of a seventh step in the fabrication of the FET of this invention.
• Fig. 9 is a cross sectional view of a eighth step in the fabrication of the FET of this invention.
• Fig. 10 is a cross sectional view of the FET of this invention. Modes for Carrying Out the Invention
• an active region 48 of a field effect transistor 10 of this invention includes a channel region 26, a source region 28, and a drain region 30.
• the channel region 26 is preferably P-conductivity silicon while the source region 28 and the drain region 30 are each N-conductivity silicon to form two semiconductor junctions 40 and 42.
• the channel region 26 may be N-conductivity silicon while each of the source region 28 and the drain region 30 are P- conductivity silicon.
• the active region is isolated by an insulating trench 32 which has side walls 16 forming the perimeter 22 of the active region 48 of the FET 10. The insulating trench 32 insulates the active region 48 from other structures formed in the silicon substrate 12.
• the insulating trench 32 includes under cut regions 20 which form the bottom surface 24 of the active region 48 and form the sidewalls 14 of a bridge region 36 which electrically couples the channel region 26 of the active region 48 to the bulk silicon substrate 12.
• the active region 38 and the bridge region 36 together form the body 34 of the FET 10 of this invention.
• the bridge region 36 electrically couples the channel region 26 to the bulk silicon substrate 12, the channel region 26 potential will always remain at the potential of the silicon substrate 12 and can not accumulate a charge, or float, based on historical operation of the FET 10. It should also be appreciated that because the insulating trench 32 includes undercut regions 20, the cross sectional area of the bridge region 36 is significantly smaller than the cross sectional area of the active region 48 and therefore there is no semiconductor junction, or minimal sized semiconductor junction, between either the source region 28 or the drain region 30 and the silicon substrate 12 thereby reducing junction capacitance.
• a silicon nitride layer 18 approximately 1,500 - 2,000 Angstroms thick is formed on top of a thin layer of oxide (not shown) approximately 150 - 200 on the top surface of the bulk silicon substrate 12 as shown in Figure 2.
• the silicon nitride 18 is patterned and etched to form a silicon nitride mask over the active region 48 while exposing the silicon substrate in the areas where insulating trench 32 is to be formed as shown in Figure 3.
• Patterning and etching the silicon nitride 18 to form the silicon nitride mask is performed using conventional photolithography techniques wherein 1 ) a layer of a UV sensitive photoresist layer is applied to the surface of the silicon nitride 18; 2) a UV illumination source and reticle provide collimated light to expose and pattern the photoresist; 3) A developer solution hardens the unexposed areas of the photoresist while the UV light dissolves and the developer washes away the exposed portions thereby leaving the exposed portions as a mask on the surface of the silicon nitride 18; And 4) a dry etch with an etching compound that etches silicon nitride while not etching the photoresist removes the silicon nitride layer 18 in the
• the unmasked portions of the silicon substrate 12 are etched away to a depth of approximately 2,000 - 4,000 Angstroms to form an open trench 38 as shown in Figure 4.
• the open trench 38 will later be filled with silicon dioxide to become the insulating trench 32 described in the discussion of Figure 1.
• the etching process for the silicon substrate is typically an anisotropic dry etch using hydrogen bromide (HBr) which has selectivity characteristics such that it etches the silicon substrate 12 but not the silicon nitride 18.
• HBr hydrogen bromide
• a fourth step in the fabrication of the FET 10 of this invention includes depositing a layer of silicon dioxide 44, approximately 500 - 1,000 Angstroms in depth, across all exposed surfaces of the wafer including the across the top of the silicon nitride layer 18 and on the sidewalls and bottom of open trench 38 as shown in Figure 5.
• Depositing the layer of silicon dioxide 44 is typically performed using a conventional chemical vapor deposition (CVD) process with a gas such as SiH4.
• CVD chemical vapor deposition
• a vertical anisotropic etch of the silicon dioxide layer 44 removes such silicon dioxide from all horizontal surfaces, including the top surface of the silicon nitride 18 and the bottom of open trench 38.
• An example of a vertical anisotropic etch includes a plasma etch using CHF3. It should be appreciated that such an etching technique removes an even thickness of the silicon dioxide layer in a vertical dimension such that the net result of the vertical etch is that a layer of silicon dioxide remains on the side walls 16 of the open trench 38 while the bottom of trench 38 is exposed silicon substrate 12.
• an isotropic etch of the bulk silicon at the bottom of the open trench 38 is performed to remove approximately 1 ,000 - 2,000 Angstroms of material in both the horizontal and vertical dimensions to form an open undercut 46 which in a subsequent step will be filled with silicon dioxide to form the undercut region 20 of the insulating trench 32 as shown in Figure 7.
• This isototropic etching step is preferably a known KOH wet etch. It should be appreciated that such an etching compound must be chosen with selectivity characteristics such that it will rapidly etch the exposed silicon substrate 12 but will not materially etch the silicon dioxide coating 44 on the sidewalls of the open trench 38.
• undercut regions 20 define the bottom surface 24 of the active region 48 and the side walls 14 of the bridge region 36.
• the open trench 38 is filled with silicon dioxide to form insulating trench 32.
• Filling the open trench 38 preferably uses a known CVD process using a gas such as SiH4 or TEOS.
• the surface of the wafer is polished using a chemical mechanical polish (CMP) to remove any excess silicon dioxide layer and the remaining silicon nitride mask as shown in Figure 8.
• CMP chemical mechanical polish
• a layer of silicon dioxide 50, serving as the gate oxide layer, and a polysilicon gate 52 are formed on the top surface of the substrate.
• the silicon dioxide 50 is typically grown on the surface of the active region 48 using a thermal oxidation process and the polysilicon layer is deposited on top of the silicon dioxide layer 50 using a low pressure chemical vapor deposition (LPCVD) process.
• LPCVD low pressure chemical vapor deposition
• the polysilicon layer is then patterned and etched using the photolithography method discussed earlier to define and mask the channel region of the FET 10 in a known self alligning gate, source and drain process as shown in Figure 9.
• the portions of the silicon substrate on opposing sides of the P-type silicon in the channel region of the FET 10 that are not masked by the gate applied in the 7 th step are doped into N-type silicon.
• Doping is typically performed using Ion implantation techniques. Ions of dopant such as arsenic 54 are accelerated to a high velocity in an electric field and impinge on the target wafer. Because the ions cannot penetrate the poly-silicon gate, the poly-silicon gate effectively operates as a mask which results in doping only the exposed source region 28, the drain region 30, and the polysilicon gate 52 as shown in Figure 10.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Thin Film Transistor (AREA)

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• 1999
  • 1999-10-20 US US09/421,305 patent/US6376286B1/en not_active Expired - Lifetime
• 2000
  • 2000-09-21 JP JP2001531145A patent/JP2003512724A/ja not_active Withdrawn
  • 2000-09-21 WO PCT/US2000/026165 patent/WO2001029897A1/en not_active Ceased
  • 2000-09-21 KR KR1020017007803A patent/KR100670226B1/ko not_active Expired - Fee Related
  • 2000-09-21 EP EP00963752A patent/EP1173892A1/en not_active Withdrawn
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