JP2003124251A - 半導体装置と実装構造及びその製造方法 - Google Patents

半導体装置と実装構造及びその製造方法

Info

Publication number
JP2003124251A
JP2003124251A JP2001312459A JP2001312459A JP2003124251A JP 2003124251 A JP2003124251 A JP 2003124251A JP 2001312459 A JP2001312459 A JP 2001312459A JP 2001312459 A JP2001312459 A JP 2001312459A JP 2003124251 A JP2003124251 A JP 2003124251A
Authority
JP
Japan
Prior art keywords
semiconductor device
mounting
target member
electrode
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001312459A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003124251A5 (enExample
Inventor
Masahiro Ono
正浩 小野
Yutaka Kumano
豊 熊野
Minehiro Itagaki
峰広 板垣
Tosaku Nishiyama
東作 西山
Yoshihiro Tomura
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001312459A priority Critical patent/JP2003124251A/ja
Publication of JP2003124251A publication Critical patent/JP2003124251A/ja
Publication of JP2003124251A5 publication Critical patent/JP2003124251A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01321—Manufacture or treatment of die-attach connectors using local deposition
    • H10W72/01325—Manufacture or treatment of die-attach connectors using local deposition in solid form
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/859—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
JP2001312459A 2001-10-10 2001-10-10 半導体装置と実装構造及びその製造方法 Pending JP2003124251A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001312459A JP2003124251A (ja) 2001-10-10 2001-10-10 半導体装置と実装構造及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001312459A JP2003124251A (ja) 2001-10-10 2001-10-10 半導体装置と実装構造及びその製造方法

Publications (2)

Publication Number Publication Date
JP2003124251A true JP2003124251A (ja) 2003-04-25
JP2003124251A5 JP2003124251A5 (enExample) 2005-04-07

Family

ID=19131112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001312459A Pending JP2003124251A (ja) 2001-10-10 2001-10-10 半導体装置と実装構造及びその製造方法

Country Status (1)

Country Link
JP (1) JP2003124251A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363220A (ja) * 2003-06-03 2004-12-24 Matsushita Electric Ind Co Ltd 実装構造体の製造方法及び接続体
WO2005119776A1 (ja) * 2004-06-04 2005-12-15 Zycube Co., Ltd. 三次元積層構造を持つ半導体装置及びその製造方法
US7649267B2 (en) 2005-03-17 2010-01-19 Panasonic Corporation Package equipped with semiconductor chip and method for producing same
US7906363B2 (en) 2004-08-20 2011-03-15 Zycube Co., Ltd. Method of fabricating semiconductor device having three-dimensional stacked structure
WO2015002921A1 (en) * 2013-07-03 2015-01-08 Harris Corporation Method for manufacturing an electronic device by connecting an integrated circuit to a substrate using a liquid crystal polymer layer with openings and a corresponding device
WO2020182361A1 (en) * 2019-03-13 2020-09-17 Danfoss Silicon Power Gmbh Method for making a cohesive connection by fluxless chip- or element soldering, gluing or sintering using a material preform

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004363220A (ja) * 2003-06-03 2004-12-24 Matsushita Electric Ind Co Ltd 実装構造体の製造方法及び接続体
WO2005119776A1 (ja) * 2004-06-04 2005-12-15 Zycube Co., Ltd. 三次元積層構造を持つ半導体装置及びその製造方法
JPWO2005119776A1 (ja) * 2004-06-04 2008-04-03 株式会社ザイキューブ 三次元積層構造を持つ半導体装置及びその製造方法
JP5052130B2 (ja) * 2004-06-04 2012-10-17 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置及びその製造方法
TWI426542B (zh) * 2004-06-04 2014-02-11 Ｋａｍｉｙａｃｈｏ知識產權控股公司 三維積層構造之半導體裝置及其製造方法
US7906363B2 (en) 2004-08-20 2011-03-15 Zycube Co., Ltd. Method of fabricating semiconductor device having three-dimensional stacked structure
US7649267B2 (en) 2005-03-17 2010-01-19 Panasonic Corporation Package equipped with semiconductor chip and method for producing same
WO2015002921A1 (en) * 2013-07-03 2015-01-08 Harris Corporation Method for manufacturing an electronic device by connecting an integrated circuit to a substrate using a liquid crystal polymer layer with openings and a corresponding device
US9293438B2 (en) 2013-07-03 2016-03-22 Harris Corporation Method for making electronic device with cover layer with openings and related devices
US9681543B2 (en) 2013-07-03 2017-06-13 Harris Corporation Method for making electronic device with cover layer with openings and related devices
WO2020182361A1 (en) * 2019-03-13 2020-09-17 Danfoss Silicon Power Gmbh Method for making a cohesive connection by fluxless chip- or element soldering, gluing or sintering using a material preform

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