JP2002506288A5 - - Google Patents

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Publication number
JP2002506288A5
JP2002506288A5 JP2000535047A JP2000535047A JP2002506288A5 JP 2002506288 A5 JP2002506288 A5 JP 2002506288A5 JP 2000535047 A JP2000535047 A JP 2000535047A JP 2000535047 A JP2000535047 A JP 2000535047A JP 2002506288 A5 JP2002506288 A5 JP 2002506288A5
Authority
JP
Japan
Prior art keywords
region
layer
separation
hard mask
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000535047A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002506288A (ja
Filing date
Publication date
Priority claimed from US09/036,288 external-priority patent/US5966618A/en
Application filed filed Critical
Publication of JP2002506288A publication Critical patent/JP2002506288A/ja
Publication of JP2002506288A5 publication Critical patent/JP2002506288A5/ja
Pending legal-status Critical Current

Links

JP2000535047A 1998-03-06 1999-03-05 デュアルフィールド分離構造を形成する方法 Pending JP2002506288A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/036,288 1998-03-06
US09/036,288 US5966618A (en) 1998-03-06 1998-03-06 Method of forming dual field isolation structures
PCT/US1999/004905 WO1999045589A1 (en) 1998-03-06 1999-03-05 Method of forming dual field isolation structures

Publications (2)

Publication Number Publication Date
JP2002506288A JP2002506288A (ja) 2002-02-26
JP2002506288A5 true JP2002506288A5 (enExample) 2006-04-06

Family

ID=21887749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000535047A Pending JP2002506288A (ja) 1998-03-06 1999-03-05 デュアルフィールド分離構造を形成する方法

Country Status (6)

Country Link
US (1) US5966618A (enExample)
EP (1) EP1060510B1 (enExample)
JP (1) JP2002506288A (enExample)
KR (1) KR100537812B1 (enExample)
DE (1) DE69939775D1 (enExample)
WO (1) WO1999045589A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249036B1 (en) * 1998-03-18 2001-06-19 Advanced Micro Devices, Inc. Stepper alignment mark formation with dual field oxide process
US6127247A (en) * 1998-06-03 2000-10-03 Texas Instruments - Acer Incorporated Method of eliminating photoresist outgassing in constructing CMOS vertically modulated wells by high energy ion implantation
US6362049B1 (en) * 1998-12-04 2002-03-26 Advanced Micro Devices, Inc. High yield performance semiconductor process flow for NAND flash memory products
US6383861B1 (en) * 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
FR2810447B1 (fr) * 2000-06-16 2003-09-05 Commissariat Energie Atomique Procede de creation d'un etage de circuit integre ou conexistent des motifs fins et larges
US6750157B1 (en) 2000-10-12 2004-06-15 Advanced Micro Devices, Inc. Nonvolatile memory cell with a nitridated oxide layer
US6908817B2 (en) * 2002-10-09 2005-06-21 Sandisk Corporation Flash memory array with increased coupling between floating and control gates
US7183153B2 (en) * 2004-03-12 2007-02-27 Sandisk Corporation Method of manufacturing self aligned non-volatile memory cells
US7202125B2 (en) * 2004-12-22 2007-04-10 Sandisk Corporation Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
US7482223B2 (en) * 2004-12-22 2009-01-27 Sandisk Corporation Multi-thickness dielectric for semiconductor memory
ATE556020T1 (de) * 2004-12-29 2012-05-15 Otis Elevator Co Ausgleich in einem aufzugsystem mit mehreren kabinen in einem einzigen schacht
US7541240B2 (en) * 2005-10-18 2009-06-02 Sandisk Corporation Integration process flow for flash devices with low gap fill aspect ratio
EP3664151A1 (en) * 2018-12-06 2020-06-10 Nexperia B.V. Bipolar transistor with polysilicon emitter and method of manufacturing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3318213A1 (de) * 1983-05-19 1984-11-22 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum herstellen eines integrierten isolierschicht-feldeffekttransistors mit zur gateelektrode selbstausgerichteten kontakten
JPS62183164A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 半導体記憶装置およびその製造方法
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JPS6442164A (en) * 1987-08-07 1989-02-14 Fujitsu Ltd Semiconductor device and manufacture thereof
JP2512216B2 (ja) * 1989-08-01 1996-07-03 松下電器産業株式会社 半導体装置の製造方法
JPH04111465A (ja) * 1990-08-31 1992-04-13 Fujitsu Ltd 不揮発性半導体記憶装置の製造方法
FR2667440A1 (fr) * 1990-09-28 1992-04-03 Philips Nv Procede pour realiser des motifs d'alignement de masques.
US5110756A (en) * 1991-07-03 1992-05-05 At&T Bell Laboratories Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density
JPH08125006A (ja) * 1994-10-20 1996-05-17 Victor Co Of Japan Ltd 半導体装置及びその製造方法
JPH0997788A (ja) * 1995-07-21 1997-04-08 Rohm Co Ltd 半導体装置及びその製造方法
KR100214469B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 격리막 형성방법
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US5794809A (en) * 1997-02-18 1998-08-18 Shuval; Shlomo Trash container with automatic liner bag feed

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