KR100537812B1 - 이중 필드 분리 구조의 형성 방법 - Google Patents

이중 필드 분리 구조의 형성 방법 Download PDF

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Publication number
KR100537812B1
KR100537812B1 KR10-2000-7009845A KR20007009845A KR100537812B1 KR 100537812 B1 KR100537812 B1 KR 100537812B1 KR 20007009845 A KR20007009845 A KR 20007009845A KR 100537812 B1 KR100537812 B1 KR 100537812B1
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KR
South Korea
Prior art keywords
layer
hard mask
mask layer
locos
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-2000-7009845A
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English (en)
Korean (ko)
Other versions
KR20010041645A (ko
Inventor
유선
팜투안디.
람스베이마크에스.
창치
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20010041645A publication Critical patent/KR20010041645A/ko
Application granted granted Critical
Publication of KR100537812B1 publication Critical patent/KR100537812B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR10-2000-7009845A 1998-03-06 1999-03-05 이중 필드 분리 구조의 형성 방법 Expired - Fee Related KR100537812B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US9/036,288 1998-03-06
US09/036,288 1998-03-06
US09/036,288 US5966618A (en) 1998-03-06 1998-03-06 Method of forming dual field isolation structures

Publications (2)

Publication Number Publication Date
KR20010041645A KR20010041645A (ko) 2001-05-25
KR100537812B1 true KR100537812B1 (ko) 2005-12-20

Family

ID=21887749

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2000-7009845A Expired - Fee Related KR100537812B1 (ko) 1998-03-06 1999-03-05 이중 필드 분리 구조의 형성 방법

Country Status (6)

Country Link
US (1) US5966618A (enExample)
EP (1) EP1060510B1 (enExample)
JP (1) JP2002506288A (enExample)
KR (1) KR100537812B1 (enExample)
DE (1) DE69939775D1 (enExample)
WO (1) WO1999045589A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6249036B1 (en) * 1998-03-18 2001-06-19 Advanced Micro Devices, Inc. Stepper alignment mark formation with dual field oxide process
US6127247A (en) * 1998-06-03 2000-10-03 Texas Instruments - Acer Incorporated Method of eliminating photoresist outgassing in constructing CMOS vertically modulated wells by high energy ion implantation
US6362049B1 (en) * 1998-12-04 2002-03-26 Advanced Micro Devices, Inc. High yield performance semiconductor process flow for NAND flash memory products
US6383861B1 (en) * 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
FR2810447B1 (fr) * 2000-06-16 2003-09-05 Commissariat Energie Atomique Procede de creation d'un etage de circuit integre ou conexistent des motifs fins et larges
US6750157B1 (en) 2000-10-12 2004-06-15 Advanced Micro Devices, Inc. Nonvolatile memory cell with a nitridated oxide layer
US6908817B2 (en) * 2002-10-09 2005-06-21 Sandisk Corporation Flash memory array with increased coupling between floating and control gates
US7183153B2 (en) * 2004-03-12 2007-02-27 Sandisk Corporation Method of manufacturing self aligned non-volatile memory cells
US7202125B2 (en) * 2004-12-22 2007-04-10 Sandisk Corporation Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
US7482223B2 (en) * 2004-12-22 2009-01-27 Sandisk Corporation Multi-thickness dielectric for semiconductor memory
ATE556020T1 (de) * 2004-12-29 2012-05-15 Otis Elevator Co Ausgleich in einem aufzugsystem mit mehreren kabinen in einem einzigen schacht
US7541240B2 (en) * 2005-10-18 2009-06-02 Sandisk Corporation Integration process flow for flash devices with low gap fill aspect ratio
EP3664151A1 (en) * 2018-12-06 2020-06-10 Nexperia B.V. Bipolar transistor with polysilicon emitter and method of manufacturing

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3318213A1 (de) * 1983-05-19 1984-11-22 Deutsche Itt Industries Gmbh, 7800 Freiburg Verfahren zum herstellen eines integrierten isolierschicht-feldeffekttransistors mit zur gateelektrode selbstausgerichteten kontakten
JPS62183164A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 半導体記憶装置およびその製造方法
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JPS6442164A (en) * 1987-08-07 1989-02-14 Fujitsu Ltd Semiconductor device and manufacture thereof
JP2512216B2 (ja) * 1989-08-01 1996-07-03 松下電器産業株式会社 半導体装置の製造方法
JPH04111465A (ja) * 1990-08-31 1992-04-13 Fujitsu Ltd 不揮発性半導体記憶装置の製造方法
FR2667440A1 (fr) * 1990-09-28 1992-04-03 Philips Nv Procede pour realiser des motifs d'alignement de masques.
US5110756A (en) * 1991-07-03 1992-05-05 At&T Bell Laboratories Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density
JPH08125006A (ja) * 1994-10-20 1996-05-17 Victor Co Of Japan Ltd 半導体装置及びその製造方法
JPH0997788A (ja) * 1995-07-21 1997-04-08 Rohm Co Ltd 半導体装置及びその製造方法
KR100214469B1 (ko) * 1995-12-29 1999-08-02 구본준 반도체소자의 격리막 형성방법
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US5794809A (en) * 1997-02-18 1998-08-18 Shuval; Shlomo Trash container with automatic liner bag feed

Also Published As

Publication number Publication date
WO1999045589A1 (en) 1999-09-10
EP1060510A1 (en) 2000-12-20
JP2002506288A (ja) 2002-02-26
EP1060510B1 (en) 2008-10-22
KR20010041645A (ko) 2001-05-25
DE69939775D1 (de) 2008-12-04
US5966618A (en) 1999-10-12

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