JP2002333464A - 試験装置 - Google Patents

試験装置

Info

Publication number
JP2002333464A
JP2002333464A JP2002092565A JP2002092565A JP2002333464A JP 2002333464 A JP2002333464 A JP 2002333464A JP 2002092565 A JP2002092565 A JP 2002092565A JP 2002092565 A JP2002092565 A JP 2002092565A JP 2002333464 A JP2002333464 A JP 2002333464A
Authority
JP
Japan
Prior art keywords
dut
unit
signal
response signal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002092565A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002333464A5 (enExample
Inventor
Klaus-Peter Behrens
クラウス・ピーター・ベーレンス
Markus Rottacker
マルクス・ロッタッカー
Joerg-Walter Mohr
ヨエルク・ヴァルター・モール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2002333464A publication Critical patent/JP2002333464A/ja
Publication of JP2002333464A5 publication Critical patent/JP2002333464A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31935—Storing data, e.g. failure memory
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/005—Correction by an elastic buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2002092565A 2001-03-31 2002-03-28 試験装置 Pending JP2002333464A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01108250.0 2001-03-30
EP01108250A EP1164700B1 (en) 2001-03-31 2001-03-31 Data flow synchronization

Publications (2)

Publication Number Publication Date
JP2002333464A true JP2002333464A (ja) 2002-11-22
JP2002333464A5 JP2002333464A5 (enExample) 2005-09-08

Family

ID=8177015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002092565A Pending JP2002333464A (ja) 2001-03-31 2002-03-28 試験装置

Country Status (4)

Country Link
US (1) US20020141525A1 (enExample)
EP (1) EP1164700B1 (enExample)
JP (1) JP2002333464A (enExample)
DE (1) DE60100060T2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7689739B2 (en) * 2005-07-11 2010-03-30 Via Technologies, Inc. Spread spectrum receiver, apparatus and method of a circular buffer for multirate data
US8775701B1 (en) * 2007-02-28 2014-07-08 Altera Corporation Method and apparatus for source-synchronous capture using a first-in-first-out unit
US9449032B2 (en) * 2013-04-22 2016-09-20 Sap Se Multi-buffering system supporting read/write access to different data source type
EP3287799B1 (en) * 2015-04-16 2022-11-02 Renesas Electronics Corporation Semiconductor device and scan test method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS647400A (en) * 1987-06-29 1989-01-11 Hitachi Ltd Ic tester
US5323426A (en) * 1992-02-21 1994-06-21 Apple Computer, Inc. Elasticity buffer for data/clock synchronization
US5867672A (en) * 1996-05-21 1999-02-02 Integrated Device Technology, Inc. Triple-bus FIFO buffers that can be chained together to increase buffer depth
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6073264A (en) * 1998-04-02 2000-06-06 Intel Corporation Debug vector launch tool
US6324664B1 (en) * 1999-01-27 2001-11-27 Raytheon Company Means for testing dynamic integrated circuits

Also Published As

Publication number Publication date
DE60100060T2 (de) 2003-05-08
DE60100060D1 (de) 2003-01-16
EP1164700B1 (en) 2002-12-04
US20020141525A1 (en) 2002-10-03
EP1164700A1 (en) 2001-12-19

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