JP2002203852A - 絶縁膜の形成方法及び絶縁膜 - Google Patents

絶縁膜の形成方法及び絶縁膜

Info

Publication number
JP2002203852A
JP2002203852A JP2001000627A JP2001000627A JP2002203852A JP 2002203852 A JP2002203852 A JP 2002203852A JP 2001000627 A JP2001000627 A JP 2001000627A JP 2001000627 A JP2001000627 A JP 2001000627A JP 2002203852 A JP2002203852 A JP 2002203852A
Authority
JP
Japan
Prior art keywords
insulating film
interlayer insulating
bond
forming
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001000627A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002203852A5 (enrdf_load_stackoverflow
Inventor
Masazumi Matsuura
正純 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001000627A priority Critical patent/JP2002203852A/ja
Priority to US09/963,648 priority patent/US20020090833A1/en
Priority to US10/196,181 priority patent/US6903027B2/en
Publication of JP2002203852A publication Critical patent/JP2002203852A/ja
Publication of JP2002203852A5 publication Critical patent/JP2002203852A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP2001000627A 2001-01-05 2001-01-05 絶縁膜の形成方法及び絶縁膜 Pending JP2002203852A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001000627A JP2002203852A (ja) 2001-01-05 2001-01-05 絶縁膜の形成方法及び絶縁膜
US09/963,648 US20020090833A1 (en) 2001-01-05 2001-09-27 Method of forming dielectric film and dielectric film
US10/196,181 US6903027B2 (en) 2001-01-05 2002-07-17 Method of forming dielectric film and dielectric film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001000627A JP2002203852A (ja) 2001-01-05 2001-01-05 絶縁膜の形成方法及び絶縁膜

Publications (2)

Publication Number Publication Date
JP2002203852A true JP2002203852A (ja) 2002-07-19
JP2002203852A5 JP2002203852A5 (enrdf_load_stackoverflow) 2008-02-14

Family

ID=18869380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001000627A Pending JP2002203852A (ja) 2001-01-05 2001-01-05 絶縁膜の形成方法及び絶縁膜

Country Status (2)

Country Link
US (2) US20020090833A1 (enrdf_load_stackoverflow)
JP (1) JP2002203852A (enrdf_load_stackoverflow)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324837A (ja) * 2001-04-25 2002-11-08 Hitachi Ltd 半導体装置の製造方法
KR100439844B1 (ko) * 2002-07-24 2004-07-12 삼성전자주식회사 반도체 소자의 금속배선 형성 후의 감광막 제거방법
US7172965B2 (en) 2003-05-21 2007-02-06 Rohm Co., Ltd. Method for manufacturing semiconductor device
JP2008545253A (ja) * 2005-05-10 2008-12-11 ラム リサーチ コーポレーション 通常の低ｋ誘電性材料および／または多孔質の低ｋ誘電性材料の存在下でのレジスト剥離のための方法
US7563705B2 (en) 2002-02-14 2009-07-21 Nec Electronics Corporation Manufacturing method of semiconductor device
KR100976882B1 (ko) 2007-08-17 2010-08-18 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법 및 기억 매체

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6759098B2 (en) * 2000-03-20 2004-07-06 Axcelis Technologies, Inc. Plasma curing of MSQ-based porous low-k film materials
US6908846B2 (en) * 2002-10-24 2005-06-21 Lam Research Corporation Method and apparatus for detecting endpoint during plasma etching of thin films
US7416990B2 (en) * 2005-12-20 2008-08-26 Dongbu Electronics Co., Ltd. Method for patterning low dielectric layer of semiconductor device
US7553736B2 (en) * 2006-07-13 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Increasing dielectric constant in local regions for the formation of capacitors
US20090078675A1 (en) * 2007-09-26 2009-03-26 Silverbrook Research Pty Ltd Method of removing photoresist
WO2009039551A1 (en) * 2007-09-26 2009-04-02 Silverbrook Research Pty Ltd Method of removing photoresist
CN102509699B (zh) * 2011-11-02 2016-05-11 上海华虹宏力半导体制造有限公司 金属层光刻胶重涂方法以及光刻方法
US8871639B2 (en) * 2013-01-04 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9685393B2 (en) * 2013-03-04 2017-06-20 The Hong Kong University Of Science And Technology Phase-change chamber with patterned regions of high and low affinity to a phase-change medium for electronic device cooling
US10381322B1 (en) 2018-04-23 2019-08-13 Sandisk Technologies Llc Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same
US10879260B2 (en) 2019-02-28 2020-12-29 Sandisk Technologies Llc Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177588A (en) 1991-06-14 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including nitride layer
JP3204041B2 (ja) 1995-05-19 2001-09-04 ソニー株式会社 絶縁膜の形成方法
JPH0992717A (ja) 1995-09-21 1997-04-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH11150101A (ja) * 1997-11-18 1999-06-02 Nec Corp 半導体装置の製造方法
JP3193335B2 (ja) * 1997-12-12 2001-07-30 松下電器産業株式会社 半導体装置の製造方法
JP3248492B2 (ja) 1998-08-14 2002-01-21 日本電気株式会社 半導体装置及びその製造方法
JP2000077410A (ja) 1998-08-27 2000-03-14 Tokyo Ohka Kogyo Co Ltd 多層配線構造の形成方法
US6207583B1 (en) * 1998-09-04 2001-03-27 Alliedsignal Inc. Photoresist ashing process for organic and inorganic polymer dielectric materials
US6117782A (en) * 1999-04-22 2000-09-12 Advanced Micro Devices, Inc. Optimized trench/via profile for damascene filling
US6457477B1 (en) * 2000-07-24 2002-10-01 Taiwan Semiconductor Manufacturing Company Method of cleaning a copper/porous low-k dual damascene etch

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324837A (ja) * 2001-04-25 2002-11-08 Hitachi Ltd 半導体装置の製造方法
US7563705B2 (en) 2002-02-14 2009-07-21 Nec Electronics Corporation Manufacturing method of semiconductor device
KR100439844B1 (ko) * 2002-07-24 2004-07-12 삼성전자주식회사 반도체 소자의 금속배선 형성 후의 감광막 제거방법
US7172965B2 (en) 2003-05-21 2007-02-06 Rohm Co., Ltd. Method for manufacturing semiconductor device
JP2008545253A (ja) * 2005-05-10 2008-12-11 ラム リサーチ コーポレーション 通常の低ｋ誘電性材料および／または多孔質の低ｋ誘電性材料の存在下でのレジスト剥離のための方法
KR100976882B1 (ko) 2007-08-17 2010-08-18 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법 및 기억 매체

Also Published As

Publication number Publication date
US20020182891A1 (en) 2002-12-05
US6903027B2 (en) 2005-06-07
US20020090833A1 (en) 2002-07-11

Similar Documents

Publication Publication Date Title
US6080526A (en) Integration of low-k polymers into interlevel dielectrics using controlled electron-beam radiation
JP2002203852A (ja) 絶縁膜の形成方法及び絶縁膜
JP5482881B2 (ja) 半導体装置、および半導体装置の製造方法
JP4090740B2 (ja) 集積回路の作製方法および集積回路
JP4812838B2 (ja) 多孔質絶縁膜の形成方法
KR100985613B1 (ko) 금속간 유전체로서 사용된 낮은 ｋ 및 극도로 낮은 ｋ의 오가노실리케이트 필름의 소수성을 복원하는 방법 및 이로부터 제조된 물품
JP2004241776A (ja) 低ｋ誘電体フイルムの化学的処理
JP4667165B2 (ja) 半導体装置の製造方法
JP2001077196A (ja) 半導体装置の製造方法
JP2002110644A (ja) エッチング方法
CN1832128A (zh) 制造互连结构的方法及由其制造的互连结构
CN101005023A (zh) 低介电常数介电层的形成方法
JP2003152076A (ja) 半導体装置およびその製造方法
US7830012B2 (en) Material for forming exposure light-blocking film, multilayer interconnection structure and manufacturing method thereof, and semiconductor device
US20030134495A1 (en) Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof
US9236294B2 (en) Method for forming semiconductor device structure
US20100301495A1 (en) Semiconductor device and method for manufacturing same
JP2011082308A (ja) 半導体装置の製造方法
JP5679662B2 (ja) 誘電体キャップ層
US6417118B1 (en) Method for improving the moisture absorption of porous low dielectric film
US7691736B2 (en) Minimizing low-k dielectric damage during plasma processing
JP2004296476A (ja) 半導体装置の製造方法
US20130056874A1 (en) Protection of intermetal dielectric layers in multilevel wiring structures
JP2004260076A (ja) 被膜形成用塗布液、絶縁膜及びその製造方法ならびに半導体装置
KR100935620B1 (ko) 금속간 유전체로서 사용된 낮은 ｋ 및 극도로 낮은 ｋ의오가노실리케이트 필름의 소수성을 복원하는 방법 및이로부터 제조된 물품

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071213

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071213

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20071213

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090115

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090127

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090526