US20020090833A1 - Method of forming dielectric film and dielectric film - Google Patents

Method of forming dielectric film and dielectric film Download PDF

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Publication number
US20020090833A1
US20020090833A1 US09/963,648 US96364801A US2002090833A1 US 20020090833 A1 US20020090833 A1 US 20020090833A1 US 96364801 A US96364801 A US 96364801A US 2002090833 A1 US2002090833 A1 US 2002090833A1
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insulating film
bond
interlayer insulating
film
forming
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US09/963,648
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Masazumi Matsuura
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATSUURA, MASAZUMI
Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA reassignment MITSUBISHI DENKI KABUSHIKI KAISHA CORRECTED RECORDATION FORM COVER SHEET TO CORRECT ASSIGNOR'S DOC. DATE, PREVIOUSLY RECORDED AT REEL/FRAME 012299/0005 (ASSIGNMENT OF ASSIGNOR'S INTEREST) Assignors: MATSUURA, MASAZUMI
Publication of US20020090833A1 publication Critical patent/US20020090833A1/en
Priority to US10/196,181 priority Critical patent/US6903027B2/en
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Definitions

  • the present invention relates to a method of forming a dielectric film and a structure thereof, and more particularly to a method of forming an interlayer dielectric film in a buried wiring structure and a structure thereof.
  • the signal delay of a device is a sum of signal delay in transistors and that in interconnection. As reduction in wiring pitch rapidly proceeds, the effect of the signal delay in interconnection becomes larger than that in transistors. Since the signal delay in interconnection is in proportion to the RC product (wiring resistance ⁇ wiring capacitance), in order to reduce the signal delay in interconnection, it is necessary to reduce the wiring resistance or the wiring capacitance.
  • an insulating film having lower relative dielectric constant than that of a silicon oxide film which is a general insulating film is used as an interlayer insulating film and a copper wiring having lower wiring resistance than that of an aluminum wiring which is a general metal wiring is used as a buried wiring, to reduce the signal delay in interconnection.
  • FIGS. 13 to 17 are cross sections showing a method of forming a buried copper wiring in the background art step by step.
  • an underlying insulating film 102 made of silicon oxide film is formed on a silicon substrate 101 .
  • semiconductor elements such as transistors are formed in the silicon substrate 101 and the underlying insulating film 102 .
  • source/drain regions are selectively formed in an upper surface of the silicon substrate 101 and a gate electrode is selectively formed on the upper surface of the silicon substrate 101 .
  • source/drain wirings connected to the source/drain regions are selectively formed in the underlying insulating film 102 .
  • the first interlayer insulating film 103 is an insulating film made of a material having lower relative dielectric constant than that of the silicon oxide film.
  • a film such as Hydrogen Silsesquioxane, Methyl Silsesquioxane (MSQ), Poly arylether, Benzocyclobutene, Polytetrafluoroethylene, Xerogel or Aerogel is formed by the spin-on method.
  • a film such as SiOF film, CF film, Parylene or SiOC film is formed by the CVD (Chemical Vapor Deposition) method.
  • the relative dielectric constants of these materials range from about 1.8 to 3.7.
  • a second interlayer insulating film 104 is formed on the first interlayer insulating film 103 .
  • a silicon nitride film (whose relative dielectric constant is 7.4), a silicon oxide film (whose relative dielectric constant ranges from 4.3 to 4.5), a silicon carbide film (whose relative dielectric constant ranges from 4.3 to 4.7) or the like is used.
  • a photoresist 105 having a pattern with openings above regions in which the copper wirings are to be formed is formed on the second interlayer insulating film 104 by photolithography.
  • the second interlayer insulating film 104 and the first interlayer insulating film 103 are etched in this order by anisotropic dry etching with high etching rate in a direction of depth of the silicon substrate 101 , to expose an upper surface of the underlying insulating film 102 .
  • a recess 106 having a bottom surface defined by the upper surface of the underlying insulating film 102 and a side surface defined by a sidewall of the first interlayer insulating film 103 and a sidewall of the second interlayer insulating film 104 .
  • the photoresist 105 is removed by ashing process using oxygen gas plasma 107 .
  • the ashing process is performed under a plasma forming condition that the RF power is 900 W, the chamber pressure is 133 Pa, the oxygen flow is 2000 sccm and the substrate temperature is 200° C.
  • a tantalum nitride (TaN) film (not shown) is entirely formed by sputtering method and then a copper film is so formed as to have such a film thickness as to fill the inside of the recess 106 by sputtering method or plating method.
  • the copper film and the TaN film are polished by the CMP (Chemical Mechanical Polishing) method until an upper surface of the second interlayer insulating film 104 is exposed.
  • the TaN film is formed in order to prevent diffusion of copper atoms of the copper wiring 109 into the first and second interlayer insulating films 103 and 104 .
  • the ashing process using the oxygen gas plasma 107 is performed under the plasma forming condition that the chamber pressure is 133 Pa and the substrate temperature is 200° C. in the step of removing the photoresist 105 (FIG. 16).
  • an insulating film including Si—C n H 2n+1 bond (n: natural number) therein such as an MSQ film or an SiOC film including Si—CH 3 bond
  • the Si—CH 3 bond in the film is decomposed by the oxygen gas plasma 107 into Si—OH bond, as shown in the chemical equation (1):
  • FIG. 18 is a graph showing an infrared absorption spectrum of an MSQ film with respect to the sidewall portion of the first interlayer insulating film 103 in a case where the MSQ film is adopted as the first interlayer insulating film 103 . It can be seen from FIG. 18 that a spectrum caused by Si—OH bond, which does not exist before performing the ashing process (before irradiation of gas plasma), is generated after performing the ashing process (after irradiation of gas plasma).
  • the Si—OH bond has an orientational polarization component, the relative dielectric constant of the first interlayer insulating film 103 in which the damage layer 110 exists is higher than that of the first interlayer insulating film 103 in which no damage layer 110 exists. Further, since the Si—OH bond becomes an adsorption site of moisture in the atmosphere, a lot of absorbed moisture exists in the damage layer 110 and therefore the relative dielectric constant of the first interlayer insulating film 103 becomes still higher.
  • FIG. 19 is a graph showing variation in relative dielectric constant of the first interlayer insulating film 103 between before and after performing the ashing process for removing the photoresist 105 .
  • the relative dielectric constant after performing the ashing process (after irradiation of gas plasma) is higher than that before performing the ashing process (before irradiation of gas plasma) by 48%.
  • the background-art method of forming a buried copper wiring has the following problem: when the insulating film including Si—C n H 2n+1 bond is adopted as the first interlayer insulating film 103 , much of the Si—C n H 2n+1 bond in the film is changed into Si—OH bond through the ashing process for removing the photoresist 105 and that causes a rise in relative dielectric constant of the first interlayer insulating film 103 , leading to an increase in wiring capacitance.
  • the present invention is directed to a method of forming a dielectric film.
  • the method of forming a dielectric film comprises the steps of: (a) forming an insulating film including Si—C n H 2n+1 bond; (b) forming a resist selectively on a main surface of the insulating film; (c) removing the insulating film not covered with the resist to form a recess in the main surface of the insulating film; and (d) performing an ashing process using gas plasma under a condition that the Si—C n H 2n+1 , bond should not be changed to Si—OH bond to remove the resist.
  • the Si—C n H 2n+1 bond is changed to Si—H bond in the ashing process under the condition in the step (d).
  • the condition is that oxygen gas plasma is used, the temperature is 25° C. or lower and the chamber pressure ranges from 4 to 70 Pa.
  • the condition is that oxygen gas plasma is used, the temperature is 100° C. or lower and the chamber pressure ranges from 4 to 13.3 Pa.
  • the ashing process is performed by using hydrogen gas plasma or ammonia gas plasma in the step (d).
  • the method of forming a dielectric film of the first aspect further comprises the step of: (e) filling the inside of the recess with a metal film, and in the method, the step (e) is executed after the step (d).
  • the insulating film is formed on an underlying layer in the step (a), and the recess is so formed as not to reach the underlying layer in the step (c).
  • the present invention is also directed to a dielectric film.
  • the dielectric film comprises: an insulating film including Si—C n H 2n+1 bond; a recess formed selectively in a main surface of the insulating film; and a surface protective layer including Si—H bond, being formed in a surface of the insulating film in an inner wall of the recess.
  • the dielectric film of the sixth aspect further comprises: a metal film for filling the inside of the recess.
  • the dielectric film is formed on an underlying layer, and the recess is so formed, extending from the main surface of the insulating film, as not to reach the underlying layer.
  • the Si—H bond exists in the surface protective layer. Therefore, the insulating film of the sixth aspect can suppress or avoid a rise in relative dielectric constant of the insulating film, as compared with an insulating film in which a layer including the Si—OH bond, instead of the surface protective layer including the Si—H bond, is formed in its surface.
  • An object of the present invention is to provide a method of forming a dielectric film and a structure thereof, which can suppress a rise in relative dielectric constant of an interlayer insulating film, which is caused by a change of Si—C n H 2n+1 bond in the film into Si—OH bond, in a buried wiring structure in which an insulating film including Si—C n H 2n+1 bond is adopted as the interlayer insulating film.
  • FIGS. 1 to 5 are cross sections showing a method of forming a buried copper wiring in accordance with a first preferred embodiment step by step;
  • FIG. 6 is a graph showing an infrared absorption spectrum of an MSQ film with respect to a sidewall portion of a first interlayer insulating film
  • FIG. 7 is a graph showing variation in dielectric constant of the first interlayer insulating film between before and after performing an ashing process
  • FIG. 8 is a graph showing a measurement result of the amount of Si—H bond generated in the first interlayer insulating film after irradiation of oxygen gas plasma under varying chamber pressures;
  • FIG. 9 is a graph showing a measurement result of the amount of Si—OH bond generated in the first interlayer insulating film after irradiation of oxygen gas plasma under varying substrate temperatures;
  • FIGS. 10 and 11 are cross sections each showing a step in a method of forming a buried copper wiring in accordance with a second preferred embodiment
  • FIG. 12 is a cross section showing a structure formed by a method of forming a buried copper wiring in accordance with a third preferred embodiment
  • FIGS. 13 to 17 are cross sections showing a method of forming a buried copper wiring in the background art step by step
  • FIG. 18 is a graph showing an infrared absorption spectrum of an MSQ film with respect to a sidewall portion of the first interlayer insulating film.
  • FIG. 19 is a graph showing variation in dielectric constant of the first interlayer insulating film between before and after performing an ashing process.
  • FIGS. 1 to 5 are cross sections showing a method of forming a buried copper wiring in accordance with the first preferred embodiment step by step.
  • an underlying insulating film 2 made of silicon oxide film is formed on a silicon substrate 1 .
  • semiconductor elements such as transistors are formed in the silicon substrate 1 and the underlying insulating film 2 .
  • source/drain regions are selectively formed in an upper surface of the silicon substrate 1 and a gate electrode is selectively formed on the upper surface of the silicon substrate 1 .
  • source/drain wirings connected to the source/drain regions are selectively formed in the underlying insulating film 2 .
  • a first interlayer insulating film 3 functioning as a dielectric film is formed on the underlying insulating film 2 .
  • the first interlayer insulating film 3 may be directly formed on the silicon substrate 1 in which the semiconductor elements are formed, instead of being formed on the underlying insulating film 2 .
  • the first interlayer insulating film 3 is an insulating film made of a material having lower relative dielectric constant than that of the silicon oxide film which is a general insulating film.
  • the first interlayer insulating film 3 for example, a film such as Hydrogen Silsesquioxane, Methyl Silsesquioxane (MSQ), Poly arylether, Benzocyclobutene, Polytetrafluoroethylene, Xerogel or Aerogel is formed by the spin-on method. Alternatively, a film such as SiOF film, CF film, Parylene or SiOC film is formed by the CVD method. In the first preferred embodiment, as the first interlayer insulating film 3 , an insulating film (MSQ film in this preferred embodiment) including Si—C n H 2n+1 bond therein is adopted.
  • a second interlayer insulating film 4 is formed on the first interlayer insulating film 3 .
  • a silicon nitride film, a silicon oxide film, a silicon carbide film or the like is used as the material of the second interlayer insulating film 4 .
  • the second interlayer insulating film 4 may not be necessarily formed.
  • a photoresist 5 having a pattern with openings above regions in which the copper wirings are to be formed is formed on the second interlayer insulating film 4 by photolithography.
  • the photoresist 5 is formed on the first interlayer insulating film 3 .
  • the second interlayer insulating film 4 and the first interlayer insulating film 3 are etched in this order by anisotropic dry etching with high etching rate in a direction of depth of the silicon substrate 1 , to expose an upper surface of the underlying insulating film 2 .
  • a recess 6 having a bottom surface defined by the upper surface of the underlying insulating film 2 and an inner wall defined by a sidewall of the first interlayer insulating film 3 and a sidewall of the second interlayer insulating film 4 .
  • the photoresist 5 is removed by ashing process using an oxygen gas plasma 7 .
  • the ashing process is performed under a plasma forming condition that the RF power is 300 W, the chamber pressure is 30 Pa, the oxygen flow is 100 sccm and the substrate temperature is 25° C.
  • a surface protective layer 8 is formed inside the sidewall of the first interlayer insulating film 3 .
  • FIG. 6 is a graph showing an infrared absorption spectrum of the MSQ film with respect to the sidewall portion of the first interlayer insulating film 3 . It can be seen from FIG.
  • Si—H bond has no orientational polarization component and does not become an adsorption site of moisture in the atmosphere. Therefore, even if the surface protective layer 8 including Si—H bond is formed inside the sidewall of the first interlayer insulating film 3 , Si—H bond does not cause a rise in relative dielectric constant of the first interlayer insulating film 3 .
  • FIG. 7 is a graph showing variation in relative dielectric constant of the first interlayer insulating film 3 between before and after performing the ashing process for removing the photoresist 5 . It can be seen from FIG. 7 that the rise in relative dielectric constant after performing the ashing process as compared with before performing the ashing process is suppressed to 14% (48% in FIG. 19 of the background art).
  • a tantalum nitride (TaN) film (not shown) is entirely formed by sputtering method and then a copper film is so formed as to have such a film thickness as to fill the inside of the recess 6 by sputtering method or plating method.
  • the copper film and the TaN film are polished by the CMP method until an upper surface of the second interlayer insulating film 4 is exposed.
  • the TaN film is formed in order to prevent diffusion of copper atoms of the copper wiring 9 into the first and second interlayer insulating films 3 and 4 .
  • FIG. 8 is a graph showing a measurement result of the amount of Si—H bond generated in the first interlayer insulating film 3 after irradiation of the oxygen gas plasma 7 under varying chamber pressures.
  • the amount of Si—H on the vertical axis is represented by an area value for absorption of the infrared absorption spectrum, which is caused by Si—H bond.
  • the amount of Si—H decreases as the chamber pressure rises and when the substrate temperature is 25° C., for example, almost no Si—H bond is generated when the chamber pressure becomes over 70 Pa.
  • the amount of Si—OH decreases as the chamber pressure falls and when the substrate temperature is 25° C., for example, almost no Si—OH bond is generated when the chamber pressure becomes 70 Pa or lower. Therefore, in order to generate Si—H bond, instead of Si—OH bond, in the fist interlayer insulating film 3 after irradiation of the oxygen gas plasma 7 , when the substrate temperature is 25° C., for example, it is only necessary to set the upper limit of the chamber pressure to 70 Pa. Since it becomes difficult to provide the oxygen gas plasma 7 stably when the chamber pressure becomes below 4 Pa, however, it is necessary to set the lower limit of the chamber pressure to 4 Pa.
  • FIG. 9 is a graph showing a measurement result of the amount of Si—OH bond generated in the first interlayer insulating film 3 after irradiation of the oxygen gas plasma 7 under fixed chamber pressure of 106 Pa and varying substrate temperatures.
  • the amount of Si—OH on the vertical axis is represented by an area value for absorption of the infrared absorption spectrum, which is caused by Si—OH bond.
  • the amount of Si—OH bond decreases as the substrate temperature falls, in other words, it becomes likely to generate the Si—H bond depending on the condition of chamber pressure.
  • the Si—H bond can be obtained by the ashing process for removing the photoresist 5 under the condition that the chamber pressure ranges from 4 to 70 Pa when the substrate temperature is 25° C. or lower or the chamber pressure ranges from 4 to 13.3 Pa when the substrate temperature is 100° C. or lower, and further no Si—OH bond is generated under the same condition.
  • the ashing process for removing the photoresist 5 is performed by using the oxygen gas plasma under the condition that the chamber pressure ranges from 4 to 70 Pa when the substrate temperature is 25° C. or lower or the chamber pressure ranges from 4 to 13.3 Pa when the substrate temperature is 100° C. or lower.
  • the surface protective layer 8 including the Si—H bond, not including the Si—OH bond is formed in the surface of the first interlayer insulating film 3 in the inner wall of the recess 6 .
  • FIGS. 10 and 11 are cross sections each showing a step in a method of forming a buried copper wiring in accordance with the second preferred embodiment.
  • the oxygen gas plasma is used in the ashing process for removing the photoresist 5 (FIG. 4) in the first preferred embodiment
  • a mixed gas of nitrogen and hydrogen as shown in FIG. 10 or an ammonia gas as shown in FIG. 11 may be used, instead of the oxygen gas.
  • Other steps in the method of forming a buried copper wiring of the second preferred embodiment are the same as those in the first preferred embodiment.
  • the chemical equation in a case of using the mixed gas of nitrogen and hydrogen is as follows:
  • the Si—CH 3 bond is decomposed and Si—H bond is generated both in the cases. Therefore, like in the first preferred embodiment, it is possible to form the surface protective layer 8 including the Si—H bond, not including the Si—OH bond.
  • the nitrogen gas is mixed from a safety standpoint and may not be necessarily mixed from a standpoint of generation of the Si—H bond.
  • the surface protective layer 8 including the Si—H bond, not including the Si—OH bond in the surface of the first interlayer insulating film 3 in the inner wall of the recess 6 by performing the ashing process using the mixed gas of nitrogen and hydrogen or the ammonia gas. Therefore, it becomes possible to avoid a rise in relative dielectric constant of the first interlayer insulating film 3 .
  • the recess 6 having the bottom surface defined by the upper surface of the underlying insulating film 2 is formed in the etching step of FIG. 3. At that time, there may be a case where the etching is stopped before the upper surface of the underlying insulating film 2 is exposed, to form the recess 6 having the bottom surface defined by the first interlayer insulating film 3 .
  • FIG. 12 is a cross section showing a structure formed by a method of forming a buried copper wiring in accordance with the third preferred embodiment.
  • the surface protective layer 8 including the Si—H bond, not including the Si—OH bond in the surface of the first interlayer insulating film 3 in the inner wall (i.e., the side surface and the bottom surface) of the recess 6 .
  • the inner wall i.e., the side surface and the bottom surface

Abstract

A first interlayer insulating film (3) having low dielectric constant is formed on an underlying insulating film (2) and a second interlayer insulating film (4) is formed on the first interlayer insulating film (3). Subsequently, a photoresist (5) having a pattern with openings above regions in which copper wirings are to be formed is formed on the second interlayer insulating film (4). Using the photoresist (5) as an etching mask, the second interlayer insulating film (4) and the first interlayer insulating film (3) are etched, to form a recess (6). Next, an ashing process using oxygen gas plasma (7) is performed, to remove the photoresist (5). This ashing process is performed under a plasma forming condition that the RF power is 300 W, the chamber pressure is 30 Pa, the oxygen flow is 100 sccm and the substrate temperature is 25 ° C. That provides a method of forming a dielectric film and a structure thereof, which allows suppression of a rise in dielectric constant of an interlayer insulating film, which is caused by a change of Si—CnH2n+1 bond into Si—OH bond in the film.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method of forming a dielectric film and a structure thereof, and more particularly to a method of forming an interlayer dielectric film in a buried wiring structure and a structure thereof. [0002]
  • 2. Description of the Background Art [0003]
  • Especially in a system LSI after the 0.18-micron generation, in order to achieve speed-up of devices, it is important to reduce signal delay of the devices. The signal delay of a device is a sum of signal delay in transistors and that in interconnection. As reduction in wiring pitch rapidly proceeds, the effect of the signal delay in interconnection becomes larger than that in transistors. Since the signal delay in interconnection is in proportion to the RC product (wiring resistance×wiring capacitance), in order to reduce the signal delay in interconnection, it is necessary to reduce the wiring resistance or the wiring capacitance. Therefore, an insulating film having lower relative dielectric constant than that of a silicon oxide film which is a general insulating film is used as an interlayer insulating film and a copper wiring having lower wiring resistance than that of an aluminum wiring which is a general metal wiring is used as a buried wiring, to reduce the signal delay in interconnection. [0004]
  • FIGS. [0005] 13 to 17 are cross sections showing a method of forming a buried copper wiring in the background art step by step. First, referring to FIG. 13, an underlying insulating film 102 made of silicon oxide film is formed on a silicon substrate 101. Though not shown in FIG. 13, semiconductor elements such as transistors are formed in the silicon substrate 101 and the underlying insulating film 102. For example, source/drain regions are selectively formed in an upper surface of the silicon substrate 101 and a gate electrode is selectively formed on the upper surface of the silicon substrate 101. Further, source/drain wirings connected to the source/drain regions are selectively formed in the underlying insulating film 102.
  • Subsequently, a first [0006] interlayer insulating film 103 is formed on the underlying insulating film 102. The first interlayer insulating film 103 is an insulating film made of a material having lower relative dielectric constant than that of the silicon oxide film. For example, a film such as Hydrogen Silsesquioxane, Methyl Silsesquioxane (MSQ), Poly arylether, Benzocyclobutene, Polytetrafluoroethylene, Xerogel or Aerogel is formed by the spin-on method. Alternatively, a film such as SiOF film, CF film, Parylene or SiOC film is formed by the CVD (Chemical Vapor Deposition) method. The relative dielectric constants of these materials range from about 1.8 to 3.7.
  • Subsequently, a second [0007] interlayer insulating film 104 is formed on the first interlayer insulating film 103. As the material of the second interlayer insulating film 104, a silicon nitride film (whose relative dielectric constant is 7.4), a silicon oxide film (whose relative dielectric constant ranges from 4.3 to 4.5), a silicon carbide film (whose relative dielectric constant ranges from 4.3 to 4.7) or the like is used.
  • Next, referring to FIG. 14, a [0008] photoresist 105 having a pattern with openings above regions in which the copper wirings are to be formed is formed on the second interlayer insulating film 104 by photolithography.
  • Next, referring to FIG. 15, using the [0009] photoresist 105 as an etching mask, the second interlayer insulating film 104 and the first interlayer insulating film 103 are etched in this order by anisotropic dry etching with high etching rate in a direction of depth of the silicon substrate 101, to expose an upper surface of the underlying insulating film 102. Through this step formed is a recess 106 having a bottom surface defined by the upper surface of the underlying insulating film 102 and a side surface defined by a sidewall of the first interlayer insulating film 103 and a sidewall of the second interlayer insulating film 104.
  • Next, referring to FIG. 16, the [0010] photoresist 105 is removed by ashing process using oxygen gas plasma 107. The ashing process is performed under a plasma forming condition that the RF power is 900 W, the chamber pressure is 133 Pa, the oxygen flow is 2000 sccm and the substrate temperature is 200° C.
  • Subsequently, a tantalum nitride (TaN) film (not shown) is entirely formed by sputtering method and then a copper film is so formed as to have such a film thickness as to fill the inside of the [0011] recess 106 by sputtering method or plating method. Next, referring to FIG. 17, the copper film and the TaN film are polished by the CMP (Chemical Mechanical Polishing) method until an upper surface of the second interlayer insulating film 104 is exposed. Through this step formed is a copper wiring 109 for filling the inside of the recess 106 with the not-shown TaN film interposed therebetween. Further, the TaN film is formed in order to prevent diffusion of copper atoms of the copper wiring 109 into the first and second interlayer insulating films 103 and 104.
  • Thus, in the background-art method of forming a buried copper wiring, the ashing process using the [0012] oxygen gas plasma 107 is performed under the plasma forming condition that the chamber pressure is 133 Pa and the substrate temperature is 200° C. in the step of removing the photoresist 105 (FIG. 16). For this reason, when an insulating film including Si—CnH2n+1 bond (n: natural number) therein, such as an MSQ film or an SiOC film including Si—CH3 bond, is used as the first interlayer insulating film 103, the Si—CH3 bond in the film is decomposed by the oxygen gas plasma 107 into Si—OH bond, as shown in the chemical equation (1):
  • Si−CH3+2O2→Si−OH+CO2+H2O   (1)
  • As a result, as shown in FIG. 16, a [0013] damage layer 110 including a lot of Si—OH bond is formed inside the inner wall of the first interlayer insulating film 103. FIG. 18 is a graph showing an infrared absorption spectrum of an MSQ film with respect to the sidewall portion of the first interlayer insulating film 103 in a case where the MSQ film is adopted as the first interlayer insulating film 103. It can be seen from FIG. 18 that a spectrum caused by Si—OH bond, which does not exist before performing the ashing process (before irradiation of gas plasma), is generated after performing the ashing process (after irradiation of gas plasma).
  • Since the Si—OH bond has an orientational polarization component, the relative dielectric constant of the first interlayer [0014] insulating film 103 in which the damage layer 110 exists is higher than that of the first interlayer insulating film 103 in which no damage layer 110 exists. Further, since the Si—OH bond becomes an adsorption site of moisture in the atmosphere, a lot of absorbed moisture exists in the damage layer 110 and therefore the relative dielectric constant of the first interlayer insulating film 103 becomes still higher.
  • FIG. 19 is a graph showing variation in relative dielectric constant of the first [0015] interlayer insulating film 103 between before and after performing the ashing process for removing the photoresist 105. The relative dielectric constant after performing the ashing process (after irradiation of gas plasma) is higher than that before performing the ashing process (before irradiation of gas plasma) by 48%.
  • Thus, the background-art method of forming a buried copper wiring has the following problem: when the insulating film including Si—C[0016] nH2n+1 bond is adopted as the first interlayer insulating film 103, much of the Si—CnH2n+1 bond in the film is changed into Si—OH bond through the ashing process for removing the photoresist 105 and that causes a rise in relative dielectric constant of the first interlayer insulating film 103, leading to an increase in wiring capacitance.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to a method of forming a dielectric film. According to a first aspect of the present invention, the method of forming a dielectric film comprises the steps of: (a) forming an insulating film including Si—C[0017] nH2n+1 bond; (b) forming a resist selectively on a main surface of the insulating film; (c) removing the insulating film not covered with the resist to form a recess in the main surface of the insulating film; and (d) performing an ashing process using gas plasma under a condition that the Si—CnH2n+1, bond should not be changed to Si—OH bond to remove the resist.
  • According to a second aspect of the present invention, in the method of forming a dielectric film of the first aspect, the Si—C[0018] nH2n+1 bond is changed to Si—H bond in the ashing process under the condition in the step (d).
  • According to a third aspect of the present invention, in the method of forming a dielectric film of the first aspect, the condition is that oxygen gas plasma is used, the temperature is 25° C. or lower and the chamber pressure ranges from 4 to 70 Pa. [0019]
  • According to a fourth aspect of the present invention, in the method of forming a dielectric film of the first aspect, the condition is that oxygen gas plasma is used, the temperature is 100° C. or lower and the chamber pressure ranges from 4 to 13.3 Pa. [0020]
  • According to a fifth aspect of the present invention, in the method of forming a dielectric film of the first aspect, the ashing process is performed by using hydrogen gas plasma or ammonia gas plasma in the step (d). [0021]
  • Preferably, the method of forming a dielectric film of the first aspect further comprises the step of: (e) filling the inside of the recess with a metal film, and in the method, the step (e) is executed after the step (d). [0022]
  • Preferably, the insulating film is formed on an underlying layer in the step (a), and the recess is so formed as not to reach the underlying layer in the step (c). [0023]
  • The present invention is also directed to a dielectric film. According to a sixth aspect of the present invention, the dielectric film comprises: an insulating film including Si—C[0024] nH2n+1 bond; a recess formed selectively in a main surface of the insulating film; and a surface protective layer including Si—H bond, being formed in a surface of the insulating film in an inner wall of the recess.
  • Preferably, the dielectric film of the sixth aspect further comprises: a metal film for filling the inside of the recess. [0025]
  • Preferably, the dielectric film is formed on an underlying layer, and the recess is so formed, extending from the main surface of the insulating film, as not to reach the underlying layer. [0026]
  • In the method of forming an insulating film of the first and second aspects, since the Si—C[0027] nH2n+1 bond included in the surface of the insulating film in the inner wall of the recess is not changed to the Si—OH bond through the ashing process in the step (d), it is possible to suppress a rise in relative dielectric constant of the insulating film.
  • In the method of forming an insulating film of the third and fourth aspects, it is possible to appropriately change the Si—C[0028] nH2n+1 bond included in the insulating film to the Si—H bond.
  • In the method of forming an insulating film of the fifth aspect, it is possible to avoid the change of the Si—C[0029] nH2+1 bond included in the insulating film into the Si—OH bond and suppress a rise in relative dielectric constant of the insulating film, which is caused by the Si—OH bond.
  • In the insulating film of the sixth aspect, the Si—H bond exists in the surface protective layer. Therefore, the insulating film of the sixth aspect can suppress or avoid a rise in relative dielectric constant of the insulating film, as compared with an insulating film in which a layer including the Si—OH bond, instead of the surface protective layer including the Si—H bond, is formed in its surface. [0030]
  • An object of the present invention is to provide a method of forming a dielectric film and a structure thereof, which can suppress a rise in relative dielectric constant of an interlayer insulating film, which is caused by a change of Si—C[0031] nH2n+1 bond in the film into Si—OH bond, in a buried wiring structure in which an insulating film including Si—CnH2n+1 bond is adopted as the interlayer insulating film.
  • These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.[0032]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. [0033] 1 to 5 are cross sections showing a method of forming a buried copper wiring in accordance with a first preferred embodiment step by step;
  • FIG. 6 is a graph showing an infrared absorption spectrum of an MSQ film with respect to a sidewall portion of a first interlayer insulating film; [0034]
  • FIG. 7 is a graph showing variation in dielectric constant of the first interlayer insulating film between before and after performing an ashing process; [0035]
  • FIG. 8 is a graph showing a measurement result of the amount of Si—H bond generated in the first interlayer insulating film after irradiation of oxygen gas plasma under varying chamber pressures; [0036]
  • FIG. 9 is a graph showing a measurement result of the amount of Si—OH bond generated in the first interlayer insulating film after irradiation of oxygen gas plasma under varying substrate temperatures; [0037]
  • FIGS. 10 and 11 are cross sections each showing a step in a method of forming a buried copper wiring in accordance with a second preferred embodiment; [0038]
  • FIG. 12 is a cross section showing a structure formed by a method of forming a buried copper wiring in accordance with a third preferred embodiment; [0039]
  • FIGS. [0040] 13 to 17 are cross sections showing a method of forming a buried copper wiring in the background art step by step;
  • FIG. 18 is a graph showing an infrared absorption spectrum of an MSQ film with respect to a sidewall portion of the first interlayer insulating film; and [0041]
  • FIG. 19 is a graph showing variation in dielectric constant of the first interlayer insulating film between before and after performing an ashing process.[0042]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS The First Preferred Embodiment
  • FIGS. [0043] 1 to 5 are cross sections showing a method of forming a buried copper wiring in accordance with the first preferred embodiment step by step. First, referring to FIG. 1, an underlying insulating film 2 made of silicon oxide film is formed on a silicon substrate 1. Though not shown in FIG. 1, semiconductor elements such as transistors are formed in the silicon substrate 1 and the underlying insulating film 2. For example, source/drain regions are selectively formed in an upper surface of the silicon substrate 1 and a gate electrode is selectively formed on the upper surface of the silicon substrate 1. Further, source/drain wirings connected to the source/drain regions are selectively formed in the underlying insulating film 2.
  • Subsequently, a first [0044] interlayer insulating film 3 functioning as a dielectric film is formed on the underlying insulating film 2. The first interlayer insulating film 3, however, may be directly formed on the silicon substrate 1 in which the semiconductor elements are formed, instead of being formed on the underlying insulating film 2. The first interlayer insulating film 3 is an insulating film made of a material having lower relative dielectric constant than that of the silicon oxide film which is a general insulating film. As the first interlayer insulating film 3, for example, a film such as Hydrogen Silsesquioxane, Methyl Silsesquioxane (MSQ), Poly arylether, Benzocyclobutene, Polytetrafluoroethylene, Xerogel or Aerogel is formed by the spin-on method. Alternatively, a film such as SiOF film, CF film, Parylene or SiOC film is formed by the CVD method. In the first preferred embodiment, as the first interlayer insulating film 3, an insulating film (MSQ film in this preferred embodiment) including Si—CnH2n+1 bond therein is adopted.
  • Subsequently, a second [0045] interlayer insulating film 4 is formed on the first interlayer insulating film 3. As the material of the second interlayer insulating film 4, a silicon nitride film, a silicon oxide film, a silicon carbide film or the like is used. The second interlayer insulating film 4, however, may not be necessarily formed.
  • Next, referring to FIG. 2, a [0046] photoresist 5 having a pattern with openings above regions in which the copper wirings are to be formed is formed on the second interlayer insulating film 4 by photolithography. When the second interlayer insulating film 4 is not formed, the photoresist 5 is formed on the first interlayer insulating film 3.
  • Next, referring to FIG. 3, using the [0047] photoresist 5 as an etching mask, the second interlayer insulating film 4 and the first interlayer insulating film 3 are etched in this order by anisotropic dry etching with high etching rate in a direction of depth of the silicon substrate 1, to expose an upper surface of the underlying insulating film 2. Through this step formed is a recess 6 having a bottom surface defined by the upper surface of the underlying insulating film 2 and an inner wall defined by a sidewall of the first interlayer insulating film 3 and a sidewall of the second interlayer insulating film 4.
  • Next, referring to FIG. 4, the [0048] photoresist 5 is removed by ashing process using an oxygen gas plasma 7. The ashing process is performed under a plasma forming condition that the RF power is 300 W, the chamber pressure is 30 Pa, the oxygen flow is 100 sccm and the substrate temperature is 25° C. When the ashing process is performed under such a condition as above, as shown in FIG. 4, a surface protective layer 8 is formed inside the sidewall of the first interlayer insulating film 3. FIG. 6 is a graph showing an infrared absorption spectrum of the MSQ film with respect to the sidewall portion of the first interlayer insulating film 3. It can be seen from FIG. 6 that a spectrum caused by Si—H bond, which does not exist before performing the ashing process (before irradiation of the oxygen gas plasma 7 on the first interlayer insulating film 3), is generated after performing the ashing process (after irradiation of the oxygen gas plasma 7 on the first interlayer insulating film 3). The reason is that Si—CH3 bond in the MSQ film is decomposed by the oxygen gas plasma 7 into Si—H bond, as shown in the chemical equation (2):
  • Si−CH3+O2→Si−H+CO+H2O   (2)
  • Unlike Si—OH bond, Si—H bond has no orientational polarization component and does not become an adsorption site of moisture in the atmosphere. Therefore, even if the surface [0049] protective layer 8 including Si—H bond is formed inside the sidewall of the first interlayer insulating film 3, Si—H bond does not cause a rise in relative dielectric constant of the first interlayer insulating film 3.
  • FIG. 7 is a graph showing variation in relative dielectric constant of the first [0050] interlayer insulating film 3 between before and after performing the ashing process for removing the photoresist 5. It can be seen from FIG. 7 that the rise in relative dielectric constant after performing the ashing process as compared with before performing the ashing process is suppressed to 14% (48% in FIG. 19 of the background art).
  • Subsequently, a tantalum nitride (TaN) film (not shown) is entirely formed by sputtering method and then a copper film is so formed as to have such a film thickness as to fill the inside of the [0051] recess 6 by sputtering method or plating method. Next, referring to FIG. 5, the copper film and the TaN film are polished by the CMP method until an upper surface of the second interlayer insulating film 4 is exposed. Through this step formed is a copper wiring 9 for filling the inside of the recess 6 with the not-shown TaN film interposed therebetween. Further, the TaN film is formed in order to prevent diffusion of copper atoms of the copper wiring 9 into the first and second interlayer insulating films 3 and 4.
  • The condition to obtain Si—H bond, instead of Si—OH bond, by the ashing process for removing the [0052] photoresist 5 is as follows.
  • FIG. 8 is a graph showing a measurement result of the amount of Si—H bond generated in the first [0053] interlayer insulating film 3 after irradiation of the oxygen gas plasma 7 under varying chamber pressures. In FIG. 8, the amount of Si—H on the vertical axis is represented by an area value for absorption of the infrared absorption spectrum, which is caused by Si—H bond. As can be seen from FIG. 8, the amount of Si—H decreases as the chamber pressure rises and when the substrate temperature is 25° C., for example, almost no Si—H bond is generated when the chamber pressure becomes over 70 Pa. Further, the amount of Si—OH decreases as the chamber pressure falls and when the substrate temperature is 25° C., for example, almost no Si—OH bond is generated when the chamber pressure becomes 70 Pa or lower. Therefore, in order to generate Si—H bond, instead of Si—OH bond, in the fist interlayer insulating film 3 after irradiation of the oxygen gas plasma 7, when the substrate temperature is 25° C., for example, it is only necessary to set the upper limit of the chamber pressure to 70 Pa. Since it becomes difficult to provide the oxygen gas plasma 7 stably when the chamber pressure becomes below 4 Pa, however, it is necessary to set the lower limit of the chamber pressure to 4 Pa.
  • Further, as shown in FIG. 8, when the substrate temperature is 100° C., no Si—OH bond is detected and Si—H bond is generated in the [0054] interlayer insulating film 3 both in the cases where the chamber pressure is 4 Pa and 13.3 Pa. Therefore, when the substrate temperature is 100° C., the effect of the present invention can be produced at least in the range of the chamber pressure from 4 to 13.3 Pa.
  • FIG. 9 is a graph showing a measurement result of the amount of Si—OH bond generated in the first [0055] interlayer insulating film 3 after irradiation of the oxygen gas plasma 7 under fixed chamber pressure of 106 Pa and varying substrate temperatures. In FIG. 9, the amount of Si—OH on the vertical axis is represented by an area value for absorption of the infrared absorption spectrum, which is caused by Si—OH bond. As can be seen from FIG. 9, the amount of Si—OH bond decreases as the substrate temperature falls, in other words, it becomes likely to generate the Si—H bond depending on the condition of chamber pressure.
  • Therefore, it can be seen from FIGS. 8 and 9 that the Si—H bond can be obtained by the ashing process for removing the [0056] photoresist 5 under the condition that the chamber pressure ranges from 4 to 70 Pa when the substrate temperature is 25° C. or lower or the chamber pressure ranges from 4 to 13.3 Pa when the substrate temperature is 100° C. or lower, and further no Si—OH bond is generated under the same condition.
  • In the method of forming a buried copper wiring of the first preferred embodiment, the ashing process for removing the [0057] photoresist 5 is performed by using the oxygen gas plasma under the condition that the chamber pressure ranges from 4 to 70 Pa when the substrate temperature is 25° C. or lower or the chamber pressure ranges from 4 to 13.3 Pa when the substrate temperature is 100° C. or lower. Through this ashing process formed is the surface protective layer 8 including the Si—H bond, not including the Si—OH bond, in the surface of the first interlayer insulating film 3 in the inner wall of the recess 6. As a result, it becomes possible to suppress a rise in relative dielectric constant of the first interlayer insulating film 3.
    • The Second Preferred Embodiment
  • FIGS. 10 and 11 are cross sections each showing a step in a method of forming a buried copper wiring in accordance with the second preferred embodiment. Though the oxygen gas plasma is used in the ashing process for removing the photoresist [0058] 5 (FIG. 4) in the first preferred embodiment, a mixed gas of nitrogen and hydrogen as shown in FIG. 10 or an ammonia gas as shown in FIG. 11 may be used, instead of the oxygen gas. Other steps in the method of forming a buried copper wiring of the second preferred embodiment are the same as those in the first preferred embodiment. The chemical equation in a case of using the mixed gas of nitrogen and hydrogen is as follows:
  • Si−CH3+H2+N2→Si−H+CH4+N2  (3)
  • The chemical equation in a case of using the ammonia gas is as follows: [0059]
  • Si−CH3+NH3→Si−H+CH4+N+H   (4)
  • It can be seen from the equations (3) and (4) that the Si—CH[0060] 3 bond is decomposed and Si—H bond is generated both in the cases. Therefore, like in the first preferred embodiment, it is possible to form the surface protective layer 8 including the Si—H bond, not including the Si—OH bond. In the case of using the mixed gas of nitrogen and hydrogen, the nitrogen gas is mixed from a safety standpoint and may not be necessarily mixed from a standpoint of generation of the Si—H bond.
  • Thus, in the method of forming a buried copper wiring of the second preferred embodiment, it is possible to form the surface [0061] protective layer 8 including the Si—H bond, not including the Si—OH bond, in the surface of the first interlayer insulating film 3 in the inner wall of the recess 6 by performing the ashing process using the mixed gas of nitrogen and hydrogen or the ammonia gas. Therefore, it becomes possible to avoid a rise in relative dielectric constant of the first interlayer insulating film 3.
    • The Third Preferred Embodiment
  • In the above method of forming a buried copper wiring of the first and second preferred embodiments, the [0062] recess 6 having the bottom surface defined by the upper surface of the underlying insulating film 2 is formed in the etching step of FIG. 3. At that time, there may be a case where the etching is stopped before the upper surface of the underlying insulating film 2 is exposed, to form the recess 6 having the bottom surface defined by the first interlayer insulating film 3.
  • Next, the [0063] photoresist 5 is removed by the ashing process using the oxygen gas plasma (in the first preferred embodiment) or the ashing process using the mixed gas of nitrogen and hydrogen or the ammonia gas (in the second preferred embodiment). The ashing process is performed under the same condition as in the first and second preferred embodiments. After that, like in the first and second preferred embodiments, the TaN film is formed and then the copper wiring 9 is formed to fill the inside of the recess 6 with the TaN film interposed therebetween. FIG. 12 is a cross section showing a structure formed by a method of forming a buried copper wiring in accordance with the third preferred embodiment.
  • Thus, in the method of forming a buried copper wiring of the third preferred embodiment, it is possible to form the surface [0064] protective layer 8 including the Si—H bond, not including the Si—OH bond, in the surface of the first interlayer insulating film 3 in the inner wall (i.e., the side surface and the bottom surface) of the recess 6. As a result, it becomes possible to avoid a rise in relative dielectric constant of the first interlayer insulating film 3.
  • While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention. [0065]

Claims (10)

What is claimed is:
1. A method of forming a dielectric film, comprising the steps of:
(a) forming an insulating film including Si—CnH2n+1 bond;
(b) forming a resist selectively on a main surface of said insulating film;
(c) removing said insulating film not covered with said resist to form a recess in said main surface of said insulating film; and
(d) performing an ashing process using gas plasma under a condition that said Si—CnH2n+1 bond should not be changed to Si—OH bond to remove said resist.
2. The method of forming a dielectric film according to claim 1, wherein
said Si—CnH2n+1 bond is changed to Si—H bond in said ashing process under said condition in said step (d).
3. The method of forming a dielectric film according to claim 1, wherein
said condition is that oxygen gas plasma is used, the temperature is 25° C. or lower and the chamber pressure ranges from 4 to 70 Pa.
4. The method of forming a dielectric film according to claim 1, wherein
said condition is that oxygen gas plasma is used, the temperature is 100° C. or lower and the chamber pressure ranges from 4 to 13.3 Pa.
5. The method of forming a dielectric film according to claim 1, wherein
said ashing process is performed by using hydrogen gas plasma or ammonia gas plasma in said step (d).
6. The method of forming a dielectric film according to claim 1, further comprising the step of:
(e) filling the inside of said recess with a metal film, wherein said step (e) is executed after said step (d).
7. The method of forming a dielectric film according to claim 1, wherein
said insulating film is formed on an underlying layer in said step (a), and
said recess is so formed as not to reach said underlying layer in said step (c).
8. A dielectric film, comprising:
an insulating film including Si—CnH2n+1 bond;
a recess formed selectively in a main surface of said insulating film; and
a surface protective layer including Si—H bond, being formed in a surface of said insulating film in an inner wall of said recess.
9. The dielectric film according to claim 8, further comprising:
a metal film for filling the inside of said recess.
10. The dielectric film according to claim 8, wherein
said insulating film is formed on an underlying layer, and
said recess is so formed, extending from said main surface of said insulating film, as not to reach said underlying layer.
US09/963,648 2001-01-05 2001-09-27 Method of forming dielectric film and dielectric film Abandoned US20020090833A1 (en)

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US20020182891A1 (en) 2002-12-05

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