JP2002028289A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a trouble in control caused by an unexpected electric power failure which may rapidly be restored by keeping a controlling state. SOLUTION: A power source substrate mounts a reset control circuit for supplying a reset signal and a return signal to respective electric part controlling substrate. When the reset control circuit supplies a reset signal to the CPUs of the respective electric part controlling substrates, a delay circuit 960 delays the reset signal to the CPU of a man substrate. Consequently, when the power source is turned on, a reset signal to the CPU of the main substrate is started later than that to the CPUs of the other electric part controlling substrates. A counter 971 starts counting when a power disconnection signal comes to a low level. A count up value is set to be equal to or larger than a time until power voltage drops to voltage making control operation impossible since the power disconnection signal comes to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, and a slot machine in which a game is played in accordance with a player's operation. The present invention relates to a gaming machine in which a game is played according to a player's operation.

[0002]

2. Description of the Related Art As an example of a gaming machine, when a game medium such as a game ball is fired into a game area by a launching device, and a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of game media are played. Some prize balls are paid out to players. Further, a variable display unit whose display state can be changed is provided, and when a display result of the variable display unit becomes a predetermined specific display mode, a predetermined game value is provided to the player. There is.

[0003] The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is in a state that is advantageous for a player who is likely to win a hit ball, or is in a state that is advantageous for the player. In other words, the right is to be generated, or the condition for paying out premium game media is easily established.

In a first-type pachinko gaming machine having a variable display section for displaying a special symbol, it is generally known that the display result of the variable display section for displaying a special symbol is a combination of predetermined specific display modes. , "Big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. And
In each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Also,
If a predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time of closing the special winning opening, the big hit gaming state ends.

[0005] Further, among the combinations of display modes other than the combination of "big hits", when a part of the display results of the plurality of variable display portions is not yet derived and displayed, it is already definite or temporary. A state in which the display mode of the variable display unit on which the various display results are derived and displayed satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of "big hit", the result is "missing" and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the payout control board. In the following, since the game control means and other control means control various electric components provided in the gaming machine, they may be referred to as electric component control means.

[0007]

As described above, a gaming machine is equipped with various electric component control means including game control means. Generally, each electric component control means is configured to include a microcomputer. Such an electric component control means generally performs an initialization process when a power supply voltage rises, and starts control from an initial state. Then, an unexpected power interruption such as a power failure occurs, and thereafter, when the power is restored, the state returns to the initial state, so that a problem such as a loss of the game value obtained by the player may occur. In order to prevent such a problem from occurring, the game control is interrupted in response to a predetermined signal generated with a decrease in the power supply voltage value, and the game state at that time is changed to a power supply stop to the game machine. Above all, it may be stored in a storage unit (backup storage unit) that is backed up by a power supply, and may be controlled so as to wait until the power supply is completely stopped. Such a gaming machine restarts the game based on the stored game state if power supply is resumed in a state where the game state is stored in the storage means, and therefore, a disadvantage is given to the player. Is prevented.

However, when the power supply voltage drops for a very short period of time due to an instantaneous interruption of the power supply, the power supply voltage is immediately restored. In such a case, it is conceivable that the control of the microcomputer cannot completely escape from the state of waiting for the power supply to completely stop. In other words, despite the fact that the power supply to the gaming machine is in a normal state,
It is conceivable that the gaming machine control does not return to the normal state.

Therefore, the present invention provides a gaming machine which is configured to save the control state at the time of unexpected power-off or the like, even if an instantaneous power-off of the power supply which recovers in a very short time occurs. It is an object of the present invention to provide a gaming machine that does not hinder the game machine.

[0010]

A gaming machine according to the present invention comprises:
A game machine in which a player can perform a predetermined game, an electric component control means for controlling an electric component provided in the game machine, and an electric component control even if power supply to the game machine is stopped. Storage holding means capable of holding the storage contents of the means,
Power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine, wherein the electric component control means detects that the state of the predetermined power supply has reached a predetermined state by the power supply monitoring means When the power supply is stopped, the power supply stop processing is performed after the power supply stop processing related to the storage of the control state is performed, and the power supply is stopped after a predetermined period elapses after the power supply monitoring unit detects that the power supply monitoring unit has reached the predetermined state. A return signal output unit capable of outputting a return signal for returning from the standby state to the electric component control unit when not performing the standby operation is provided.

The return signal is input to, for example, a reset signal input section of the electric component control means.

The return signal output means may include a timer means capable of measuring a predetermined period.

[0013] For a predetermined period, for example, when the power supply to the gaming machine is cut off, the power supply monitoring means detects that the state of the predetermined power supply has reached a predetermined state, and then the electric component is stopped. It is longer than the time until the control means becomes inoperable.

When there are game control means for controlling the progress of the game and payout control means for controlling the payout of the game medium as the electric component control means, the return signal output means is provided to the payout control means prior to the game control means. Alternatively, a configuration may be employed in which a return signal is output.

A power supply board for generating a voltage used in each electric component control board is provided separately from the electric component control board on which the electric component control means is mounted, and the return signal output means is mounted on the power supply board. May be configured.

[0016] The electric component control means includes those having storage holding means and those not having the memory holding means, and is configured such that the power supply board is provided with a starting order control means for controlling the starting order of each electric component control means. It may be.

The starting order control means may be configured to control the starting order by controlling the output order of the reset signal to each electric component control means.

A game control means for controlling the progress of the game as the electric part control means; and another electric part control means for controlling the electric parts in response to a control signal from the game control means,
The activation sequence control means may be configured to activate the game control means last.

[0019]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing game balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section (special symbol display device) 9 for variably displaying a plurality of types of symbols and a normal symbol display (ordinary symbol display device) 10 using 7-segment LEDs are provided. A variable display device 8 is provided. In the variable display section 9, for example, "left", "middle",
There are three symbol display areas of "right". Variable display device 8
Is provided with a passage gate 11 for guiding a hit ball. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V winning switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, the number of winning balls entering the starting winning opening 14 is displayed.
A start winning storage display 18 having a plurality of display units is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls into the respective winning ports 19 and 24 is determined by setting the corresponding winning port switches 19a and 19a.
19b, 24a and 24b. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Prize ball lamp 5 that lights up when there are remaining prize balls near
1 is provided, and near the other speaker 27, a ball-out lamp 52 is provided, which lights up when the supply ball is out. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and that allows a ball to be lent by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is ready for use. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the number displayed on the symbol display 10 normally changes. When a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17,
If the change of the symbol can be started, the symbol in the variable display section 9 starts rotating. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. When the hit ball wins in the specific winning area while the opening and closing plate 20 is being opened and is detected by the V winning switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. The continuation right is generated a predetermined number of times (for example, 15 rounds)
Permissible.

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol = small hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball dispensing device covered with a prize ball case 40A.

On the back side of the gaming machine, a variable display control unit 29 for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. A payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted;
And a hit ball launching device that launches a hit ball into the game area 7 using the rotational force of a motor. Furthermore, the decoration lamp 25, the game effect LED 28a, the game effect lamp 28
b, 28c, a lamp control board 35 for sending signals to the prize ball lamp 51 and the ball out lamp 52, a voice control board 70 for controlling the generation of voice from the speaker 27, and a launch control for controlling the hit ball launching device. A substrate 91 is also provided.

Further, DC30V, DC21V, DC1
A power supply board 910 on which a power supply circuit for generating 2V and 5V DC is mounted is provided, and a terminal board 1 provided with terminals for outputting various information to the outside of the gaming machine is provided above.
60 are installed. The terminal board 160 has at least an out-of-ball terminal for introducing and outputting the output of the out-of-ball detection switch, an award ball terminal for externally outputting the award ball number signal, and an externally outputting ball lending number signal. A ball lending terminal is provided. In the vicinity of the center, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is provided. In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are supplied to the game effect LEDs 28a, game effect lamps 28b and 28c, the prize ball lamp 51, and the ball cut lamp 52 provided on the frame side. Although the electric relay board A77 for performing the above is shown, other relay boards are provided as necessary for signal relay.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The balls stored in the ball storage tank 38 pass through the guide gutter 39, pass through the ball cut detectors (ball cut switches) 187a and 187b, and are dispensed through the ball supply gutters 186a and 186b, as shown in FIG. The device 97 is reached. The ball out switches 187a and 187b are switches for detecting the presence or absence of a game ball in the game ball passage.
67 is also provided. Hereafter, the ball out switch 187
a, 187b may be expressed as a ball-out switch 187.

The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front face of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed.

A number of prize balls are paid out based on the prize, and the hitting ball supply plate 3 becomes full.
When the game balls are further paid out after reaching 5, the game balls are guided to the surplus ball tray 4 via the surplus ball passage 46. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hitting ball firing device also stops.

Next, the structure of the intermediate base unit installed on the mechanism plate 36 will be described. The intermediate base unit includes the ball supply gutters 186a and 186b and the ball discharging device 9
7 is installed. As shown in FIG. 4, connecting concave protrusions 182 are formed on the upper and lower sides of the intermediate base unit. The connection concave projection 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

A passage member 18 is provided above the intermediate base unit.
4 is fixed. The ball dispensing device 97 is fixed to a lower portion of the passage body 184. The passage body 184 is a payout ball passage 186 that allows two rows of game balls whose flow direction has been changed left and right by the curve gutter 174 (see FIG. 3) to flow down.
a, 186b. Dispensing ball passages 186a, 186b
On the upstream side of the ball, ball breaking switches 187a and 187b are provided. The ball out switches 187a and 187b
It detects the presence or absence of a game ball in the payout ball passages 186a and 186b, and detects a ball out switch 187a or 187b.
Stops detecting the game ball, the rotation of the payout motor (not shown in FIG. 4) in the ball payout device 97 is stopped, and the ball payout is immobilized.

It should be noted that the ball out switches 187a, 187b
Is locked by a locking piece 188 at a position where it can be detected that about 27 to 28 game balls exist in the payout ball paths 186a and 186b. That is, the out-of-ball switches 187a and 187b are the maximum payout amount of one unit of the prize ball (15 in this embodiment) and the maximum payout amount of one unit of the ball lending (100 yen: 25 in this embodiment).
It is installed in a position where it can be confirmed that the above is secured.

The central portion of the passage body 184 is formed in a shape curved right and left so as to reduce the ball pressure of the game ball flowing down inside. And the payout ball passages 186a, 186b
A stop hole 189 is formed therebetween. The mounting boss provided on the intermediate base unit is fitted into the back surface of the stop hole 189. The set screw is screwed in that state,
The passage body 184 is fixed to the intermediate base unit. Before being screwed, the positioning of the passage body 184 can be performed by a locking projection 185 provided on the intermediate base unit.

Below the passage body 184, a ball payout device 97 is provided.
To supply the game balls to the ball, and in the event of failure, the ball payout device 9
A ball stopping device 190 for stopping the supply of game balls to the game ball 7 is provided. The ball dispensing device 97 installed below the ball stopping device 190 is housed inside a rectangular parallelepiped case 198. Protrusions are provided at four places on the left and right of the case 198. The lower end of the case 198 is fitted into an elastic engagement piece provided at a lower portion of the intermediate base unit with each projection being related to a positioning projection provided on the intermediate base unit.

FIG. 5 is an exploded perspective view of the ball payout device 97. The configuration and operation of the ball payout device 97 will be described with reference to FIG. Ball payout device 97 in this embodiment
, A stepping motor (payout motor) 289 rotates a screw 288 to pay out pachinko balls one by one. The ball payout device 97 pays out not only premium balls based on winnings but also game balls to be lent.

As shown in FIG. 5, the ball dispensing device 97
There are two cases 198a and 198b. The ball dispensing device 9 is provided at two places on the left and right of each case 198a, 198b.
7 is provided with an engagement projection 280 that is in contact with a positioning projection provided at the upper part of the installation position. In each case 198a, 198b, a ball supply path 281a,
81b are formed. Ball supply path 281a, 281b
Has curved surfaces 282a and 282b, and has curved surfaces 282a and 282b.
Below the end of 282b, there is a ball feed horizontal path 284a, 2
84b are formed. In addition, ball feed horizontal path 284
Ball discharge passages 283a and 283b are formed at the ends of a and 284b.

The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b.
Are formed in front of partition walls 295a and 295b that partition the cases 198a and 198b forward and backward, respectively.
Further, in front of the partition walls 295a and 295b, a ball pressure buffering member 285 is sandwiched between the cases 198a and 198b. The ball pressure buffering member 285 distributes the ball supplied to the ball payout device 97 to the left and right sides and the ball supply paths 281a, 281.
81b.

Further, below the ball pressure buffering member 285, a payout motor position sensor including a light emitting element (LED) 286 and a light receiving element (not shown) is provided. Light emitting element 2
86 and the light receiving element are provided at a predetermined interval. The distal end of the screw 288 is inserted into the space. The ball pressure buffering member 28
When the cases 198a and 198b are attached to each other, the case 5 is completely stored and fixed therein.

The ball feed horizontal paths 284a and 284b have a screw 28 rotated by a payout motor 289.
8 are arranged. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 is
Fixing grooves 291a, 2 formed behind 5a, 295b
Fits into 91b. In this state, the motor shaft of the dispensing motor 289 projects forward of the partition walls 295a, 295b, so that the screw 288 is fixed forward of the projection. On the outer periphery of the screw 288, a spiral protrusion 288a for moving the game ball placed on the ball feed horizontal path 284a, 284b forward by the rotation of the payout motor 289.
Is provided.

A recess is formed at the tip of the screw 288 so as to house the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, while the screw 288 makes one rotation, the light from the light emitting element 286 is
Is detected twice by the light receiving element via the.

That is, the dispensing motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position and detecting that the dispensing operation has been performed. The wires from the light emitting element 286, the light receiving element, and the payout motor 289 are collectively pulled out to the outside through drawout holes formed below the rear portions of the cases 198a, 198b, and connected to the connector.

[0047] The game ball is a ball feeding horizontal path 284a, 284b.
When the payout motor 289 rotates in a state where the screw 288 is placed on the
The game ball moves forward on the ball feeding horizontal paths 284a and 284b. And finally, ball feed horizontal path 28
4a, 284b from the end of the ball discharge path 283a, 283b
To fall. At this time, the left and right ball feed horizontal paths 284a,
The drop from 284b is performed alternately. That is, every time the screw 288 makes a half turn, one game ball falls from one side. Therefore, every time one game ball falls, light from the light emitting element 286 is detected by the light receiving element.

As shown in FIG. 4, a ball distribution member 311 is provided below the ball payout device 97. The ball distribution member 311 is driven by the distribution solenoid 310.
For example, when the solenoid 310 is on, the ball sorting member 3
11 falls to the right, and when off, falls to the left. Below the distribution solenoid 310, a prize ball count switch 301A and a ball lending count switch 3 by a proximity switch are provided.
01B is provided. At the time of prize ball based on winning,
The ball distribution member 311 falls to the right side, and the ball discharge paths 283a, 283
The balls from 83b are both prize ball count switches 301A
Pass through. Also, at the time of lending a ball, the ball distribution member 311 falls to the left, and the balls from the ball discharge paths 283a and 283b both pass through the ball lending count switch 301B. Accordingly, the ball payout device 97 can switch the payout flow path between the time of winning a ball and the time of lending a ball, and can pay out a predetermined number of game media.

As described above, by providing the ball sorting member 311, the balls that have fallen in the two ball passages can receive the prize ball count switch 301 A and the ball lending count switch 30.
1B. Therefore,
The number of prize balls or the number of ball lending can be immediately grasped from the detection output of the prize ball counting switch 301A and the ball lending count switch 301B without determining whether the ball is a prize ball or a ball lending.

In this embodiment, a ball payout device 97 that pays out game balls by rotation of a stepping motor is used as a ball payout device that pays out game balls by driving an electric drive source. A ball payout device having a structure in which a game ball is sent out by a driving source of the above may be used, or a ball payout device having a structure in which a stopper is removed by driving an electric drive source to pay out the game ball by its own weight may be used. In this embodiment, the ball payout device 97 pays out both a prize ball based on a prize ball and a loaned ball based on a loan request, but a payout device may be provided for each.

FIG. 6 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 6 also shows a payout control board 37, a lamp control board 35, a voice control board 70, a firing control board 91, and a symbol control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12,
Starting port switch 17, V winning switch 22, count switch 23, winning port switches 19a, 19b, 24a,
24b, the full tank switch 48, the ball out switch 187, and the switch circuit 58 that supplies signals from the prize ball count switch 301A to the basic circuit 53;
A solenoid 16 for opening / closing the opening 5, a solenoid 21 for opening / closing the opening / closing plate 20, and a solenoid circuit 59 for driving a solenoid 21 A for switching a path in the special winning opening in accordance with a command from the basic circuit 53 are mounted.

Although not shown in FIG. 6, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start displaying an image on the variable display section 9, and probability fluctuation have occurred. An information output circuit 64 for outputting an information output signal such as probability change information indicating the fact to an external device such as a hall computer is mounted.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal.

A hit ball firing device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a firing control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, a reset signal whose low level indicates a reset state, a low-active return signal, and a low-active power-off signal are also input from power supply substrate 910 to main substrate 31. The reset signal and the return signal are input to the AND circuit 161 and the AND circuit 1
The output of 61 is input to the reset terminal of the CPU 56.
In addition, the power-off signal is output from the non-maskable interrupt (N
MI) terminal. Although not explicitly shown in FIG. 6, at least a part of the RAM (may be a RAM with a built-in CPU) 55 is backed up by a backup power supply created on the power supply board 910. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM 55 is stored for a predetermined period.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decorative lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. The display control of the variable display unit 9 for variably displaying special symbols and the ordinary symbol display 10 for variably displaying ordinary symbols is performed by display control means mounted on the symbol control board 80.

FIG. 7 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port unit 57. The full tank switch 48 is a switch that detects whether the excess ball tray 4 is full. In addition, the ball out switch 187 (187a, 187)
The detection signal from b) is also used for the relay board 72 and the relay board 7.
1 is input to the I / O port unit 57 of the main board 31.

The CPU 56 of the main board 31 determines whether or not the detection signal from the out-of-ball switch 187 indicates the out-of-ball state.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, a payout control command to instruct payout prohibition is transmitted. When receiving the payout control command instructing the payout prohibition, the payout control CPU 37 of the payout control board 37
1 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the relay board 72 and the I / O port section 57 of the main board 31 via the relay board 71, and the payout control is performed via the relay board 72. It is input to the input port 372b of the substrate 37. Prize ball count switch 30
1A is provided in the payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371
A payout control command is input via the / O port 372a, and the ball payout device 97 is driven in accordance with the payout control command to perform award ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a RAM.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
A ball lending number signal indicating the number of lending balls is output to the terminal board 160 via 72c. Further, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
The detection signal from the ball lending count switch 301B is input to 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid lending balls.
The drive signal from the payout control board 37 to the payout motor 289 is supplied to the payout motor 28 in the payout mechanism of the ball payout device 97 via the output port 372c and the relay board 72.
9 and the drive signal to the distribution solenoid 310 is
The distribution solenoid 310 in the dispensing mechanism of the ball dispensing device 97 via the output port 372e and the relay board 72.
Conveyed to.

The card unit 50 is equipped with a card unit control microcomputer. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37.

The payout control C of the payout control board 37
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 and pays out a predetermined number of loaned balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 sets the card unit 5
The EXS signal for 0 falls. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state,
The winning ball payout control is executed.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, a reset signal, a return signal, and a power-off signal are also input from power supply board 910 to payout control board 37. The reset signal and the return signal are input to the AND circuit 385, and the output of the AND circuit 385 is input to the reset terminal of the payout control CPU 371. The power-off signal is input to a non-maskable interrupt (NMI) terminal of the payout control CPU 371. further,
RAM (RAM with built-in CPU) existing on the payout control board 37
It may be. At least a part of the power supply board 91
0 is backed up by a backup power supply created at 0. That is, even if the power supply to the gaming machine is stopped, at least a part of the contents of the RAM is stored for a predetermined period.

In this embodiment, the case where the card unit 50 is installed separately from the gaming machine and adjacent to the gaming machine is taken as an example, but the card unit 50 is integrated with the gaming machine. You may. Also, the present invention can be applied to a case where a game ball corresponding to the amount of money is lent out according to insertion of a coin.

FIG. 8 shows the circuit configuration in the symbol control board 80 by changing the LCD (liquid crystal display) 82 as an example of the variable display section 9, the variable display 10, and the output ports (port 0, 2) It is a block diagram shown together with 570, 572 and output buffer circuits 620, 62A. Output port (output port 2) 572 outputs 8-bit data, and output port 570 outputs a 1-bit strobe signal (INT signal).

As shown in FIG. 8, the display control CPU 10
1 is supplied with a reset signal from the power supply board 910. When the reset signal is low level, the display control C
The PU 101 is in a reset state, and when the reset signal goes high, the display control CPU 101 is in an operable state.

The display control CPU 101 controls the control data R
It operates according to the program stored in the OM 102, and receives an INT signal from the main board 31 via the noise filter 107 and the input buffer circuit 105B, and receives a display control command via the input buffer circuit 105A. As the input buffer circuits 105A and 105B, for example, 74HC540 and 74HC14, which are general-purpose ICs, can be used. When the display control CPU 101 does not include an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

Then, the display control CPU 101 controls display of a screen displayed on the LCD 82 according to the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. VDP103
Reads necessary data from the character ROM 86. The VDP 103 controls the LCD 8 according to the input data.
2 to generate image data to be displayed on the LCD 2, and output R, G, B signals and a synchronization signal to the LCD 82.

FIG. 8 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, figures, or symbols displayed on the LCD 82.

The input buffer circuits 105A and 105B
Signals can be passed only in the direction from the main board 31 to the symbol control board 80. Therefore, the symbol control board 8
There is no room for a signal to be transmitted from the 0 side to the main board 31 side. That is, the input buffer circuits 105A and 105B together with the input ports constitute irreversible information input means. Even if the circuit in the symbol control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

The outputs of the output ports 570 and 572 may be directly output to the symbol control board 80, but the output buffer circuits 620 and 62A capable of transmitting signals only in one direction.
, The main board 31 to the symbol control board 8
One-way signal transmission to 0 can be more reliably performed. That is, the output buffer circuits 620 and 62A together constitute an irreversible information output unit with the output ports.

Further, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 for cutting off the high-frequency signal. The effect is eliminated. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

FIG. 9 is a block diagram showing a signal transmission / reception portion of the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and game effect lamps 28b, 28 provided outside the game area 7 are provided.
c and lighting / extinguishing of the decorative lamp 25 provided on the game board, and lighting / extinguishing of the award ball lamp 51 and the ball out lamp 52
A lamp control command indicating turning off is output from the main board 31 to the lamp control board 35. Also, the start memory display 1
8 and the lamp control command indicating the number of lighting of the gate passage memory display 41 are also transmitted from the main board 31 to the lamp control board 35.
Is output to

A reset signal is supplied from the power supply board 910 to the CPU 351 for lamp control. When the reset signal is at a low level, the lamp control CPU 351 is in a reset state, and when the reset signal is at a high level, the lamp control CPU 351 is in an operable state.

As shown in FIG. 9, the lamp control commands relating to the lamp control are output ports (output ports 0, 3) 570, 5 of the I / O port unit 57 in the basic circuit 53.
73. Output port (output port 3) 57
3 outputs 8-bit data, and output port 570 is 1
It outputs a bit INT signal. In the lamp control board 35, a control command from the main board 31 is transmitted to the CPU for lamp control via input buffer circuits 355A and 355B.
351. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

On the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a, a game effect lamp 28b, and a game effect lamp 28b defined in accordance with each control command.
8c, according to the lighting / extinguishing pattern of the decorative lamp 25,
Game effect LED 28a, game effect lamps 28b, 28
c, output a light-on / light-off signal to the decorative lamp 25; The ON / OFF signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. It should be noted that the lighting / extinguishing pattern is determined by the lamp control CPU
351 is stored in an internal ROM or an external ROM.

On the main board 31, the CPU 56
When there is an unpaid prize ball remaining number in the memory contents of M55, the control command for instructing lighting of the prize ball lamp 51 is output, and the control command is provided upstream of the payout ball passages 186a, 186b on the back of the game board. Ball switch 187a, 187b
When the game ball is no longer detected (see FIG. 3), a control command for instructing lighting of the ball out lamp 52 is output. In the lamp control board 35, each control command is transmitted to the lamp control CPU via input buffer circuits 355A and 355B.
351. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball out lamp 52 according to the control commands. The light-on / light-off pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

Further, the lamp control CPU 351 outputs a light-on / light-off signal to the start storage display 18 and the gate passage storage display 41 according to the control command.

As the input buffer circuits 355A and 355B, for example, a 74HC54 which is a general-purpose CMOS-IC
0,74HC14 is used. Input buffer circuit 35
5A and 355B are connected to the lamp control board 35 from the main board 31.
The signal can be passed only in the direction toward. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

In the main board 31, the output port 5
Buffer circuits 620 and 63A are provided outside 70 and 573. As the buffer circuits 620 and 63A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the lamp control board 70 to the main board 31 is more reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 63A.

FIG. 10 is a block diagram showing an example of the configuration of the voice control command signal transmission portion on the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing a voice output of the speaker 27 provided outside the game area 7 is output from the main board 31 to the voice control board 70 in accordance with the progress of the game.

The audio control CPU 701 includes a power supply board 9
10, a reset signal is supplied. When the reset signal is at a low level, the audio control CPU 701 is in a reset state, and when the reset signal is at a high level, the audio control CPU 701 is in an operable state.

As shown in FIG. 10, voice control commands are output from output ports (output ports 0, 4) 570, 574 of the I / O port unit 57 in the basic circuit 53. An output port (output port 4) 574 outputs 8-bit data, and an output port 570 outputs a 1-bit INT signal. In the audio control board 70, each signal from the main board 31 is input to the input buffer circuit 70.
The data is input to the voice control CPU 701 via 5A and 705B. If the audio control CPU 701 does not have an I / O port, the input buffer circuit 705A,
An I / O port is provided between the audio control CPU 701 and the audio control CPU 701.

The voice synthesizing circuit 702 using, for example, a digital signal processor is
The sound and the sound effect corresponding to the instruction 01 are generated and output to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the voice control CPU 701 to a level corresponding to the set volume and outputs the output level to the volume amplification circuit 704. The volume amplification circuit 704 outputs the amplified audio signal to the speaker 27.

As the input buffer circuits 705A and 705B, for example, 74HC54 which is a general-purpose CMOS-IC
0,74HC14 is used. Input buffer circuit 70
5A and 705B can pass signals only in the direction from the main board 31 to the voice control board 70. Therefore, there is no room for a signal to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if the circuit in the voice control board 70 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

In the main board 31, the output port 5
Buffer circuits 620 and 67A are provided outside 70 and 574. As the buffer circuits 620 and 67A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be supplied from the voice control board 70 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 67A.

FIG. 11 shows a payout control board 37 and a firing control board 9 on which a control means for controlling hit ball firing is mounted.
FIG. As shown in FIG. 11, the firing control signal is output from the output port 37 on the payout control board 37.
2d is output to the launch control board 91. In the firing control board 91, the firing control signal from the payout control board 37 is transmitted to the motor drive circuit 813 via the buffer circuit 815.
To enter.

The motor drive circuit 813 controls the drive motor 9 in each period of, for example, a ball hitting operation for firing a game ball and a recovery / ball replenishment operation in preparation for firing the next game ball.
4 to generate a voltage for controlling the rotation speed. During the ball hitting operation period, a voltage that gradually increases in accordance with the rotation operation angle with respect to the operation knob 5 is generated.
A predetermined voltage is generated.

The touch sensor circuit 93 outputs a firing permission signal to the motor drive circuit 813 while the human body is in contact with the human body detection electrode attached to the operation knob 5.
The motor drive circuit 813 is supplied with a firing control signal from the payout control board 37. Motor drive circuit 813
When the firing control signal and the firing permission signal are turned on, the switching of the sequence operation during the ball hitting operation period and the recovery / ball replenishment operation period is controlled, and the driving pattern signal and the driving voltage switching signal necessary for driving the driving motor 94 are controlled. Occurs.

FIG. 12 is a block diagram showing a DC voltage and the like supplied from the power supply substrate 910 to each substrate. As shown in FIG. 12, a power supply circuit for generating various DC voltages is mounted on a power supply board 910. If necessary, AC2
4V is also supplied to each substrate.

In this embodiment, the main substrate 31 has
C30V, DC12V, DC5V and backup power supply voltage (VBB) are supplied. The lamp control board 35 includes DC30V, DC21V, DC12V and DC5V.
V is supplied. 24V AC,
DC30V, DC12V, DC5V and backup power supply voltage (VBB) are supplied. Then, 30 V DC, 12 V DC and 5 V DC are supplied to the launch control board 91. The voice control board 70 is supplied with DC12 and DC5V. The symbol control board 80 includes DC
12V and 5V DC are supplied. Further, a reset signal is supplied from a power supply substrate 910 to each substrate.

As shown in FIG. 12, the ground side of the voltage supplied to each substrate is shared by the power supply substrate 910. Therefore, the ground level in each substrate is common. Then, a voltage level can be used as it is as a signal transmitted from one substrate to another substrate. If there is a substrate whose ground level is not shared, when transmitting signals to such a substrate, it is necessary to use a non-contact type information transmitting means such as a photocoupler, which causes an increase in cost. However, when the ground levels of all the substrates are common as in this embodiment, it is not necessary to use a photocoupler or the like.

FIG. 13 is a block diagram showing a configuration example of a power supply board 910 of a gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the symbol control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and controls each of the electric component control boards in the game machine. Generates voltages used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21
V, + 12V DC and + 5V DC. Also,
The capacitor 916 serving as a backup power supply is DC + 5
V, that is, charged from a power supply line for driving an IC or the like on each substrate.

Transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
The C converter 913 has + 21V, + 12V and + 5V.
V is generated and output to the connector 915. Connector 91
5 is connected to, for example, a relay board, from which electric power of a voltage required for each electric component control board and mechanism components is supplied.

However, the power supply board 910 may be provided with each connector leading to each electric component control board, and the power supply board 910 may supply each voltage reaching each board without passing through the relay board. Further, FIG. 13 shows one connector 915 as a representative, but the connector is provided for each electric component control board.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is provided with an electric power so as to be able to hold a storage state in a backup RAM (power-backed-up RAM, that is, storage means that can be in a storage state) when the power supply to the gaming machine is cut off. Backup power supply. Also,
A diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line.

A battery that can be charged from a + 5V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has a power monitoring I
C902 is mounted. The power supply monitoring IC 902
The occurrence of power interruption is detected by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage falls below a predetermined value (+22 V in this example),
A power-off signal is output on the assumption that power-off occurs. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The power supply cutoff signal from the power supply monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

The predetermined value for the power supply monitoring IC 902 to detect a power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electric component control board to operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed.

Further, VSL (+30 V) is used as the monitoring voltage.
Is used, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon a momentary power interruption can be expected. That is, by monitoring the voltage of the +30 V power supply, it is possible to detect a decrease in the voltage of +12 V generated after the generation of +30 V before the voltage starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output comes to the on state. However, if the + 30V power supply voltage that drops faster than + 12V is monitored and the power cutoff is recognized, the power supply is turned on before the switch output turns on. It is possible to enter a state of waiting for restoration and to enter a state where the switch output is not detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the power supply monitoring circuit can supply a power cutoff signal to the plurality of electric component control boards. No matter how many electrical component control boards need a power-off signal, it is sufficient that only one power supply monitoring means is provided. Therefore, even if each electrical component control means in each electrical component control board performs return control described later, However, the cost of gaming machines does not increase much.

In the configuration shown in FIG. 13, the detection output (power cutoff signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control signal) via the buffer circuits 918 and 919. Although transmitted to the board 37), for example, a configuration in which one detection output is transmitted to the relay board, and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates that require a power-off signal.

Further, on the power supply board 910, a reset management circuit 940 for supplying a reset signal and a return signal to each board is mounted. The reset management circuit 940 includes:
It is an example of realization of a boot order control means.

FIG. 14 is a block diagram showing a configuration example of the reset management circuit 940. In the reset management circuit 940, the reset IC 651 in the reset circuit 65
When the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. The output of the reset IC 651 is supplied to the buffer circuit 9 via the circuits 941 to 949.
61 to 964 and the delay circuit 960. The output of the delay circuit 960 is input to the buffer circuit 965. Then, the buffer circuits 961 to 965 are supplied as reset signals to the respective electric component control boards. Therefore, when the output of the reset IC 651 becomes high level, the CPU in each electric component control board becomes operable.

The reset IC 651 monitors the power supply voltage VSL, which is the same power supply voltage as the power supply voltage monitored by the power supply monitoring IC 902, and sets the voltage to a predetermined value (the power supply monitoring IC 902 outputs a power-off signal. (Lower than the voltage value). Therefore, CPU
56 and the payout control CPU 371 are power monitoring ICs.
After performing a predetermined power supply stop preparation process in response to the power-off signal from the power supply 902, the system is reset.

As shown in FIG. 14, the reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947.

The Q6 output of the counter IC 941 is:
The clock is input to a flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. NAN is input to the other input of the OR circuit 949.
The output of the D circuit 947 is introduced via a NOT circuit 948. The output of the OR circuit 949 is supplied to each CPU via the buffer circuits 961 to 965. According to such a configuration, when the power is turned on, two reset signals (low-level signals) are supplied to the reset terminal of each CPU, so that each CPU reliably starts operating.

For example, the detection voltage of the power supply monitoring IC 902 as the power supply monitoring means (the voltage at which the power supply cutoff signal is output) is set to +22 V, and the detection voltage of the reset IC 651 is set to +9 V. In such a configuration, the power supply monitoring means and the reset IC 651 monitor the voltage of the same power supply VSL. Therefore, the timing at which the power supply monitoring means outputs the power cutoff signal and the low level at which the reset IC 651 is at the reset level Can be surely set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop preparation process (the process at the time of power supply stop) in response to the power-off signal from the power supply monitoring unit until the process is reliably completed.

In this example, the detection condition that the power supply monitoring means outputs the detection signal is that the power supply voltage of +30 V is +22.
That is, the condition that the reset IC 651 outputs the low level, which is the reset level, means that the +30 V power supply voltage has dropped to +9 V. However, the voltage value used here is an example, and another value may be used.

However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the power supply monitoring means and the reset IC 651. Also in that case, the detection voltage of the power supply monitoring circuit is set higher than the detection voltage of the reset IC 651.

The CP of the main board 31 and the payout control board 37
While power is not being supplied from the + 5V power supply which is the drive power supply of the U56 and the payout control CPU 371, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board 910, and the power supply to the gaming machine is cut off. The contents are also preserved. Then, when the power is restored, the reset signal from the reset management circuit 940 becomes high level, so that the CPU 56 and the payout control C
PU 371 returns to the normal operation state. then,
Since the necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of the occurrence of the power failure upon recovery from a power failure or the like.

FIG. 14 shows a configuration in which two reset signals (low level signals) are supplied to the reset terminal of the CPU of each electric component control board when the power is turned on.
In the case of using a CPU in which reset is surely released even if the reset signal rises only once, the circuit elements indicated by reference numerals 941 to 949 are unnecessary. In that case, the output of the reset IC 651 is directly connected to the buffer circuits 961 to 964 and the delay circuit 960.

In this embodiment, the power supply board 91
When a reset signal is supplied from 0 to the CPU of each electric component control board, the delay circuit
Delay the reset signal for U56. Therefore, when the power is turned on, the reset signal to the CPU 56 of the main board 31 rises later than the reset signal to the CPUs of the other electric component control boards.

For example, when the CPU 56 of the main board 31 outputs a control command to another electric component control board,
Since the CPUs of the other electrical component control boards have already been started, the control commands are reliably received by the CPU of the electrical component control board on the receiving side.

Further, a counter 971 which is an example of timer means is mounted on the main board 910. The counter 971 counts the clock signal from the oscillator 943 when the power-off signal goes low to clear the signal. Upon counting up, a high-level one pulse is generated as the Q output. The pulse signal is logically inverted by the inverting circuit 972 and input to the buffer circuit 973 and the delay circuit 974. The delay circuit 974 delays the input signal by a predetermined period and inputs the input signal to the buffer circuit 975.

The output of the buffer circuit 973 becomes a return signal to the payout control board 37. The buffer circuit 975
Is a return signal to the main board 31. The buffer circuits 973 and 975 may be provided on the payout control board 37 and the main board 31.

FIG. 15 is a timing chart for explaining the operation of counter 971. As shown in (A), when the power supply voltage decreases and the voltage value of VSL decreases to the power-off signal output level (+22 V in this example), a power-off signal is generated. Specifically, the power-off signal goes low.
Then, as will be described later, the CPU 31 of the main board 31 and the payout control CPU 371 start execution of the power supply stop processing, and when the processing ends, the CPU 31 enters a loop state (standby state) in which no control is performed.

The counter 971 starts counting when the power-off signal goes low. The count-up value is set to VSL after the power-off signal goes low.
Is set to a time equal to or longer than the time during which the voltage value of the voltage is reduced to the voltage capable of generating Vcc. That is, the power supply voltage is set to be at least longer than the time required for the power supply voltage to decrease to a voltage at which the control operation is disabled. Since the counter 971 operates using Vcc as a power supply, the count-up value is set to a value equal to or longer than the value corresponding to the operable period of the counter 971. Therefore, in general,
Before the counter 971 counts up and the return signal is output, the counter 971 and other circuit components stop operating.

When an instantaneous interruption of the power supply or the like occurs, as shown in FIG. 15B, the power supply is restored after the voltage level of VSL is reduced for a short period of time. When the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level, and the process at the time of power supply stop is started. Then, the CPU 56 and the payout control CPU 371 enter a loop state after the end of the power supply stop processing. If no control is performed, the loop processing cannot be exited. In this case, the counter 971 counts up and a return signal is generated.

As shown in FIGS. 6 and 7, in the main board 31 and the payout control board 371, the return signal is
The signals are input to the reset terminals of the CPU 56 and the payout control CPU 371 via the AND circuits 161 and 385.
Therefore, a system reset is applied to the CPU 56 and the payout control CPU 371. As a result, the CPU 56 and the payout control CPU 371 can exit the loop state.

FIG. 15B shows a counter 971.
In this case, the return signal is output immediately after the count-up of the main circuit 31. However, as shown in FIG.
The supply timing of the return signal to the PU 56 is later than the supply timing of the return signal to the payout control CPU 371. That is, similarly to the case where the reset signal is given at the start of the normal power supply, the reset release timing of the game control means is delayed with respect to the reset release timing of the payout control means. Therefore, even when the control operation is restored by the return signal, the game control means is activated with a delay with respect to the other electric component control means.

FIG. 16 and FIG. 17 are explanatory diagrams showing the assignment of output ports of the game control means in this embodiment. As shown in FIG. 16, the output port 0 is an output port for a strobe signal (INT signal) of a control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1, and the 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2. The 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. Then, as shown in FIG. 17, 8-bit data of the voice control command transmitted to the voice control board 70 is output from the output port 4.

The output port 5 is connected to the information output circuit 6
4, various information output signals reaching the information terminal board 34 and the like, that is, output data of information related to control are output.
Drives from the output port 6 to a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the opening and closing plate 2 of the special winning opening, and a solenoid 21A for switching a path in the special winning opening. A signal is output.

FIG. 18 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 18, bits 0 to 7 of the input port 0 include a winning opening switch 24a, a winning opening switch 24b, a winning opening switch 19a, a winning opening switch 19b, a starting opening switch 17, a count switch 23, and a V switch, respectively. The detection signals of the winning switch (specific area switch) 22 and the gate switch 12 are input. Also, bits 0 to 3 of input port 1
, A detection signal of the prize ball count switch 301A, the full tank switch 48, the ball out switch 187, and a count switch short circuit signal are input.

Next, the operation of the gaming machine will be described. Figure 1
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power is turned on to the gaming machine and the CPU 56 is started, in the main processing, the CPU 56 first performs necessary initial settings.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and a stack pointer designated address is set to the stack pointer (step S3). Then, the internal device registers are initialized (step S4). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to an accessible state (step S6).

The CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). Also, CTC has two external clock / timer trigger inputs CLK / TRG2, 3
And two timer outputs ZC / TO0,1.

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Thus, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Then, it is confirmed whether or not the data protection processing of the backup RAM area (for example, the power failure occurrence NMI processing such as the addition of parity data) has been performed when the power is turned off (step S7). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. In this example, as shown in FIG. 20, if "55H" is set in the backup flag area, it means that there is a backup (on state),
If a value other than “55H” is set, it means that there is no backup (off state).

When the backup is confirmed, the CPU 5
Reference numeral 6 performs data check (parity check in this example) of the backup RAM area. If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on without power recovery is executed.

If the check result is normal (step S
8) The CPU 56 performs a game state restoring process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state at the time of power-off (step S).
9). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

In the initialization processing, the CPU 56 first sets R
An AM clear process is performed (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
An initial value setting process for setting an initial value to a payout command storage pointer or the like is also performed. Further, a process for initializing the sub-boards (the lamp control board 35, the payout control board 37, the voice control board 70, and the symbol control board 80) is executed (step S13). The process of initializing the sub board is
For example, a process of transmitting an initialization command.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S14). That is,
A value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S1 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S1).
5).

In this embodiment, the built-in C
The TC is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, when the timer interrupt occurs, as shown in FIG. 21, the CPU 56 sets, for example, a timer interrupt flag indicating that the timer interrupt has occurred (Step S).
12).

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the process proceeds to a loop process in which the main process checks whether or not a timer interrupt has occurred (step S17). In the loop, a display random number update process (step S16) is also executed.

In step S17, the CPU 56 determines
Upon recognizing that a timer interrupt has occurred, step S2
The game control processing of 1 to S31 is executed. In the game control process, the CPU 56 firstly receives, via the switch circuit 58, the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a, 19b, 24.
The states of the switches such as a and 24b are input and their states are determined (switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process for updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Next, the CPU 56 sets a display control command relating to the special symbol in a predetermined area of the RAM 55 and sends out the display control command (special symbol command control process: step S27). Further, a display control command relating to a normal symbol is set in a predetermined area of the RAM 55, and a process of transmitting the display control command is performed (ordinary symbol command control process: step S28).

Further, the CPU 56 performs an information output process of outputting data such as jackpot information, start information, and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

The CPU 56 has switches 17, 23, 19a, and 19 for detecting winning in each winning opening.
A prize ball process for setting the number of prize balls based on the detection outputs of b, 24a and 24b is executed (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the payout control command.

According to the above control, in this embodiment, the game control process is started every 2 ms.
In this embodiment, for example, in the timer interrupt processing, only a flag indicating that an interrupt has occurred is set, and the game control processing is executed in the main processing.
The game control process may be executed by a timer interrupt process.

The main process includes a process for determining whether or not to shift to the game control process. The internal timer of the CPU 56 performs a timer interrupt process based on a timer interrupt that is periodically generated. Since a flag for determining whether or not to shift is set or the like, all of the game control processing is reliably executed. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

As described above, in this embodiment, the interrupt mode 2 is set in the CPU 56 having a built-in CTC or PIO in the initial setting process. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

The output ports 0, 1, 2, 3, 4 out of the output ports 0 to 6 shown in FIGS.
Is accessed in a special symbol command control process (step S25), a normal symbol command control process (step S27), a prize ball process (step S31) and the like in the game control process. The output port 5 is accessed in information output processing (step S29), and the output port 6 is accessed in special symbol processing (step S25) and ordinary symbol processing (step S26).

Next, a method of transmitting a control command from the game control means to each electric component control means will be described. FIG. 22 is an explanatory diagram showing an example of a command form of a control command sent from the main board 31 to another electric component control board. In this embodiment, the control command has a 2-byte configuration, the first byte represents MODE (classification of command), and the second byte represents EXT (type of command). The first bit (bit 7) of MODE data is always "1", and the first bit (bit 7) of EXT data
Is always set to “0”. The command form shown in FIG. 22 is an example, and another command form may be used.

FIG. 23 is a timing chart showing the relationship between an 8-bit control signal constituting a control command from the game control board to each of the other electric component control boards and an INT signal (strobe signal). As shown in FIG.
Or, after the EXT data is output to the output port,
When the predetermined period has elapsed, the CPU 56 turns on the INT signal, which is a signal indicating data output. When a predetermined period elapses therefrom, the INT signal is turned off.

When a control command is to be output from the game control means to each electric component control board such as a payout control board, a command transmission table is set. FIG.
(A) is an explanatory view showing a configuration example of a command transmission table. One command transmission table is composed of three bytes, and INT data is set in the first byte. In the command data 1 of the second byte, MODE data of the first byte of the control command is set. And
The command data 2 in the third byte includes the control command 2
The EXT data of the byte is set.

Although the EXT data itself may be set in the command data 2 area, the command data 2
May be set to data for specifying an address of a table in which EXT data is stored. In this embodiment, bit 7 of command data 2
If (work area reference bit) is 0, it indicates that the EXT data itself is set in the command data 2. Such EXT data is data in which bit 7 is 0. If the work area reference bit is 1, the other 7
The bit indicates that it is an offset for specifying the address of the table in which the EXT data is stored.
In this embodiment, a command transmission table is prepared for each control command.

FIG. 24B is an explanatory diagram showing an example of the configuration of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is "1", it indicates that a payout control command should be sent. Therefore, the CPU 56
For example, when sending out the payout control command in the prize ball processing, “01 (H)” is set in the INT data of the command transmission table for the payout control command.

Bits 1, 2, and 3 of the INT data are bits indicating whether or not to transmit a display control command, a lamp control command, and a voice control command, respectively.
If the PU 56 is to send those commands,
INT is stored in the command transmission table indicated by the pointer.
Data, command data 1 and command data 2 are set. When sending those commands, INT
The corresponding bit of the data is set to “1”, and MODE data and E
XT data is set.

Control commands to each electric component control board are
When outputting to a corresponding output port (output ports 1 to 4), any one of bits 0 to 3 of output port 0 is turned on for a predetermined period. This corresponds to the bit arrangement at port 0. Therefore, when transmitting a control command to each electric component control board, it is possible to easily output an INT signal based on the INT data set in the command transmission table.

FIGS. 25 and 26 are flowcharts showing an example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) to a predetermined backup RAM area (step S51). Further, the interrupt flag is copied to the parity flag (step S52). The parity flag is formed in the backup RAM area. Further, the BC register, the DE register, the HL register, the IX register, and the stack pointer are saved in the backup RAM area (Steps S54 to S58).

Next, the backup specified value (in this example, “55H”) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, parity data is created (steps S60 to S67). That is, first, clear data (0
0) is set in the checksum data area (step S60), and the checksum calculation start address is set in the pointer (step S61). Further, the number of checksum calculations is set (step S62).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S63). The calculation result is stored in the checksum data area (step S6).
4) The value of the pointer is incremented by 1 (step S65), and the value of the checksum calculation count is decremented by 1 (step S6).
6). The processing of steps S63 to S66 is repeated until the value of the number of checksum calculation times becomes 0 (step S63).
67).

When the value of the number of times of checksum calculation becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S68). And
The inverted data is stored in the checksum data area (step S69). This data is the parity data that is checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S70). Thereafter, the internal RAM 55 cannot be accessed.

Further, the CPU 56 sets the clear data (0
0) is set in an appropriate register (step S71),
The number of processes ("7" in this example) is set in another register (step S72). Further, the address of the output port 0 is set in the IO pointer (step S73). Yet another register is used as the IO pointer.

Then, clear data is set at the address pointed to by the IO pointer (step S74), and
The value of the IO pointer is incremented by 1 (step S75), and the value of the number of processes is decremented by 1 (step S77). Step S7
The processes from 4 to S76 are repeated until the value of the number of processes becomes zero. As a result, clear data is set in all output ports 0 to 6 (see FIGS. 17 and 18). FIG.
As shown in FIG. 18 and FIG. 18, in this example, "1" is on, and "00", which is clear data, is set for each output port, so that all output ports are off.

Therefore, after the processing for saving the game state (in this example, generation of a checksum and prevention of RAM access) is executed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up by power. Therefore, a process of generating a checksum indicating whether or not the content is correctly stored, and an R for preventing the content from being rewritten.
The AM access prevention process corresponds to a process for saving a gaming state.

Since the output ports are immediately turned off after the processing for storing the game state is executed, it is possible to reliably prevent a situation in which the game state does not match the stored game state. When the processing shown in FIG. 25 is executed, the supply of power to the gaming machine is stopped, so that the voltage applied to the electric components decreases. Then, when the applied voltage falls below the drivable voltage, the driving of the electric component is stopped. Therefore, when the power supply to the gaming machine is stopped, the driving of the electric components is stopped although there is a short delay.

However, if the clearing process for the output port as in this embodiment is not performed, after the game state is saved, the variable prize ball device is set while the game control means waits for the power supply to stop. In some cases, a further prize may be won. In such a case, when the power supply is resumed, the saved game state is restored, so the start winning storage number at the time of saving is displayed on the start storage display 18. Then, from the player's point of view, the stored value of the start winning prize may be reduced, and a trouble may occur.
However, in this embodiment, such a trouble does not occur. Further, in the case where the power supply stop processing is executed with the control for opening the special winning opening immediately before the occurrence of the power failure or the like, the power supply stop processing is executed, and the apparatus enters a standby loop, and then returns without stopping the power supply. In the embodiment, the phenomenon that the game control is in the standby loop but the special winning opening is kept open is prevented from occurring. In addition, it is possible to prevent a phenomenon that the variable display is started during the standby loop.

[0177] Further, after the game state is saved, a prize may be generated in the big prize hole as the variable prize ball device. In such a case, the winning number recognized by the player may be different from the winning number displayed on the display unit based on the saved game state when the power supply is restored, and a trouble may occur. However, in this embodiment, such a trouble does not occur.

When the clear processing for the output port is completed, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

As described above, when a power-off signal is generated due to an instantaneous power-off or the like, the power supply voltage is restored to a normal value and the gaming machine returns to a controllable state. When such a situation occurs, a return signal is supplied from the power supply board 910 to the main board 31. When a return signal is input to the main board 31, the CPU 56 is reset. Therefore, the CPU 56 can start executing the main processing shown in FIG. At this time, since the game state is stored when the power-off signal is output, the game state restoration processing is executed in the processing of step S9, and the game control returns to the state at the time of the power-off signal generation, The game control is continued from.

In this embodiment, the power supply stop processing is executed in response to the NMI.
It may be connected to the maskable terminal of the PU 56 to execute the power supply stop processing by the maskable interrupt processing. Alternatively, the power-off signal may be input to the input port, and the power supply stop processing may be executed according to the check result of the input port.

Hereinafter, the game state restoring process will be described. FIG. 27 is a flowchart showing an example of the gaming state restoring process shown in step S9 of FIG. In this example, the CPU 56 restores the value stored in the backup RAM to each register (Step S91). Then, based on the data stored in the backup RAM, the game state at the time of the power failure is confirmed and restored. That is, based on the data stored in the backup RAM, the solenoid 16
And the solenoid 21 are driven, and the starting winning opening 14 and the opening and closing plate 2
0 is restored (steps S92 and S9).
3). In addition, according to the value of the special symbol process flag and the normal symbol process flag that have been saved even during the power-off, the control command corresponding to the progress status of the special symbol process process and the normal symbol process process at the time of power-off, The information is sent to the symbol control board 80, the lamp control board 35, and the voice control board 70 (step S94).

As described above, in the game state restoring process, the states of various electric components are restored according to the restored internal state, and the symbol control board 80, the lamp control board 35, and the voice control board 70 are restored. Then, a control command for returning the control state to the power-off state (a control command for generating the control state at the time of power-off) is transmitted.
Such a control command is generally one or more control commands that were last sent out before power down.

When the game state is restored to the state at the time of power-off, in this embodiment, the CPU 56 restores the interrupt permission / prohibition state at the time of the previous power-off to save the parity stored in the backup RAM. The value of the flag is confirmed (step S95). If the parity flag is off, interrupt permission setting is performed (step S96). However, if the parity flag is in the on state, the game state restoring process is terminated as it is (with the interrupt prohibition state set in step S1). The on state of the parity flag means that the interrupt was disabled at the time of the previous power-off, as shown in step S52 in FIG. Therefore, when the parity flag is in the ON state, the interruption is not permitted.

FIG. 28 is a flowchart showing a part of the non-maskable interrupt processing (processing at the time of stopping power supply) of the game control means according to another embodiment of the present invention. The flowchart shown in FIG. 28 corresponds to step S51 shown in FIG.
The processing is executed subsequent to the processing of S70. That is, in this embodiment, after the RAM access is prohibited (step S70), the start address of the clear data table is set in the pointer (step S78), and after the data clear processing is executed (step S78). S7
9) Enter a standby state waiting for a system reset. In addition,
A predetermined register is used as a pointer.

FIG. 29 is an explanatory diagram showing one configuration example of the clear data table. In the example shown in FIG. 29, in the clear data table, the processing number data (“7” in this example), the address of the output port 0, the clear data to be set to the output port 0,. 6, the clear data to be set in the output port 6 is set. The output port address and the clear data are set in ascending order of the output port address.

FIG. 30 is a flowchart showing the data clear processing in step S79. In the data clearing process, the CPU 56 extracts the processing number data from the address indicated by the pointer (step S81). Then, the value of the pointer is increased by 1 (step S82). Next, address data (output port address) is extracted from the address indicated by the pointer (step S83). further,
The value of the pointer is incremented by 1 (step S84).

Then, clear data is extracted from the address indicated by the pointer (step S85), and the data is
The address is set to the address extracted in step S83 (step S86). Next, the value of the number of processes is subtracted by 1 (step S
87) When the number of processes becomes 0, the data clearing process ends (step S88). If the number of processes is not 0,
It returns to step S81.

The address assignment of the output port is as follows.
If the addresses are regularly arranged, the address may be skipped one by one. Even in such a case, the next address can be easily obtained by changing the added value in the operation for obtaining the port address (step S82). . The operation is not limited to addition, but may be subtraction, integration, or the like, depending on how addresses are allocated.

Even if the clear data table is used, the clear signal output processing can be performed quickly, and the occurrence of inconsistency between the control state stored when the power supply to the gaming machine is stopped and the actual control state can be reduced. It can be effectively prevented. When the clear data table is used, the address data and the clear data do not have to be arranged in the order of addresses in the table, and the degree of freedom of the table configuration is increased.
For example, when it is desired not to clear the test signal in a gaming machine using the test signal or the like, by clearing the data relating to the output port related to the test signal from the table, the clearing process of the test signal can be easily omitted. Further, when there is an increase or decrease or a change in the output port, only the contents of the table need be changed, and there is no need to change the program.

If the clear data is 00H for all output ports, the clear data need not be included in the clear data table. In that case, FIG.
Step SS8 in the data clear processing indicated by 0
4, the processing of S85 is unnecessary, and in step S86, clear data 00 is added to the address indicated by the address data.
H is set.

As described above, since the electric component control means outputs the clear signal in the power supply stop processing, the operating state of each electric component can be made consistent with the stored game state. For example, immediately after the game state is saved, by closing the open big winning opening, closing the open variable winning ball device 15 being open, or by stopping the operation of the payout motor 289 in the driven state. It is possible to wait for power restoration in an appropriate stop state.

Even when the non-maskable interrupt processing is configured as shown in FIG. 28, when the return signal is supplied from the power supply board 910 to the main board 31, the CPU 56 is reset. The execution of the main processing shown in FIG. At this time, since the game state is stored when the power-off signal is output, the game state restoration processing is executed in the processing of step S9, and the game control returns to the state at the time of the power-off signal generation, The game control is continued from.

Next, as an example of the case where the data saving processing and the restoring processing are performed in the electric component control means other than the game control means, the case where the payout control means stores and restores the data will be described.

As shown in FIG. 7, the payout control board 37
In, a power-off signal from the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the AND circuit 385. Therefore,
The payout control CPU 371 can confirm the occurrence of power interruption by the non-maskable interrupt processing.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 incorporated in the payout control CPU 371 is counted down. When the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt occurs in response to the input of the INT signal.

FIG. 31 is an explanatory diagram showing the assignment of output ports in this embodiment. As shown in FIG. 31, the output port C (address 00H) is
The output port of the drive signal output to 89. Also,
Output port D (address 01H) is 7 segment LE
This is an output port of a display control signal output to the error display LED 374 which is D. The output port E (address 02H) is an output port for outputting a drive signal output to the distribution solenoid 310 and an EXS signal and a PRDY signal to the card unit 50.

FIG. 32 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 32, the input port A (address 06H) is an input port for receiving an 8-bit payout control signal of the payout control command sent from the main board 31. Further, detection signals of the prize ball count switch 301A, the ball lending count switch 301B, and the motor position sensor are input to bits 0 to 2 of the input port B (address 07H), respectively. In bits 3 to 5, the BRDY signal, the BRQ signal, and the VL signal from the card unit 50 are input.

FIG. 33 is a flowchart showing the main processing executed by the payout control CPU 371. When the power is supplied to the gaming machine and the payout control CPU 371 is activated, the payout control CPU 371 is executed in the main processing.
First, perform necessary initial settings. That is, the payout control CPU 371 sets interrupt prohibition (step S7).
01). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and a stack pointer designated address is set to the stack pointer (step S703). Also, the payout control CPU 371 initializes the built-in device register (step S704), and sets the CTC and P
After initializing the IO (step S705), RA
M is set to an accessible state (step S70)
6).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process in step S704 and the process in step S705, a register setting for setting a channel to be used to the timer mode, a register setting for permitting interrupt generation, and a register for setting an interrupt vector The settings are made. Then, the interruption by the channel is used as a timer interruption. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, the timer interrupt flag is set, and when it is detected in the main process that the timer interrupt flag is set, the payout control process is executed. That is, in the timer interrupt process, a setting for executing the payout control process, which is an example of the electrical component control process, is performed.

Another channel of the built-in CTC (channel 2 in this embodiment) is used as a channel for generating an interrupt for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the setting processing of the internal device register in step S704 and the processing in step S705, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the interrupt generation, and the interrupt vector setting are performed. Is set.

The interrupt vector set for the channel (channel 2) set to the counter mode corresponds to the start address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt processing is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of the channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as a specific register
The initial value “1” is set in LK / TRG2. Also, C
The interruption based on the count-up of the channel 3 (CH3) of the TC is based on the internal clock (system clock) of the CPU.
Is counted down and the register value becomes "0", and is used as a 2 ms timer interrupt described later. Specifically, the register value of CH3 is subtracted in 1/256 cycle of the system clock. Step S7
At 05, the register of CH3 contains 2 as an initial value.
A value corresponding to ms is set.

An interrupt based on the count-up of CH2 of the CTC has a higher priority than an interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process has priority.

The payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S70).
7). That is, for example, similarly to the processing of the CPU 56 of the main board 31, it is determined whether or not backup data exists by determining whether or not a backup flag that is set when the power is turned off is in a set state. If the backup flag is set, it is determined that there is backup data.

After confirming that there is a backup, the payout control CPU 371 checks the data in the backup RAM area (parity check in this example). If the power is restored after an unexpected power failure, the backup R
Since the data in the AM area should have been saved, the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on without power recovery is executed.

If the check result is normal (step S
708), the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of power-off (step S709). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area.

In the initialization process, the payout control CPU 371
Performs RAM clear processing first (step S71).
1). A CTC provided in the payout control CPU 371 so that a timer interrupt is periodically performed every 2 ms.
Are set (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S701 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S713).

In this embodiment, the payout control CPU 3
The built-in CTC 71 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2
ms. And when a timer interrupt occurs,
As shown in FIG. 34, the payout control CPU 371 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred (step S721). Note that FIG. 34 also clearly indicates that interruption is permitted (step S72).
0) In the 2 ms timer interrupt processing, the interrupt is first set to the permission state. That is, since the interrupt is permitted during the 2 ms timer interrupt process, the payout control command receiving process based on the input of the INT signal can be preferentially executed.

The payout control CPU 371 determines in step S7
At 24, when it is detected that the timer interrupt flag has been set, the payout control process from step S751 is executed. According to the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing, and the payout control processing is executed in the main processing. However, the payout control processing may be executed in the timer interrupt processing.

In the payout control process, the payout control CPU
371 is the input port 37 via the relay board 72 first.
It is determined whether or not the prize ball count switch 301A and ball lending count switch 301B input to 2b are turned on (switch processing: step S751).

Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor for detecting the number of revolutions of the payout motor 289) to determine the state of the sensor (for example). Input determination processing: Step S752). The payout control CPU 371 further analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S75).
3).

Next, the payout control CPU 371 sets the payout stop state if the payout stop instruction command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). ).
Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control to pay out the lent ball in response to the ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Further, the payout control CPU 371 performs prize ball control processing for paying out the prize balls of the number stored in the total number storage (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the winning ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism of the ball payout device 97 via the relay board 72c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of revolutions is performed (step S758). .

In this embodiment, the payout motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control processing, eight types of excitation pattern data are repeatedly output to the payout motor 289. In this embodiment, each excitation pattern data is output for 4 ms.

Next, error detection processing is performed, and a predetermined display is performed on the error display LED 374 according to the result (error processing: step S759).

Note that the output port C is accessed in the payout motor control processing (step S758) in the payout control processing. The output port D is accessed in an error process (step S759) in the payout control process.
The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

FIG. 35 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are respectively formed.
The total number storage stores the total number of awarded ball payouts instructed from the main board 31 side. The rental ball number storage stores the number of unpaid ball rentals.

As described above, since the number of unpaid prize balls and the number of loaned balls are stored in the backup RAM area capable of holding the contents for a predetermined period, even if an unexpected power failure such as a power failure occurs, If the power is restored within a predetermined period, the prize ball processing and the ball lending processing stored in the backup RAM area can be continued. Therefore, the disadvantage given to the player can be reduced.

FIGS. 36 and 37 are flowcharts showing an example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910.

In the power supply stop processing, the payout control CPU 371 stores the AF register in the predetermined backup R
Save to the AM area (step S801). Further, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. Also, BC register, DE register, HL
The registers, the IX register, and the stack pointer are saved in the backup RAM area (Steps S804 to S804)
08).

Next, the backup specified value (in this example, “55H”) is stored in the backup flag. The backup flag is formed in the backup RAM area. Next, the same processing as the processing of the CPU 56 of the main board 31 is performed to create parity data, and the backup R
The data is stored in the AM area (steps S810 to S819).
Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the internal RAM cannot be accessed.

Further, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S821), and sets the number of processes ("3" in this example) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Yet another register is used as the IO pointer.

Then, clear data is set at the address pointed to by the IO pointer (step S82).
4), increment the value of the IO pointer by 1 (step S82)
5), the value of the number of processes is subtracted by 1 (step S827).
If the value of the number of processes is 0 in the processes of steps S824 to S826,
Repeat until. As a result, clear data is set in all the output ports CE (see FIG. 25). As shown in FIG. 31, in this example, “1” is on, and “00” which is clear data is set to each output port, so that all output ports are off.

Therefore, after the processing for saving the game state (in this example, generation of the checksum and prevention of RAM access) is executed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the payout control process is stored is all backed up by a power supply. Therefore, a process of generating a checksum indicating whether or not the content is correctly stored, and an R for preventing the content from being rewritten.
The AM access prevention process corresponds to a process for saving the payout control state.

Since each output port is immediately turned off after the processing for saving the control state is executed, it is possible to reliably prevent a situation in which the game state does not match the saved game state. Generally, when the power supply to the gaming machine is stopped, although there is a short delay, the power supply to each electric component is also stopped and the operation stops. However,
If such a natural stop of operation is expected, inconvenience may occur.

For example, if the drive signal clearing process (off process) for the payout motor 289 is not performed, the game balls are paid out while the power supply voltage is decreasing to a voltage at which the payout motor 289 becomes inoperable. Sometimes. However, since the unpaid number is stored in the previous stage, if the power supply voltage is restored and the payout processing is continued based on the stored data, extra game balls will be paid out. . However, in this embodiment, the output port is cleared immediately after the payout control state is saved, so that such an inconvenience can be prevented.

That is, in this embodiment, when the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent the occurrence of control inconsistency and the like.

When the clearing process for the output port is completed, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

As described above, when a power-off signal is generated due to an instantaneous power-off or the like, the power supply voltage is restored to a normal value and the gaming machine returns to a controllable state. When such a situation occurs, a return signal is supplied from the power supply board 910 to the payout board 37. When the return signal is input,
The payout control CPU 371 is reset. Therefore,
The payout control CPU 371 can start executing the main processing shown in FIG. At this time, since the game state is stored when the power-off signal is output, the payout state restoration processing is executed in the processing of step S709,
The payout control returns to the state at the time when the power-off signal is generated, and the payout control is continued from that state.

FIG. 38 is a flowchart showing a part of the non-maskable interrupt processing (power supply stop processing) using the clear data table of the payout control means according to another embodiment of the present invention. The flowchart shown in FIG. 38 is executed following the processing of steps S801 to S820 shown in FIG. That is, in this embodiment, RA
After the M access is prohibited (step S82)
0), the start address of the clear data table is set in the pointer (step S831), and after the data clear processing is executed (step S832), the system enters a standby state waiting for a system reset. A predetermined register is used as a pointer.

FIG. 39 is an explanatory diagram showing an example of the configuration of the clear data table. In the example shown in FIG. 39, in the clear data table, the processing number data (“3” in this example) and the address of the output port C (address 00) are sequentially stored.
H), clear data to be set to output port C,
.., The address of the output port E (address 02H) and clear data to be set in the output port E are set. The output port address and the clear data are set in ascending order of the output port address. The address assignment of the output port may be skipped one by one if the address is regularly arranged. Even in such a case, the next address can be easily obtained by changing the added value. The operation is not limited to addition, but may be subtraction, integration, or the like, depending on how addresses are allocated.

FIG. 40 is a flowchart showing the data clear processing in step S832. In the data clearing process, the payout control CPU 371 extracts the processing number data from the address indicated by the pointer (step S84).
1). Then, the value of the pointer is increased by 1 (step S8).
42). Next, address data (the address of the output port) is extracted from the address indicated by the pointer (step S843). Further, the value of the pointer is increased by 1 (step S844).

Then, clear data is extracted from the address pointed by the pointer (step S845), and the data is set to the address extracted in step S843 (step S846). Next, the value of the number of processes is decremented by 1 (step S847), and when the number of processes becomes 0, the data clearing process ends (step S848). Number of processes is 0
If not, the process returns to step S841.

Even when the non-maskable interrupt processing is configured as shown in FIG. 38, when the return signal is supplied from the power supply board 910 to the payout control board 37, the payout control CPU
371 is reset, the payout control CPU 37
1 can start execution of the main process shown in FIG. At this time, since the control state is saved when the power-off signal is output, the pay-out state restoring process is executed in the process of step S709, and the pay-out control returns to the state at the time of the power-off signal generation. The payout control is continued from.

In the above embodiment, the return signal from the power supply board 910 is input to the reset terminal of the CPU 56 on the main board 31. However, the return signal may be input to the input port of the I / O port unit 57. FIG. 41 is a block diagram showing such an embodiment.

FIG. 42 is a flowchart showing a part of the non-maskable interrupt processing (processing at the time of stopping power supply) of the game control means in the case of such a configuration. The flowchart shown in FIG. 42 corresponds to steps S51 to S51 shown in FIG.
It is executed following the processing of S70. That is, in this embodiment, after the output port clearing process is executed (steps S71 to S77), in a standby state waiting for a system reset, detection of the return signal being turned on via the input port is executed (step S100). ). When the return signal is turned on, the process jumps to step S1 of the main process shown in FIG. When the execution of the main process is started, the game state is stored when the power-off signal is output, so that the game state restoration process is executed in the process of step S9, and the game control is performed when the power-off signal is generated. And the game control is continued from that state.

The return signal is input, for example, to bit 4 of input port 1 (see FIG. 18). Further, in this embodiment, the process jumps to step S1 immediately after the ON of the return signal is detected. However, in order to remove noise or the like, the process jumps to step S1 when a plurality of consecutive ONs are detected. If ON is detected again after a predetermined period has elapsed after the detection, the process may jump to step S1.

In the non-maskable interrupt processing of the payout control means, a return signal input to the input port may be detected.

In each of the above embodiments, the return signal is generated by power supply board 910, but may be generated by an electric component control board that requires the return signal. FIG. 43 is a block diagram illustrating a configuration example of the power supply board 910A when the return signal is generated in the electric component control board. FIG.
The power supply board 910A shown in FIG. 3 does not output a return signal, unlike the power supply board 910 shown in FIG.

The reset management circuit 940A may have a configuration obtained by removing the return signal generation portion from the circuit configuration shown in FIG. 14, but may be configured as shown in FIG. 44, for example. In the configuration shown in FIG.
In A, reset circuits 65, 65B, and 65C each having a reset IC that introduces VSL and changes the output from a low level to a high level when the voltage value of the VSL rises above a predetermined value are provided. . The output of the reset circuit 65 is supplied as a reset signal to the main board 31 via the reset signal circuit 950 and the buffer circuit 965. Each reset IC changes its output from a high level to a low level when the voltage of VSL falls below a predetermined value.

The output of the reset circuit 65B is supplied as a reset signal to the payout control board 37 via the reset signal circuit 950B and the buffer circuit 961.
The configuration of the reset signal circuits 950 and 950B is the same as the configuration of the reset signal circuit 950 shown in FIG. The output of the reset circuit 65C is supplied as a reset signal to the symbol control board 80, the lamp control board 35, and the audio control board 70 via the buffer circuits 962, 963, and 964.

The predetermined values required for each reset IC in the reset circuits 65, 65B, 65C to change the output level are different. Specifically, the predetermined value in the reset IC of the reset circuit 65 is the other reset I
It is larger than a predetermined value in C. Also, the reset circuit 6
The predetermined values in the reset ICs of 5B and 65C are equal or the predetermined value in the reset IC of the reset circuit 65B is larger.

Therefore, when the power is turned on and VSL rises, the output of the reset circuit 65 becomes the latest high level. That is, the CPU 56 of the main board 31 rises latest. Further, when VSL decreases when the power is turned off, the output of the reset circuit 65 becomes the low level first. That is, the CPU of the main board 31 is reset at the earliest.

The reset management circuit 940A can be configured as shown in FIG. In the configuration shown in FIG.
When the power is turned on and VSL rises, the main board 3
The reset signal for 1 becomes high level on the condition that the reset signal to another substrate becomes high level by the AND circuit 951. Therefore, the CPU 56 of the main board 31 rises later than the CPUs of the other boards. Therefore, in the case of such a configuration, the predetermined value of each reset IC in the reset circuits 65, 65B, and 65C does not need to be a value that is significantly different from the configuration shown in FIG. Good.

FIG. 46 is a flow chart showing an example of non-maskable interrupt processing (power supply stop processing) of the game control means when no return signal is generated in the power supply board 910A. The flowchart shown in FIG. 46 is executed following the processing of steps S51 to S70 shown in FIG. That is, in this embodiment, after the output port clear processing is executed (steps S71 to S77), in a standby state waiting for a system reset, first, an initial value M of the counter is set (step S111). Then, while decrementing the value of the counter by 1 (step S11)
2) Check whether the value of the counter has become 0 (step S113).

When the value of the counter becomes 0, the process jumps to step S1 of the main processing shown in FIG. When the execution of the main process is started, the game state is stored when the power-off signal is output, so that the game state restoration process is executed in the process of step S9, and the game control is performed when the power-off signal is generated. And the game control is continued from that state.

The time from when the counter is set to the initial value M until it counts up (becomes 0) is [the time required for the processing of steps S112 and S113] × M. It is set to count a time longer than the time from when the disconnection signal is generated until the CPU 56 operating on the Vcc power supply becomes inoperable. Therefore, generally, the CPU 56 does not operate before the counter counts up and jumps to step S1. That is, there is no jump to step S1.

However, when an instantaneous interruption of the power supply occurs, the power supply voltage is restored after a short period of time. Also in this case, when the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level, and the power supply stop processing is started. Then, the CPU 56 enters a loop state after the power supply stop processing ends. If no control is performed, the loop process cannot be exited. In this case, the counter counts up and the process can return to the main process.

That is, the counter in this embodiment corresponds to a software timer for performing a timer process executed in a standby state in a process corresponding to a power-off signal. Then, when the counter counts up, that is, when the elapse of the predetermined period is measured by the timer processing, the CPU 56 as the return means performs control to return from the standby state to the game control state.

Even in such a configuration, when the power supply voltage is restored to a normal value despite the occurrence of a power supply cutoff signal due to a momentary power supply interruption or the like, the CPU 56 returns to the state shown in FIG. The execution of the main processing can be resumed. At this time, since the game state is stored when the power-off signal is output, the game state restoration processing is executed in the processing of step S9, and the game control returns to the state at the time of the power-off signal generation, The game control is continued from.

Such control can be executed by the payout control means. FIG. 47 is a flowchart illustrating an example of the non-maskable interrupt process (process at the time of power supply stop) of the payout control unit when the return signal is not generated in the power supply board 910A. The flowchart shown in FIG.
It is executed following the processing of steps S801 to S820 shown in FIG. That is, in this embodiment, after the output port clear processing is executed (step S821).
-S827), in a standby state waiting for a system reset, first, an initial value M of the counter is set (step S831). Then, while subtracting 1 from the counter value (step S832), it is checked whether the counter value has become 0 (step S833).

When the value of the counter becomes 0, the process jumps to step S701 of the main process shown in FIG. When the execution of the main processing is started, the control state is saved when the power-off signal is output, so that the payout state restoration processing is executed in the processing of step S709,
The control returns to the state at the time of occurrence of the power-off signal, and the payout control is continued from that state.

The count-up value handled by the CPU 56 of the main board 31 (M set in S111 in FIG. 46) is preferably a value larger than the count-up value handled by the payout control CPU 371. If the count-up value handled by the CPU 56 is a larger value,
The payout control means is restarted before the game control means. Therefore, the payout control means does not start up first and does not miss the payout control command from the game control means.

As described above, when the return signal is not generated in the power supply board 910A, it is possible to return from the standby state to the control state by performing the timer processing by software, but the timer processing may be executed by hardware. Good.

FIG. 48 is a block diagram showing an example of a configuration in which timer processing is performed by hardware when a return signal is not generated in power supply board 910A.
In this example, a counter (watchdog timer circuit) 16 functioning as a watchdog timer is provided on the main board 31.
2 are provided. The watchdog timer circuit 162
When the output pulse of the oscillation circuit 164 is counted and counted up, one high-level pulse is generated as the Q output. The pulse signal is logically inverted by the inversion circuit 163 and input to the AND circuit 161 as a return signal. A
The ND circuit 161 calculates the logical product of the reset signal and the return signal and supplies the logical product to the reset terminal of the CPU 56. Note that C
A system clock or a frequency-divided clock thereof may be set to be output from the PU 56, and the clock may be used as an input clock signal of the watchdog timer circuit 162.

The count-up value is set to a time equal to or longer than the time when the voltage value of VSL decreases to the voltage at which Vcc can be generated after the power-off signal goes low. Since the watchdog timer circuit 162 operates using Vcc as a power supply, the count-up value is set to a value equal to or longer than the value corresponding to the operable period of the watchdog timer circuit 162. Therefore, when the power supply to the gaming machine is stopped, generally, the watchdog timer circuit 162 and other circuit components do not operate before the watchdog timer circuit 162 counts up and the return signal is output.

When the CPU 56 is performing game control, a clear pulse is periodically given to the watchdog timer circuit 162. The output cycle of the clear pulse is shorter than the time until the watchdog timer circuit 162 counts up. Therefore, no pulse appears on the Q output of the watchdog timer circuit 162 when the CPU 56 performs the normal game control.

FIG. 49 shows the structure of the watchdog timer circuit 16.
It is a flow chart which shows a part of main processing of game control means when 2 is provided. The processing illustrated in FIG. 49 is performed subsequent to the processing in steps S1 to S15 illustrated in FIG. In this case, a watchdog timer clearing process (step S32) is executed in a loop of the game control process (steps S16 to S32). Therefore, the watchdog timer clear processing is executed every 2 ms.

In the watchdog timer clearing process (step S32), a process of outputting one pulse to an output port reaching the clear terminal of the watchdog timer circuit 162 is performed. Therefore, during execution of the game control process, a clear pulse is periodically given to the watchdog timer circuit 162, so that the watchdog timer circuit 162 does not count up.

When the supply voltage to the gaming machine decreases and a power-off signal is output, the non-maskable interrupt processing as shown in FIGS. 25 and 26 is started. During this process, no clear pulse is output to the watchdog timer circuit 162. Therefore, when the power supply voltage is restored and the watchdog timer circuit 162 operates until counting up, a return signal is output.

FIG. 50 is a timing chart showing the output timing and the like of the return signal when the above-mentioned software timer processing or the watchdog timer circuit 162 generates the return signal. (A) is an example in the case where the power supply to the gaming machine is stopped. The software timer processing is started after the power supply stop processing ends and the processing enters a standby state. Also, in the non-maskable interrupt processing, a clear pulse is not output to the watchdog timer circuit 162, so that the watchdog timer circuit 16 is started substantially from the start of the power supply stop processing.
In any case, the time-up value (count-up value) is set so as not to time-up until the power supply voltage becomes lower than the voltage value capable of generating Vcc.
No return signal is generated.

When an instantaneous interruption of the power supply or the like occurs, as shown in FIG. 50B, the power supply is restored after the voltage level of VSL decreases for a short period. Also in this case, when the voltage level of VSL becomes equal to or lower than the power-off signal output level, the power-off signal becomes low level, and the power supply stop processing is started. And CP
U56 enters a loop state after the end of the power supply stop processing.
If no control is performed, the loop processing cannot be exited. In this case, the watchdog timer circuit 16 counts up and generates a return signal.

As shown in FIG. 48, on the main board 31, the return signal is transmitted to the CPU via the AND circuit 161.
It is input to 56 reset terminals. Therefore, the CPU 56
Requires a system reset. As a result, the CPU 56
Can get out of the standby state.

FIG. 51 is a block diagram showing an example of a configuration in which timer processing is performed by hardware in the dispensing control board 37 when a return signal is not generated in the power supply board 910A. In this example, the payout control board 3
7, a counter (watchdog timer circuit) 386 that functions as a watchdog timer is provided. The watchdog timer circuit 386 counts output pulses of the oscillation circuit 388, and when counting up, generates one high-level pulse as a Q output. The pulse signal is logically inverted by the inverting circuit 387 and input to the AND circuit 385 as a return signal. AND circuit 385
The logical product of the reset signal and the return signal is calculated and supplied to the reset terminal of the CPU 56.

The count-up value is set to a time equal to or longer than the time when the voltage value of VSL decreases to the voltage at which Vcc can be generated after the power-off signal goes low. Since the watchdog timer circuit 386 operates using Vcc as a power supply, the count-up value is set to a value equal to or longer than the value corresponding to the operable period of the watchdog timer circuit 386. Therefore, generally, before the watchdog timer circuit 386 counts up and the return signal is output, the watchdog timer circuit 386 and other circuit components do not operate. Note that when the payout control CPU 371 is performing payout control, a clear pulse is periodically provided to the watchdog timer circuit 386. The output cycle of the clear pulse is shorter than the time until the watchdog timer circuit 386 counts up. Therefore, the payout control CP
When U 371 is performing normal game control, no pulse appears on the Q output of watchdog timer circuit 3876.

FIG. 52 shows a watchdog timer circuit 38.
6 is a flowchart showing a part of a main process of a payout control unit when the number 6 is provided. The processing illustrated in FIG. 52 is executed subsequent to the processing in steps S701 to S713 illustrated in FIG. In this case, the watchdog timer clearing process (step S760) is executed in the loop of the payout control process (steps S724 to S760). Therefore, the watchdog timer clear processing is performed by 2
Executed every ms.

In the watchdog timer clearing process (step S760), a process of outputting one pulse to an output port reaching the clear terminal of the watchdog timer circuit 386 is performed. Therefore, during the execution of the payout control process, a clear pulse is periodically given to the watchdog timer circuit 386, so that the watchdog timer circuit 386 does not count up.

When the supply voltage to the gaming machine is reduced and a power-off signal is output, a non-maskable interrupt process as shown in FIGS. 36 and 37 is started. During this process, no clear pulse is output to the watchdog timer circuit 386. Therefore, in the case where the power supply voltage is restored and the watchdog timer circuit 386 operates until counting up, a return signal is output.

As shown in FIG. 51, the payout control board 3
At 7, the return signal is output via the AND circuit 385,
It is input to the reset terminal of the payout control CPU 371.
Therefore, a system reset is applied to the payout control CPU 371. As a result, the payout control CPU 371 can escape from the standby state.

As described above, the watchdog timer circuits 162, 3 are provided in the main board 31 and the payout control board 37.
In the case where 86 is provided, the return signal can be generated by hardware. In addition, not only when the power supply voltage drops, but also for some reason, the CPU 5
6 or when the control of the payout control CPU 371 enters an infinite loop, it is possible to get out of the loop state.

The count-up value of the watchdog timer circuit 162 of the main board 31 is preferably larger than the count-up value of the watchdog timer circuit 386 of the payout control board 37. When the count-up value of the watchdog timer circuit 162 is larger, the return signal is supplied to the payout control unit before the game control unit. Therefore, the payout control means does not start up first and does not miss the payout control command from the game control means.

For example, a watchdog timer circuit 162 may be provided only on the main board 31 to supply a return signal from the watchdog timer circuit 162 to the CPU 56 and also to the payout control board 37. With such a configuration, the overall circuit configuration scale can be reduced. In such a configuration, it is preferable to provide a delay circuit between the watchdog timer circuit 162 and the reset terminal of the CPU 56 so that the payout control means starts up first.

Furthermore, the watchdog timer circuit 16
The return signal according to 2,386 may be input to an input port instead of being connected to the reset terminal of the CPU. In this case, the input port is monitored in the standby state in the power supply stop process, and when it is detected that the return signal is turned on, the process jumps to the beginning of the main process. Furthermore, watchdog timer circuits 162, 386
May be input to the CTC terminal of the CPU. In that case, the CTC interrupt is set in advance in response to the input of the return signal. In the standby state, interrupt permission is set. Then, when a CTC interrupt occurs, the process jumps to the beginning of the main process.

In each of the above-described embodiments, the power supply stop processing is executed in the payout control board 37 in accordance with the NMI.
And the power supply stop processing may be executed by the maskable interrupt processing. Alternatively, the power-off signal may be input to the input port, and the power supply stop processing may be executed according to the check result of the input port.

As described above, in each of the above embodiments,
When the game control means and the payout control means having the memory holding means (for example, a backup RAM) perform the power supply stop processing in response to the power-off signal and are in a standby state of waiting for a system reset, return in response to power recovery. When the signal is output, the game control means and the payout control means resume the operation from the beginning of the program. Alternatively, when a timeout occurs in the timer processing by software, the game control means and the payout control means resume the operation from the beginning of the program. At that time, the control state saved in the power supply stop time process is restored, so that the game is continued as if nothing had happened to the player.

[0279] Further, the starting sequence control means provided on the power supply board includes all the electric components including the electric component control means having no memory holding means and the electric component control means having the memory holding means. Since the activation sequence is controlled by controlling the supply sequence of the reset signal for the control unit, the activation sequence control of all the electric component control units can be realized with a simple configuration. In each of the above embodiments, the electric component control means having no memory holding means are the display control means, the lamp control means and the voice control means, and the electric component control means having the memory holding means. The game control means and the payout control means.

Furthermore, since the activation order control means activates the game control means last, there is no inconvenience that each electric component control means misses a control command from the game control means.

In the pachinko gaming machine 1 according to each of the above-described embodiments, when the stop symbol of the special symbol variably displayed on the variable display section 9 based on the winning start is a predetermined symbol combination, the predetermined game value is reduced. Although it was a first-class pachinko gaming machine that can be given to a player, a predetermined game value that can be given to a player when there is a prize in a predetermined area of an electric accessory that is opened based on a start winning prize. Two types of pachinko machines,
A third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize in a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a start winning combination is a predetermined symbol. Even so, the present invention can be applied.

The present invention is not limited to pachinko gaming machines, but may be applied to slot machines and the like in the case where electric parts for performing certain operations are provided.

FIG. 53 is a block diagram showing another configuration example of the power supply board. The power supply board 910B shown in FIG.
A switch 990 is mounted. As shown in FIG. 54, the reset management circuit 940B is equipped with a counter 991 which clears when the output of the IC 949 (original reset signal) becomes high level and starts counting. When the counter 991 counts up,
Outputs one low-level pulse. Also, the counter 99
The output of 1 is input to the AND circuit 992. In the AND circuit 992, the switch 990 is turned on (low level).
, The low level from the counter 99 can be passed.

FIG. 55 is a timing chart for explaining the operation of switch 990 and counter 991. When the reset signal (output of the IC 949) rises to a high level when the power of the gaming machine is turned on, the counter 991 starts counting. Then, when counting up, one low-level pulse is output. Therefore, switch 99
When 0 is in the ON state (low level), a low level appears at the output of the AND circuit 993 which takes the logical product of the output of the IC 949 and the output of the AND circuit 992. Therefore, a low level appears again in the reset signal reaching each electric component control board. As described above, when the power is turned on, the IC
Two low levels appear at the output of 949.

Therefore, in particular, in the game control board 31 and the payout control board 37, the CPU 56 and the payout control CPU 371 are reset again by the output of the counter 991. If the control state is saved before the power is turned on, the power-on reset (IC949)
Depending on the output of ) Is released, the control state is restored. Accordingly, at that time, the storage of the control state is released. Therefore, when the reset by the counter 991 is applied, the game state restoration processing or the payout state restoration processing is not executed in the main processing shown in FIGS. 19 and 33, and the RAM clear processing (steps S11 and S71).
1) is executed. That is, the contents of the RAM are initialized.

In this example, the reset level by the counter 991 is supplied to each electric component control board.
The output of the counter 991 is ORed with the return signal (logical OR of low level, that is, logical AND).
Only the game control unit and the payout control unit having the control state saving function may be reset.

In the case where the power supply board 910B is configured as described above, if the game machine is turned on while pressing the switch 990, a low-level reset signal based on the output of the IC 949 is output. Counter 99
After a lapse of the time created by No. 1, a low-level reset signal is generated again, and the RAM can be cleared.
Therefore, when it is desired to clear the control state stored in the backup RAM, the power of the gaming machine may be turned on while pressing the switch 990.

In the circuit configuration shown in FIG. 54,
When the switch 990 continues to be pressed, the AND circuit 9
Since a low level appears at the output of the counter 921, the counter 991
It is preferable that the operation of the counter 991 be stopped after the low level pulse is output once. Also, the circuit configuration shown in FIG.
Any configuration may be used as long as a low-level reset signal based on the output of the IC 949 can be output and a low-level reset signal can be generated again based on the depression of 0.

Further, here, a case has been described in which the RAM is cleared when the power is turned on to the gaming machine while the switch 990 is pressed. However, the RAM is cleared when the switch 990 is pressed regardless of the power-on. You may comprise so that it may be.

[0290]

As described above, according to the present invention, in the gaming machine, the electric component control means detects that the state of the predetermined power supply has reached the predetermined state by the power supply monitoring means. In this case, the power supply is stopped after performing the power supply stop processing related to the storage of the control state, and the power supply is stopped after a predetermined period elapses after the power supply monitoring unit detects that the power supply monitoring unit has reached the predetermined state. Since the return signal output means for outputting a return signal for returning from the standby state to the electric component control means when not in the standby state is provided, the electric component control means is returned to the control execution state by the return signal. As a result, it is possible to obtain an effect that even if an instantaneous interruption of the power supply, which is restored in a very short time, does not hinder the control.

When the return signal is configured to be input to the reset signal input section of the electric component control means,
The configuration for returning the electric component control means to the control execution state can be simplified.

When the return signal output means is configured to include a timer means capable of measuring a predetermined period, the structure for generating the return signal can be simplified.

When the power supply to the gaming machine is cut off for a predetermined period of time, the power supply monitoring unit detects that the state of the predetermined power supply has reached a predetermined state, and then the electric component control unit starts the operation. If the time is equal to or longer than the time until the operation becomes inoperable, it is possible to prevent the electric component control unit from returning to the control execution state by mistake.

When the return signal output means is configured to output a return signal to the payout control means prior to the game control means, when returning to the control execution state, Since the player rises first, there is no possibility that the control signal from the game control means is dropped.

If the return signal output means is configured to be mounted on the power supply board, the return signal can be supplied to a plurality of electric component control means, so that the cost of the gaming machine does not increase. Further, since the return signal is supplied from one substrate to each electric component control means, it is easy to divert it to another model.

In the case where the power supply board is configured so that the start-up sequence control means for controlling the start-up order of the electric component control means is mounted, the start-up order of each electric component control means must be managed in a unified manner. Therefore, the order of activation can be easily realized.

When the activation sequence control means is configured to control the activation sequence by controlling the output sequence of the reset signal to each electric component control means, the activation sequence of each electric component control means is determined. Can be easily realized.

In the case where the starting sequence control means is configured to start the game control means last, the electric component control means which receives a control signal from the game control means at the time of starting up the game control means has a higher priority. , The control signal from the game control means is not dropped.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an explanatory view showing each substrate provided on the back surface of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanical panel of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a front view showing a configuration around an intermediate base unit installed on a mechanism plate.

FIG. 5 is an exploded perspective view showing a ball payout device.

FIG. 6 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 7 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball payout device.

FIG. 8 is a block diagram illustrating a circuit configuration example of a symbol control board.

FIG. 9 is a block diagram illustrating a circuit configuration example of a lamp control board.

FIG. 10 is a block diagram illustrating a circuit configuration example of an audio control board.

FIG. 11 is a block diagram illustrating a circuit configuration example of a launch control board.

FIG. 12 is a block diagram showing a DC voltage and the like supplied to each substrate from a power supply substrate.

FIG. 13 is a block diagram illustrating a configuration example of a power supply board.

FIG. 14 is a block diagram illustrating a configuration example of a reset management circuit.

FIG. 15 is a timing chart for explaining the operation of a counter which is an example of the timer means.

FIG. 16 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 17 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 18 is an explanatory diagram showing an example of bit assignment of an input port.

FIG. 19 is a flowchart illustrating a main process executed by a CPU on a main board.

FIG. 20 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state restoration process.

FIG. 21 is a flowchart showing a 2 ms timer interrupt process.

FIG. 22 is an explanatory diagram illustrating an example of a command form of a control command.

FIG. 23 is a timing chart showing the relationship between an 8-bit control signal constituting a control command and an INT signal.

FIG. 24 is an explanatory diagram showing a configuration example of a command transmission table.

FIG. 25 is a flowchart showing a power supply stop process in the game control means.

FIG. 26 is a flowchart showing a power supply stop process in the game control means.

FIG. 27 is a flowchart illustrating an example of a game state restoration process.

FIG. 28 is a flowchart showing another example of the power supply stop processing in the game control means.

FIG. 29 is an explanatory diagram showing a configuration example of a clear data table.

FIG. 30 is a flowchart showing data clear processing.

FIG. 31 is an explanatory diagram showing an example of bit assignment of an output port on a payout control board.

FIG. 32 is an explanatory diagram showing an example of bit assignment of an input port on a payout control board.

FIG. 33 is a flowchart showing a main process executed by a CPU in the payout control board.

FIG. 34 is a flowchart showing a 2 ms timer interrupt process.

FIG. 35 is an explanatory diagram showing one configuration example of a RAM in the payout control means.

FIG. 36 is a flowchart showing processing at the time of stopping power supply in the payout control means.

FIG. 37 is a flowchart showing processing at the time of stopping power supply in the payout control means.

FIG. 38 is a flowchart showing another example of the power supply stop processing in the payout control means.

FIG. 39 is an explanatory diagram showing a configuration example of a clear data table.

FIG. 40 is a flowchart showing data clear processing.

FIG. 41 is a block diagram showing another circuit configuration of the game control board.

FIG. 42 is a flowchart showing another example of the power supply stop processing in the game control means.

FIG. 43 is a block diagram showing another configuration example of the power supply board.

FIG. 44 is a block diagram illustrating another configuration example of the reset management circuit.

FIG. 45 is a block diagram showing yet another configuration example of the reset management circuit.

FIG. 46 is a flowchart showing another example of the power supply stop processing in the game control means.

FIG. 47 is a flowchart showing another example of the power supply stop processing in the payout control means.

FIG. 48 is a block diagram showing a part of another configuration example of the game control means.

FIG. 49 is a flowchart illustrating another example of the main processing executed by the CPU on the main board.

FIG. 50 is a timing chart for explaining the operation of the software timer and the watchdog timer circuit.

FIG. 51 is a block diagram illustrating a part of another configuration example of the payout control unit.

FIG. 52 is a flowchart showing another example of the main processing executed by the CPU in the payout control board.

FIG. 53 is a block diagram showing another configuration example of the power supply board.

FIG. 54 is a block diagram illustrating another configuration example of the reset management circuit;

FIG. 55 is a timing chart for explaining the operation of the switch on the power supply board.

[Explanation of symbols]

 31 game control board (main board) 37 payout control board 54 ROM 55 RAM 56 CPU 57 I / O port 162 watchdog timer circuit 371 payout control CPU 385 watchdog timer circuit 910, 910A, 910B power supply board 940, 940A, 940B Reset management circuit 971 counter (timer means)

Claims (9)

[Claims] 1. A gaming machine in which a player can play a predetermined game, an electric component control means for controlling an electric component provided in the gaming machine, and a power supply to the gaming machine is stopped. Storage means capable of holding the storage contents of the electric component control means, and power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine, wherein the electric component control means comprises: When it is detected that the state of the predetermined power supply has reached a predetermined state, a standby state is performed after performing a power supply stoppage process related to storage of a control state, and the power supply monitoring unit And outputting a return signal for returning from the standby state to the electric component control means when the power supply has not been stopped after a predetermined period has elapsed after the predetermined state has been detected. Game machine characterized by comprising a potential reversion signal output means. 2. The gaming machine according to claim 1, wherein the return signal is input to a reset signal input section of the electric component control means. 3. The gaming machine according to claim 1, wherein the return signal output means includes timer means capable of measuring a predetermined period. 4. During a predetermined period, when the power supply to the gaming machine is cut off, the power supply monitoring means detects that the state of the predetermined power supply has reached a predetermined state, and thereafter the electric component is stopped. The gaming machine according to claim 1, wherein the time is equal to or longer than a time required for the control unit to become inoperable. 5. 5. The electric component control means includes a game control means for controlling the progress of a game and a payout control means for controlling a payout of a game medium, wherein the return signal output means is provided before the game control means. The gaming machine according to claim 1, wherein a return signal is output to the payout control means. 6. A power supply board for generating a voltage used in each electric component control board, separately from the electric component control board on which the electric component control means is mounted, and the return signal output means is mounted on the power supply board. The gaming machine according to claim 1, wherein 7. An electric component control unit includes a memory holding unit and a non-memory unit, and a power supply board is provided with a starting sequence control unit for controlling a starting sequence of the electric component control units. The gaming machine according to claim 6. 8. The gaming machine according to claim 7, wherein the starting order control means controls the starting order by controlling the output order of the reset signal to each electric component control means. 9. An electric component control unit comprising: a game control unit for controlling the progress of a game; and another electric component control unit for controlling an electric component in accordance with a control signal from the game control unit. 9. The gaming machine according to claim 7, wherein the control means activates the game control means last.