JP2002052216A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To preserve an appropriate game state by appropriately setting the operating state of electrical components at the time of unexpected power supply cutting or the like and improve the convenience in using a game machine in a game shop. SOLUTION: A game control means performs a predetermined process at the time of power supply stoppage when power supply to a game machine stops. In this process at the time of power supply stoppage, the game control means performs an output port clear process which clears data outputted to a plurality of output ports for outputting predetermined data. Therefore, the driving of a variable prize ball device or the like is stopped and an appropriate backup storage can be conducted. In addition, because the game machine has a clear switch, the contents of the backup storage may be cleared when the game reopening by the backup storage is inappropriate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As an example of a gaming machine, when a game medium such as a game ball is fired into a game area by a launching device, and a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of game media are played. Some prize balls are paid out to players. Further, a variable display unit whose display state can be changed is provided, and when a display result of the variable display unit becomes a predetermined specific display mode, a predetermined game value is provided to the player. There is.

[0003] The game value means that the state of the variable winning ball device provided in the game area of the gaming machine is in a state that is advantageous for a player who is likely to win a hit ball, or is in a state that is advantageous for the player. In other words, the right is to be generated, or the condition for paying out premium game media is easily established.

In a first-type pachinko gaming machine having a variable display section for displaying a special symbol, it is generally known that the display result of the variable display section for displaying a special symbol is a combination of predetermined specific display modes. , "Big hit". When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. And
In each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Also,
If a predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time of closing the special winning opening, the big hit gaming state ends.

[0005] Further, among the combinations of display modes other than the combination of "big hits", when a part of the display results of the plurality of variable display portions is not yet derived and displayed, it is already definite or temporary. A state in which the display mode of the variable display unit on which the various display results are derived and displayed satisfies the display condition that is a combination of the specific display modes is called “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of "big hit", the result is "missing" and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

When a game ball wins a winning opening provided on the game board, a predetermined number of award balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means,
Sent to the payout control board. In the following, since the game control means and other control means control various electric components provided in the gaming machine, they may be referred to as electric component control means.

[0007]

As described above, a gaming machine is equipped with various electric component control means including game control means. Generally, each electric component control means is configured to include a microcomputer. Such an electric component control means generally performs an initialization process when a power supply voltage rises, and starts control from an initial state. Then, an unexpected power interruption such as a power failure occurs, and thereafter, when the power is restored, the state returns to the initial state, so that a problem such as a loss of the game value obtained by the player may occur. In order to prevent such a problem from occurring, the game control is interrupted in response to a predetermined signal generated with a decrease in the power supply voltage value, and the game state at that time is changed to a power supply stop to the game machine. Above all, it may be stored in a storage unit (backup storage unit) that is backed up by a power supply, and may be controlled so as to wait until the power supply is completely stopped. Such a gaming machine restarts the game based on the stored game state if power supply is resumed in a state where the game state is stored in the storage means, and therefore, a disadvantage is given to the player. Is prevented.

However, if the electric component is operating immediately before the process of storing the game state in the backup storage means and waiting for the power supply to stop, the control of the electric component control means is continued until the power supply is stopped. Will give a signal indicating the operating state to the electrical component. Then, a situation may occur in which the game is continued even though the game state to be restored when the power supply is restarted is saved. For example, when the starting winning opening that is a condition for starting the variable display in the variable display unit is a variable winning ball device driven by a solenoid or the like, the stored value of the winning ball in the variable winning ball device is stored. Nevertheless, while the game control means is waiting for the power supply to stop, the variable prize ball device as the starting prize hole may further win. In such a case, when the power supply is resumed, the saved game state is restored, so from the viewpoint of the player,
It seems that the memorized value of the start winning prize has decreased, and a trouble may occur.

Further, even if the stored game state is proper, if a control for restarting the game is performed based on the stored game state, the gaming machine is installed. The convenience of a game store may be impaired. For example, when a power failure occurs and the game cannot be continued, when there is a player who has given up continuing the game without waiting for the restart of the game, another player can start the game from a state in the middle of the game Therefore, it is not preferable to restore the gaming state to the state before the power failure.

In view of the above, the present invention can save the appropriate gaming state by appropriately setting the operation state of the electric component at the time of unexpected power-off and the like, as well as the convenience of operating the gaming machine in the amusement store. It is an object of the present invention to provide a gaming machine capable of improving the game quality.

[0011]

A gaming machine according to the present invention comprises:
A gaming machine in which a player can play a predetermined game, wherein the electronic component controlling microcomputer for controlling an electrical component provided in the gaming machine and the electronic component controlling microcomputer generate when the electronic component controlling microcomputer performs control. Data storage means (for example, RAM) for storing the fluctuation data to be changed, and the final storage contents of the fluctuation data storage means immediately before the power supply is stopped even if the power supply to the gaming machine is stopped (the power supply is stopped). Will be remembered if the game is interrupted by
Storage content holding means capable of holding the contents of the final control state immediately before the stop of power supply), and an initialization operation capable of initializing the fluctuation data stored in the fluctuation data storage means Means (for example, a clear switch 921) and an output port through which the electric component control microcomputer outputs predetermined data, wherein the electric component control microcomputer performs a predetermined operation when power supply to the gaming machine is stopped. Power supply stop processing can be performed, and in the power supply stop processing, output port clear processing for clearing data output to an output port is performed.

The electric component control microcomputer, when confirming that the initialization operation means is in a predetermined operation state at the time of restarting power supply, can initialize the final storage contents of the variation data storage means. preferable.

An input port is provided for the electrical component control microcomputer to acquire predetermined data, and an initialization signal (for example, a clear switch signal) output when the initialization operation means is in a predetermined operation state ) Is preferably input to the input port.

The electric component control microcomputer is a payout control microcomputer for controlling a payout means for paying out a game medium.
It is preferable that the driving of the payout means (for example, the ball payout device 97) is stopped.

The electric component control microcomputer is a game control microcomputer for controlling a variable winning ball device (for example, the variable winning ball device 15, a large winning opening, etc.), and drives the variable winning ball device by an output port clearing process. Preferably stop.

A game medium detecting means for detecting a game medium, and a power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine. It is preferable to execute a process of inputting a detection signal from the game medium detecting means for a predetermined period when it is detected that the game media has reached a predetermined state.

The game medium detecting means preferably includes payout detecting means for detecting the game medium paid out by the payout means for paying out the game medium.

The electric component control microcomputer executes a process of inputting a detection signal from the game medium detection means when the power supply monitoring means detects that the state of the power supply has reached a predetermined state. The output port clearing process may be performed before.

The initialization request detection determination period for determining whether or not the initialization operation means is in a predetermined operation state is a game medium detection determination period for determining whether game media is detected by the game medium detection means. May be different periods. For example, during the initialization request detection determination period, the CPU 5
6 is determined to be ON if it is turned on at the confirmation time when the confirmation switch signal is input only once to determine whether or not there is a clear switch signal input. During the game medium detection determination period, the switch-on determination value ( For example, it is 0.002 seconds determined by “2”). Therefore, the signal of the game medium detecting means is at least about 0.0
The signal of the initialization operation means is turned on when it is determined to be on during one determination time, whereas it is determined to be on when the on determination is performed twice consecutively at the determination time of the 02 second interval. Is determined.

It is preferable that the electric component control microcomputer executes a process of prohibiting access to the variable data storage means in the process at the time of power supply stop.

[0021]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as viewed from the front. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine or a slot machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing game balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section (special symbol display device) 9 for variably displaying a plurality of types of symbols and an ordinary symbol display (ordinary symbol display device) 10 using 7-segment LEDs are provided. A variable display device 8 is provided. In the variable display section 9, for example, "left", "middle",
There are three symbol display areas of "right". Variable display device 8
Is provided with a passage gate 11 for guiding a hit ball. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6 and detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. A winning ball that has entered one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V winning switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, the number of winning balls entering the starting winning opening 14 is displayed.
A start winning storage display 18 having a plurality of display units is provided. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the respective winning ports 19 and 24 is determined by correspondingly provided winning port switches 19a and 19a.
19b, 24a and 24b. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A gaming effect LED 2 is provided on the outer periphery of the gaming area 7.
8a and gaming effect lamps 28b and 28c are provided.

In this example, one of the speakers 27
Prize ball lamp 5 that lights up when there are remaining prize balls near
1 is provided, and near the other speaker 27, a ball-out lamp 52 is provided, which lights up when the supply ball is out. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and that allows a ball to be lent by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is usable. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hitting ball fired from the hitting ball launching device enters the game area 7 through the hitting ball rail, and thereafter, enters the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the number displayed on the symbol display 10 normally changes. When a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17,
If the change of the symbol can be started, the symbol in the variable display section 9 starts rotating. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. When the hit ball wins in the specific winning area while the opening and closing plate 20 is being opened and is detected by the V winning switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. The continuation right is generated a predetermined number of times (for example, 15 rounds)
Permissible.

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol = small hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, each board disposed on the back of the pachinko gaming machine 1 will be described. As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2A, and above the pachinko gaming machine 1 installed on the gaming machine installation island. The game ball is supplied to the ball storage tank 38 from. The game balls in the ball storage tank 38 pass through a guiding gutter 39 to reach a ball dispensing device covered with a prize ball case 40A.

On the back side of the gaming machine, a variable display control unit 29 for controlling the variable display section 9 and a game control board (main board) 31 on which a game control microcomputer and the like are mounted are installed. A payout control board 37 on which a payout control microcomputer or the like for performing ball payout control is mounted;
And a hit ball launching device that launches a hit ball into the game area 7 using the rotational force of a motor. Furthermore, the decoration lamp 25, the game effect LED 28a, the game effect lamp 28
b, 28c, a lamp control board 35 for sending signals to the prize ball lamp 51 and the ball out lamp 52, a voice control board 70 for controlling the generation of voice from the speaker 27, and a launch control for controlling the hit ball launching device. A substrate 91 is also provided. Note that an error display LED 374 is also mounted on the payout control board 37.

Also, DC30V, DC21V, DC12
A power supply board 910 on which a power supply circuit for generating V and DC5V is mounted is provided, and a terminal board 16 having terminals for outputting various information to the outside of the gaming machine is provided above.
0 is set. The terminal board 160 has at least an out-of-ball terminal for introducing and outputting the output of the out-of-ball detection switch, an award ball terminal for externally outputting the award ball number signal, and an externally outputting ball lending number signal. A ball lending terminal is provided. In the vicinity of the center, an information terminal board 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is provided.

Further, in FIG. 2, signals from the lamp control board 35 and the voice control board 70 are transmitted to the game effect LEDs 28a, game effect lamps 28b, 2 provided on the frame side.
8c, an illuminated relay board A77 for supplying the prize ball lamp 51 and the ball cut lamp 52, and a balance display board 74 equipped with a frequency display LED and the like are shown. In this embodiment, the variation data storage means (for example, the main board 31, the payout control board 37) included in each board (for example,
A switch board 190 on which a clear switch 921 for clearing backup data stored in a backup RAM) is provided. The switch board 190 is provided with a connector (see FIGS. 6 and 7) connected to another board such as a main board. Further, although not shown, other relay boards are provided as necessary for signal relay.

FIG. 3 is a rear view of the mechanical plate of the pachinko gaming machine 1 as viewed from the rear. The balls stored in the ball storage tank 38 pass through the guide gutter 39, pass through the ball cut detectors (ball cut switches) 187a and 187b, and are dispensed through the ball supply gutters 186a and 186b, as shown in FIG. The device 97 is reached. The ball out switches 187a and 187b are switches for detecting the presence or absence of a game ball in the game ball passage.
67 is also provided. Hereafter, the ball out switch 187
a, 187b may be expressed as a ball-out switch 187.

The game balls paid out from the ball payout device 97 are supplied to the hit ball supply plate 3 provided on the front face of the pachinko gaming machine 1 through the communication port 45. On the side of the communication port 45, an excess ball passage 46 communicating with the excess ball tray 4 provided on the front of the pachinko gaming machine 1 is formed.

A number of prize balls are paid out based on the prize, and the hitting ball supply tray 3 becomes full.
When the game balls are further paid out after reaching 5, the game balls are guided to the surplus ball tray 4 via the surplus ball passage 46. When the game balls are further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In that state, the rotation of the stepping motor in the ball discharging device 97 stops, the operation of the ball discharging device 97 stops, and the driving of the hit ball firing device 34 also stops.

Next, the structure of the intermediate base unit installed on the mechanism plate 36 will be described. The intermediate base unit includes the ball supply gutters 186a and 186b and the ball discharging device 9
7 is installed. As shown in FIG. 4, connecting concave protrusions 182 are formed on the upper and lower sides of the intermediate base unit. The connection concave projection 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

A passage member 18 is provided above the intermediate base unit.
4 is fixed. The ball dispensing device 97 is fixed to a lower portion of the passage body 184. The passage body 184 is a payout ball passage 186 that allows two rows of game balls whose flow direction has been changed left and right by the curve gutter 174 (see FIG. 3) to flow down.
a, 186b. Dispensing ball passages 186a, 186b
On the upstream side of the ball, ball breaking switches 187a and 187b are provided. The ball out switches 187a and 187b
It detects the presence or absence of a game ball in the payout ball passages 186a and 186b, and detects a ball out switch 187a or 187b.
Stops detecting the game ball, the rotation of the payout motor (not shown in FIG. 4) in the ball payout device 97 is stopped, and the ball payout is immobilized.

It should be noted that the ball out switches 187a, 187b
Is locked by a locking piece 188 at a position where it can be detected that about 27 to 28 game balls exist in the payout ball paths 186a and 186b. That is, the out-of-ball switches 187a and 187b are the maximum payout amount of one unit of the prize ball (15 in this embodiment) and the maximum payout amount of one unit of the ball lending (100 yen: 25 in this embodiment).
It is installed in a position where it can be confirmed that the above is secured.

The central portion of the passage body 184 is formed in a shape curved right and left so as to reduce the ball pressure of the game ball flowing down inside. And the payout ball passages 186a, 186b
A stop hole 189 is formed therebetween. The mounting boss provided on the intermediate base unit is fitted into the back surface of the stop hole 189. The set screw is screwed in that state,
The passage body 184 is fixed to the intermediate base unit. Before being screwed, the positioning of the passage body 184 can be performed by a locking projection 185 provided on the intermediate base unit.

A ball dispensing device 97 is provided below the passage body 184.
To supply the game balls to the ball, and in the event of failure, the ball payout device 9
A ball stopping device 190 for stopping the supply of game balls to the game ball 7 is provided. The ball dispensing device 97 installed below the ball stopping device 190 is housed inside a rectangular parallelepiped case 198. Protrusions are provided at four places on the left and right of the case 198. The lower end of the case 198 is fitted into an elastic engagement piece provided at a lower portion of the intermediate base unit with each projection being related to a positioning projection provided on the intermediate base unit.

FIG. 5 is an exploded perspective view of the ball payout device 97. The configuration and operation of the ball payout device 97 will be described with reference to FIG. Ball payout device 97 in this embodiment
, A stepping motor (payout motor) 289 rotates a screw 288 to pay out pachinko balls one by one. The ball payout device 97 pays out not only premium balls based on winnings but also game balls to be lent.

As shown in FIG. 5, the ball dispensing device 97
There are two cases 198a and 198b. The ball dispensing device 9 is provided at two places on the left and right of each case 198a, 198b.
7 is provided with an engagement projection 280 that is in contact with a positioning projection provided at the upper part of the installation position. In each case 198a, 198b, a ball supply path 281a,
81b are formed. Ball supply path 281a, 281b
Has curved surfaces 282a and 282b, and has curved surfaces 282a and 282b.
Below the end of 282b, there is a ball feed horizontal path 284a, 2
84b are formed. In addition, ball feed horizontal path 284
Ball discharge passages 283a and 283b are formed at the ends of a and 284b.

The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b.
Are formed in front of partition walls 295a and 295b that partition the cases 198a and 198b forward and backward, respectively.
Further, in front of the partition walls 295a and 295b, a ball pressure buffering member 285 is sandwiched between the cases 198a and 198b. The ball pressure buffering member 285 distributes the ball supplied to the ball payout device 97 to the left and right sides and the ball supply paths 281a, 281.
81b.

Further, below the ball pressure buffering member 285, a payout motor position sensor including a light emitting element (LED) 286 and a light receiving element (not shown) is provided. Light emitting element 2
86 and the light receiving element are provided at a predetermined interval. The distal end of the screw 288 is inserted into the space. The ball pressure buffering member 28
When the cases 198a and 198b are attached to each other, the case 5 is completely stored and fixed therein.

The ball feed horizontal paths 284a and 284b have a screw 28 rotated by a payout motor 289.
8 are arranged. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 is
Fixing grooves 291a, 2 formed behind 5a, 295b
Fits into 91b. In this state, the motor shaft of the dispensing motor 289 projects forward of the partition walls 295a, 295b, so that the screw 288 is fixed forward of the projection. On the outer periphery of the screw 288, a spiral protrusion 288a for moving the game ball placed on the ball feed horizontal path 284a, 284b forward by the rotation of the payout motor 289.
Is provided.

A recess is formed at the tip of the screw 288 so as to house the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, while the screw 288 makes one rotation, the light from the light emitting element 286 is
Is detected twice by the light receiving element via the.

That is, the dispensing motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position and detecting that the dispensing operation has been performed. The wires from the light emitting element 286, the light receiving element, and the payout motor 289 are collectively pulled out to the outside through drawout holes formed below the rear portions of the cases 198a, 198b, and connected to the connector.

When the game ball is a ball feeding horizontal path 284a, 284b
When the payout motor 289 rotates in a state where the screw 288 is placed on the
The game ball moves forward on the ball feeding horizontal paths 284a and 284b. And finally, ball feed horizontal path 28
4a, 284b from the end of the ball discharge path 283a, 283b
To fall. At this time, the left and right ball feed horizontal paths 284a,
The drop from 284b is performed alternately. That is, every time the screw 288 makes a half turn, one game ball falls from one side. Therefore, every time one game ball falls, light from the light emitting element 286 is detected by the light receiving element.

As shown in FIG. 4, below the ball payout device 97, a ball distribution member 311 is provided. The ball distribution member 311 is driven by the distribution solenoid 310.
For example, when the solenoid 310 is on, the ball sorting member 3
11 falls to the right, and when off, falls to the left. Below the distribution solenoid 310, a prize ball count switch 301A and a ball lending count switch 3 by a proximity switch are provided.
01B is provided. At the time of prize ball based on winning,
The ball distribution member 311 falls to the right side, and the ball discharge paths 283a, 283
The balls from 83b are both prize ball count switches 301A
Pass through. Also, at the time of lending a ball, the ball distribution member 311 falls to the left, and the balls from the ball discharge paths 283a and 283b both pass through the ball lending count switch 301B. Accordingly, the ball payout device 97 can switch the payout flow path between the time of winning a ball and the time of lending a ball, and can pay out a predetermined number of game media.

By providing the ball distribution member 311 in this manner, the balls falling down the two ball passages can receive the prize ball count switch 301A and the ball lending count switch 30.
1B. Therefore,
The number of prize balls or the number of ball lending can be immediately grasped from the detection output of the prize ball counting switch 301A and the ball lending count switch 301B without determining whether the ball is a prize ball or a ball lending.

In this embodiment, a ball payout device 97 that pays out game balls by rotation of a stepping motor is used as a ball payout device that pays out game balls by driving an electric drive source. A ball dispensing device having a structure in which game balls are sent out by a driving source of (i) may be used, or a ball dispensing device having a structure in which a stopper is removed by driving an electric drive source and the game balls are paid out by its own weight may be used. In this embodiment, the ball payout device 97 pays out both a prize ball based on a prize ball and a loaned ball based on a loan request, but a payout device may be provided for each.

FIG. 6 is a front view showing an example in which the gaming board 6 on which the switch board 190 is mounted is viewed from the front. In FIG. 2, a switch board 190 is provided on the back of the pachinko gaming machine 1.
Has been described as an example of a state in which the game board 1 is mounted, but in more detail, as shown in FIG. 6, for example, as shown in FIG. It is installed in. FIG. 6 shows a connector 92 for connecting to another board such as a main board.
2 are disclosed.

FIG. 7 is a circuit diagram showing an example of the circuit configuration of the clear switch 921 mounted on the switch board 190. The clear switch 921 has a push button structure in this example. If the clear switch 921 is pressed (if it is in the ON state), a low-level clear switch signal is output and transmitted to each board such as the main board 31 via the connector 922. If the clear switch 921 is not pressed (if it is in the off state), a high-level output signal is output.

FIG. 8 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 8 also shows a payout control board 37, a lamp control board 35, a voice control board 70, a firing control board 91, a symbol control board 80, and a switch board 190. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12, a starting port switch 17, a V winning switch 22, a count switch 23, and a winning port switch 19 are provided.
a, 19b, 24a, 24b, full tank switch 48, ball out switch 187, and prize ball count switch 301
A switch circuit 58 for providing a signal from A to the basic circuit 53
And a solenoid 16 for opening and closing the variable winning prize ball device 15, a solenoid 21 for opening and closing the opening and closing plate 20, and a solenoid 21A for switching the path in the special winning opening.
And a solenoid circuit 59 driven in accordance with a command from the control unit 3. In this embodiment, the switch circuit 58 also supplies a signal from the clear switch 921 mounted on the switch substrate 190 to the basic circuit 53. Although not shown in FIG. 8, the count switch short-circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the variable display section 9, and probability fluctuation have occurred. An information output circuit 64 for outputting an information output signal such as probability change information indicating the fact to an external device such as a hall computer is mounted.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal.

Further, the main board 31 is provided with a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on.

A hit ball launching device that hits and fires a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decorative lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. The display control of the variable display unit 9 for variably displaying special symbols and the ordinary symbol display 10 for variably displaying ordinary symbols is performed by display control means mounted on the symbol control board 80.

FIG. 9 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 9, the detection signal from the full tank switch 48 is transmitted to the main board 3 via the relay board 71.
1 is input to the I / O port 57. Full tank switch 4
Reference numeral 8 denotes a switch for detecting whether the surplus ball tray 4 is full. In addition, the ball out switch 187 (187a, 187)
The detection signal from b) is also used for the relay board 72 and the relay board 7.
1 is input to the I / O port 57 of the main board 31.

The CPU 56 of the main board 31 checks whether the detection signal from the ball out switch 187 indicates that the ball is out.
Alternatively, when the detection signal from the full tank switch 48 indicates the full tank state, a payout control command to instruct payout prohibition is transmitted. When receiving the payout control command instructing the payout prohibition, the payout control CPU 37 of the payout control board 37
1 stops the ball payout process.

Further, the detection signal from the prize ball count switch 301A is input to the relay board 72 and the I / O port 57 of the main board 31 via the relay board 71, and the payout control board via the relay board 72. 37 is input to the input port 372b. Prize ball count switch 301
A is provided in the payout mechanism portion of the ball payout device 97 and detects the actually won prize ball payout balls.

When there is a prize, the payout control board 37 has output ports (ports 0, 1) 570, 571 of the main board 31.
, A payout control command indicating the number of winning balls is input. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). The payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371
A payout control command is input via the / O port 372a, and the ball payout device 97 is driven in accordance with the payout control command to perform award ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and has at least a RAM.

In the main board 31, the output port 5
Buffer circuits 620 and 68A are provided outside 70 and 571. As the buffer circuits 620 and 68A, for example, 74HC250 and 7HC which are general-purpose CMOS-ICs
4HC14 is used. According to such a configuration, since a signal inputted from the outside to the inside of the main board 31 is blocked, a signal line to which a signal may be given from the payout control board 37 to the main board 31 is further reliably eliminated. be able to. Note that a noise filter may be provided on the output side of the buffer circuits 620 and 68A.

The payout control CPU 371 is connected to the output port 3
A ball lending number signal indicating the number of lending balls is output to the terminal board 160 via 72c. Further, the output port 37
An error signal is output to the error display LED 374 via 2d.

Further, the input port 3 of the payout control board 37
The detection signal from the ball lending count switch 301B is input to 72b via the relay board 72. The ball lending count switch 301B is provided in the payout mechanism portion of the ball payout device 97, and detects the actually paid lending balls.
The drive signal from the payout control board 37 to the payout motor 289 is supplied to the payout motor 28 in the payout mechanism of the ball payout device 97 via the output port 372c and the relay board 72.
9 and the drive signal to the distribution solenoid 310 is
The distribution solenoid 310 in the dispensing mechanism of the ball dispensing device 97 via the output port 372e and the relay board 72.
Conveyed to.

The card unit 50 is provided with a microcomputer for controlling the card unit. Also,
The card unit 50 is provided with a fraction display switch 152, a connection board direction indicator 153, a card insertion indicator lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected to a frequency display LED, a ball lending switch, and a return switch provided near the hit ball supply tray 3.

From the balance display board 74 to the card unit 50
In response to the operation of the player, a ball lending switch signal and a return switch signal are given via the payout control board 37. In addition, the balance display board 74 is provided from the card unit 50.
, A card balance display signal indicating the balance of the prepaid card and a ball lending possible display signal are given via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal) and a unit operation signal (B
RDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal (P
RDY signal) is input port 372b and output port 3
It is exchanged via 72e.

When the power of the pachinko gaming machine 1 is turned on,
The payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connection state / non-connection state based on the input state of the VL signal. When the card is accepted in the card unit 50 and the ball lending switch is operated to input a ball lending switch signal, the microcomputer for controlling the card unit outputs a BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this point, the microcomputer for controlling the card unit outputs a BRQ signal to the payout control board 37.

The payout control board 37 of the payout control board 37
When the PU 371 raises the EXS signal to the card unit 50 and detects the fall of the BRQ signal from the card unit 50, it drives the payout motor 289 and pays out a predetermined number of loaned balls to the player. At this time, the distribution solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 sets the card unit 5
The EXS signal for 0 falls. Thereafter, if the BRDY signal from the card unit 50 is not in the ON state,
The winning ball payout control is executed.

As described above, all signals from the card unit 50 are input to the payout control board 37. Therefore, regarding the ball lending control, the card unit 5
No signal is input from 0 to the main board 31, and there is no room for a signal to be incorrectly input from the card unit 50 side to the basic circuit 53 of the main board 31. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

In this embodiment, the case where the card unit 50 is installed separately from the gaming machine and adjacent to the gaming machine is described as an example, but the card unit 50 is integrated with the gaming machine. You may. Also, the present invention can be applied to a case where a gaming machine rents a game ball corresponding to the amount of money when a coin is inserted.

FIG. 10 is a block diagram showing an example of the configuration of the power supply board 910. The power supply board 910 includes a main board 31,
It is installed independently of the electric component control boards such as the symbol control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and generates a voltage used by each electric component control board and mechanical components in the gaming machine. . In this example, AC
24V, VSL (DC + 30V), DC + 21V, DC +
Generates 12V and + 5V DC. Further, the capacitor 916 serving as a backup power supply is charged from DC + 5V, that is, a power supply line for driving an IC or the like on each substrate. Note that VSL is generated in the rectifier circuit 912 by rectifying and boosting 24 V AC by a rectifier.
VSL is a solenoid drive power supply.

Transformer 911 converts an AC voltage from an AC power supply to 24V. AC 24V voltage is applied to connector 9
15 is output. Further, the rectifier circuit 912 includes an AC24
A DC voltage of +30 V is generated from V and output to the DC-DC converter 913 and the connector 915. DC-D
C converter 913 includes one or more converters I
C922 (only one is shown in FIG. 10) and VSL
Then, + 21V, + 12V, and + 5V are generated based on the above and output to the connector 915. A relatively large-capacity capacitor 923 is connected to the input side of the converter IC 922. Therefore, when the power supply to the gaming machine from the outside is stopped, the DC voltage such as +30 V, +12 V, +5 V, etc., decreases relatively slowly. As a result, the capacitor 923 plays a role of an auxiliary driving power supply described later.
The connector 915 is connected to, for example, a relay board, and power of a voltage required for each electric component control board and a mechanical component is supplied from the relay board.

However, the power supply board 910 may be provided with each connector leading to each electric component control board, and the power supply board 910 may supply each voltage reaching each board without passing through the relay board. FIG. 10 shows one connector 915 as a representative, but the connectors are provided corresponding to the respective electric component control boards.

+5 V from DC-DC converter 913
The line branches to form a backup + 5V line. A large-capacity capacitor 916 is connected between the backup + 5V line and the ground level. The capacitor 916 is in a storage state with respect to a backup RAM (RAM backed up by a power supply, that is, a backup storage unit that can be in a storage content state even when the power supply is stopped) of the electric component control board when the power supply to the gaming machine is cut off. Backup power supply that supplies power so that the power can be maintained. Further, a diode 917 for preventing backflow is inserted between the + 5V line and the backup + 5V line. In this embodiment, +5 V for backup is applied to the main board 31 and the payout control board 37.
Supplied to

Note that a battery that can be charged from a +5 V power supply may be used as a backup power supply. In the case of using a battery, a rechargeable battery is used which runs out of capacity when power is not supplied from a + 5V power supply for a predetermined time.

The power supply board 910 has a power supply monitoring I
C902 is mounted. The power supply monitoring IC 902
The occurrence of power interruption is detected by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), it is determined that the power is cut off, and a voltage drop signal (power cutoff signal) is output. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after conversion from AC to DC, is used. The voltage drop signal from the power monitoring IC 902 is
It is supplied to the main board 31, the payout control board 37 and the like.

The predetermined value for the power supply monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage at which the CPU on each electric component control board can operate for a while. Further, the power supply monitoring IC 902 is configured to monitor a voltage higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and a voltage immediately after conversion from AC to DC. Therefore, the monitoring range can be extended for the voltage required by the CPU. Therefore,
More precise monitoring can be performed. Furthermore, when VSL (+30 V) is used as the monitoring voltage, since the voltage supplied to the various switches of the gaming machine is +12 V, prevention of erroneous switch-on detection upon momentary power interruption can be expected. That is, when monitoring the voltage of the + 30V power supply,
The drop can be detected at a stage before + 12V generated after the generation of 0V starts to fall.

Therefore, when the voltage of the +12 V power supply drops, the switch output comes to an on state,
If the power supply interruption is recognized by monitoring the +30 V power supply voltage that falls earlier than V, the power supply wait state can be entered before the switch output turns on, and the switch output can not be detected.

Further, since the power supply monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the power supply monitoring circuit can supply a power-off signal to the plurality of electric component control boards. No matter how many electrical component control boards need a power-off signal, it is sufficient that only one power supply monitoring means is provided. Therefore, even if each electrical component control means in each electrical component control board performs return control described later, However, the cost of gaming machines does not increase much.

In the configuration shown in FIG. 10, the detection output (power cutoff signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control signal) via the buffer circuits 918 and 919. Although transmitted to the board 37), for example, a configuration in which one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board may be employed. Further, a buffer circuit may be provided according to the number of substrates that require a power-off signal.

FIG. 11 shows the CPU 56 on the main board 31.
It is a block diagram which shows the example of a surrounding structure. As shown in FIG. 11, the power supply cutoff signal (voltage drop signal) from the power supply monitoring circuit (power supply monitoring unit) of the power supply board 910 is transmitted to the CPU 56.
Are connected to the non-maskable interrupt terminal (XNMI terminal). The power supply monitoring circuit is a circuit that monitors a voltage of any one of various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and when the voltage value becomes equal to or lower than a predetermined value, a low-level power-off signal is generated. VSL is the largest DC voltage used in gaming machines, and in this example is +30.
V. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt processing.

FIG. 11 also shows a system reset circuit 65. When the power is turned on, the reset IC 651
The output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage VSL, which is the same power supply voltage as the power supply voltage monitored by the power supply monitoring circuit, and determines that the voltage value is a predetermined value (lower than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). Value), the output goes low. Therefore, the CPU 56 performs a predetermined power supply stop processing in response to a power-off signal from the power supply monitoring circuit, and then performs a system reset.

As shown in FIG. 11, the reset IC 651
Is input to the NAND circuit 947 and also to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. When the input to the clear terminal goes low, the counter IC 941 counts the clock signal from the oscillator 943.
The Q5 output of the counter IC 941 is output to the NOT circuit 9
45, 946 and input to the NAND circuit 947. The Q6 output of the counter IC 941 is input to a clock terminal of a flip-flop (FF) 942.
The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The other input of the OR circuit 949 is connected to the NAND circuit 9.
The output of 47 is introduced via NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on.
Starts operation reliably.

Then, for example, the detection voltage of the power supply monitoring circuit (the voltage at which the power supply cutoff signal is output) is set to +22 V, and the detection voltage for setting the reset signal to low level is set to +9 V. In such a configuration, the power supply monitoring circuit and the system reset circuit 65 are connected to the same power supply VSL.
, The difference between the timing at which the voltage monitoring circuit outputs the power-off signal and the timing at which the system reset circuit 65 outputs the system reset signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop processing in response to the power supply cutoff signal from the power supply monitoring circuit until the power supply stop processing is completely completed.

While power is not supplied from the + 5V power supply which is the driving power supply of the CPU 56 and the like, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board, and the contents are maintained even if the power supply to the gaming machine is cut off. Is saved. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to the normal operation state. At that time, since the necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of the occurrence of the power failure when recovering from a power failure or the like.

In the configuration shown in FIG. 11, two reset signals (low-level signals) are supplied to the reset terminal of the CPU 56 when the power is turned on. However, even if the reset signal rises only once, the reset is reliably performed. When the CPU to be released is used, reference numerals 941 to 949
The circuit element indicated by is not required. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

CPU 56 used in this embodiment
Incorporates an I / O port (PIO) and a timer / counter circuit (CTC). PIO is PB0-PB
It has a port of 3 4 bits and 1 byte of PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set for both input and output.

As shown in FIG. 11, the output signal of the clear switch 921 mounted on the switch board 190 is input via a buffer circuit 578A for inverting logic and an input port 578. The input port 578 also receives the output signals of other switches such as the V winning switch 22 via the buffer circuit 578A. According to such a configuration, the clear switch 92
If the output signal is a clear switch signal (low level signal) by switching 1, the clear switch signal is inverted (the signal output by the buffer circuit 578A after inverting the clear switch signal is called a clear switch signal). Is given to the CPU 56, so that the CP
A process is performed in which the contents stored in the variable data storage unit are used as initial data by U56, the details of which will be described later. As described above, since the output signal of the clear switch 921 is input via the input port 578, the clear switch signal can be introduced with a simple configuration.

FIGS. 12 and 13 are explanatory diagrams showing the assignment of output ports in this embodiment. Figure 1
As shown in FIG. 2, output port 0 is an output port for a strobe signal (INT signal) of a control command sent to each electric component control board. The 8-bit data of the payout control command sent to the payout control board 37 is output from the output port 1, and the 8-bit data of the display control command sent to the symbol control board 80 is output from the output port 2. The 8-bit data of the lamp control command sent to the lamp control board 35 is output from the output port 3. Then, as shown in FIG.
Is output from the output port 4.

The output port 5 is connected to the information output circuit 6
4, various information output signals reaching the information terminal board 34, that is, output data of information related to control are output. Drives from the output port 6 to a solenoid 16 for opening and closing the variable winning ball device 15, a solenoid 21 for opening and closing the opening and closing plate 2 of the special winning opening, and a solenoid 21A for switching a path in the special winning opening. A signal is output.

FIG. 14 is an explanatory diagram showing bit assignment of input ports in this embodiment. As shown in FIG. 14, bits 0 to 7 of the input port 0 include a winning opening switch 24a, a winning opening switch 24b, a winning opening switch 19a, a winning opening switch 19b, a start opening switch 17, a count switch 23, and a V switch, respectively. The detection signals of the winning switch (specific area switch) 22 and the gate switch 12 are input. Also, bits 0 to 4 of input port 1
, The detection signal of the prize ball count switch 301A, the full tank switch 48, the detection signal of the ball out switch 187, the count switch short circuit signal, and the output signal of the clear switch 921 are input.

Next, the operation of the gaming machine will be described. Figure 1
5 is a flowchart showing the main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56
First, necessary initial settings are made.

In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode is set to the interrupt mode 2 (step S2), and a stack pointer designated address is set to the stack pointer (step S3). Then, the internal device registers are initialized (step S4). After initializing a built-in device (built-in peripheral circuit) CTC (counter / timer) and PIO (parallel input / output port) (step S5), the RAM is set to an accessible state (step S6).

CPU 5 used in this embodiment
6 has the following three types of modes as maskable interrupt (INT) modes. When an interrupt that can be masked occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

Interrupt mode 0: The built-in device that has issued the interrupt request receives an RST instruction (1 byte) or a CALL instruction (3 bytes).
Byte) on the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. Upon reset, CPU 56 automatically switches to interrupt mode 0
become. Therefore, when it is desired to set the mode to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the mode to the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

Interrupt mode 1: When an interrupt is accepted,
In this mode, the camera always jumps to the address 0038 (h).

Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is the interrupt address. Mode. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary (albeit skipped) even address. Each built-in device has a function of sending an interrupt vector when making an interrupt request.

Therefore, when the interrupt mode 2 is set, it is possible to easily process an interrupt request from each built-in device, and it is possible to set an interrupt process at an arbitrary position in a program. Will be possible. Further, unlike the interrupt mode 1, it is easy to prepare an interrupt process for each interrupt occurrence factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

Next, the CPU 56 sets the input port 578
In this example, the state of the output signal of the clear switch 921 input via the terminal is confirmed only once (step S7).
When the clear switch 921 is on (when pressed), a low-level clear switch signal is output. Therefore, the CPU 56 sets the clear switch 9
If the switch 21 is turned on, a normal initialization process is performed (steps S11 to S15). It is preferable to perform the ON determination of the clear switch 921 before performing the initial setting. This is because the control can be resumed after confirming the intention of erasing the backup storage (final storage contents) prior to the activation of the gaming machine. In such a case, if timer processing or switch input determination (a plurality of times) is performed before the initial setting, the backup contents may be destroyed. Also, on the back side of the pachinko gaming machine during the game, the game balls are flowing and noise is likely to be generated. Therefore, the normal switch detection performs the input determination a plurality of times. Since it is performed before the start, it is not easily affected by noise. Therefore, the clear switch 92
Even if one input determination is performed only once, it is hardly affected by noise, and the program development efficiency is increased. When importance is attached to whether or not the clear switch 921 has been securely operated, the CPU 56 may check the state of the output signal of the clear switch 921 for, for example, three seconds.

If the clear switch 921 is not in the ON state (the state in which the clear switch 921 is not pressed), the CPU 56 performs data protection processing (for example, power failure occurrence NMI processing such as addition of parity data) of the backup RAM area when the power is turned off. It is confirmed whether or not it has been performed (step S8). In this embodiment, when an unexpected power failure occurs, the backup R
A process for protecting the data in the AM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup,
U56 executes an initialization process.

In this embodiment, the backup RAM
Whether or not there is backup data in the area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. In this example, as shown in FIG. 16, if "55H" is set in the backup flag area, it means that there is a backup (on state),
If a value other than “55H” is set, it means that there is no backup (off state).

When the backup is confirmed, the CPU 5
Reference numeral 6 performs data check (parity check in this example) of the backup RAM area. If the power is restored after an unexpected power failure, the data in the backup RAM area should have been saved, and the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on without power recovery is executed.

If the check result is normal (step S
9) The CPU 56 performs a game state restoring process for returning the internal state of the game control means and the control state of the electric component control means such as the display control means to the state at the time of power-off (step S1).
0). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

In this embodiment, step S7
When the clear switch 921 is not turned on, the presence or absence of backup data is confirmed. Conversely, after confirming the presence or absence of backup data, if backup data exists (the backup area is further checked and the backup area is checked. The operation state of the clear switch 921 may be confirmed when the result of the area check is normal.

In this embodiment, step S8
The backup area is checked in step S9 after the presence or absence of the backup data is confirmed in step S9. On the other hand, after the backup area check result is confirmed to be normal in step S9. ,
The presence or absence of backup data may be confirmed. Alternatively, whether to execute the power failure recovery process may be determined by confirming whether there is backup data or checking the backup area.

Further, for example, at the time of the parity check (step S9) when determining whether or not to execute the power failure recovery processing, that is, at the time of determining whether or not to restore the gaming state, the stored RAM data According to the special process flag etc. and the start winning prize storage data, the gaming machine is in the game standby state (the symbol is not fluctuating,
If it is confirmed that the game is not being changed reliably and that there is no start winning memory, the initialization process may be executed without performing the game state restoration process.

As described above, it is determined whether or not the game is returned to the game state at the time of power-off according to the operation state of the clear switch 921. At this time, if the clear switch 921 is in the on state, the game state is determined. Since the recovery processing is not performed and the normal initialization processing is performed, the game clerk or the like can use the clear switch 921 when the power supply of the gaming machine is restarted.
By operating, it is possible to select whether or not to execute the game state restoration process based on the backup data stored in the backup data storage area (variable data storage means). Therefore, there is provided a gaming machine which can prevent a disadvantage from being brought to a player even if a power failure occurs, and can also improve convenience in operating a gaming machine in a gaming arcade.

It is to be noted that the initialization process executed when the backup data is not stored in the variable data storage means when the power is turned on, and that the clear switch 921 is turned off even if the backup data is stored in the variable data storage means. The initialization process executed in the case of (1) is also used in the program. Therefore, even if control for improving the operational convenience at the game store is added, the program capacity does not increase so much.

In the initialization process, the CPU 56 first sets R
An AM clear process is performed (step S11). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer,
An initial value setting process for setting an initial value to a payout command storage pointer or the like is also performed. Further, a process for initializing the sub-boards (the lamp control board 35, the payout control board 37, the voice control board 70, and the symbol control board 80) is executed (step S13). The process of initializing the sub board is
For example, a process of transmitting an initialization command.

Then, the register of the CTC provided in the CPU 56 is set so that the timer is interrupted periodically every 2 ms (step S14). That is,
A value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S1 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S1).
5).

In this embodiment, the built-in C
The TC is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. When a timer interrupt occurs, as shown in FIG. 17, the CPU 56 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred (step S10).
12).

Execution of initialization processing (steps S11 to S1)
When 5) is completed, the process proceeds to a loop process in which the main process checks whether or not a timer interrupt has occurred (step S17). In the loop, a display random number update process (step S16) is also executed.

The CPU 56 determines in step S17 that
Upon recognizing that a timer interrupt has occurred, step S2
The game control processing of 1 to S31 is executed. In the game control process, the CPU 56 firstly receives, via the switch circuit 58, the gate sensor 12, the starting port sensor 17, the count sensor 23, and the winning port switches 19a, 19b, 24.
The states of the switches such as a and 24b are input and their states are determined (switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating each counter indicating a random number for determination, such as a random number for big hit determination used in game control, is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the normal symbol process process, a corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

Next, the CPU 56 sets a display control command relating to the special symbol in a predetermined area of the RAM 55 and sends the display control command (special symbol command control process: step S27). Further, a display control command relating to a normal symbol is set in a predetermined area of the RAM 55, and a process of transmitting the display control command is performed (ordinary symbol command control process: step S28).

Further, the CPU 56 performs an information output process of outputting data such as jackpot information, start information, and probability variation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

Then, the CPU 56 has switches 17, 23, 19a, 19 for detecting a winning in each winning opening.
A prize ball process for setting the number of prize balls based on the detection outputs of b, 24a and 24b is executed (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the payout control command.

According to the above control, in this embodiment, the game control process is started every 2 ms.
In this embodiment, for example, in the timer interrupt processing, only a flag indicating that an interrupt has occurred is set, and the game control processing is executed in the main processing.
The game control process may be executed by a timer interrupt process.

The main process includes a process of determining whether or not to shift to the game control process. The internal timer of the CPU 56 performs a timer interrupt process based on a timer interrupt that is periodically generated. Since a flag for determining whether or not to shift is set or the like, all of the game control processing is reliably executed. In other words, until all of the game control processes have been executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all processes in the game control process will be completed. ing.

As described above, in this embodiment, the interrupt mode 2 is set by the initial setting process for the CPU 56 having a built-in CTC or PIO. Accordingly, a periodic timer interrupt process using the built-in CTC can be easily realized. Further, the timer interrupt processing can be set at an arbitrary position on the program. Further, switch detection processing using the built-in PIO can be easily realized by interruption processing. As a result, effects such as simplification of the program configuration and reduction in the number of program development steps can be obtained.

After the setting of CTC and PIO (step S5) is completed, an internal register for determining the frequency of the clock signal output from the IEO / SCLK0 terminal may be set. At that time, the frequency of the clock signal is set to a frequency corresponding to 2 ms, which is the start cycle of the game control process. With such settings, IEO /
From the SCLK0 terminal, a clock signal having a frequency corresponding to the activation cycle of the game control process is externally output from the CPU 56. Then, a signal corresponding to the start cycle of the game control process can be observed outside the CPU 56. Therefore, using such a signal, CP
Simulate the game control process by U56,
It becomes easy to test the operation status of the CPU 56.

Further, of the output ports 0 to 6 shown in FIGS. 12 and 13, output ports 0, 1, 2, 3, 4
Is accessed in a special symbol command control process (step S25), a normal symbol command control process (step S27), a prize ball process (step S31) and the like in the game control process. The output port 5 is accessed in information output processing (step S29), and the output port 6 is accessed in special symbol processing (step S25) and ordinary symbol processing (step S26).

Next, a specific example of the switch processing (step S21) in the main processing will be described. In this embodiment, when the on state of the detection signal continues for a predetermined time, it is determined that the switch has been turned on, and the processing corresponding to the switch on is started. A switch timer is used to measure a predetermined time. The switch timer is a 1-byte counter formed in the backup RAM area, and is incremented by 1 every 2 ms when the detection signal indicates the ON state. As shown in FIG. 18, switch timers are provided by the number N of detection signals. In this embodiment, N = 12. Note that N = 12 (not 13)
This is because a switch timer corresponding to the output signal of the clear switch 921 is not provided (it is unnecessary because the determination of whether or not a clear signal is detected is not performed in the switch processing). In the RAM, the addresses of the switch timers are arranged in the same order as the bit arrangement order of the input ports (the order from the top to the bottom shown in FIG. 14).

FIG. 19 is a flowchart showing a processing example of the switch processing in step S21 in the game control processing. The switch process is first executed in the game control process as shown in FIG. In the switch processing, the CPU 56 first inputs data input to the input port 0 (step S71). Next, "8" is set as the number of processes (step S72), and the address of the switch timer for the winning opening switch 24a is set in the pointer (step S73). Then, a switch check processing subroutine is called (step S74).

FIG. 20 is a flowchart showing a switch check processing subroutine. In the switch check processing subroutine, the CPU 56 sets the port input data, in this case, the input data from the input port 0, as a “comparison value” (step S81). Also,
Set clear data (00) (step S8)
2). Then, the switch timer indicated by the pointer (the address of the switch timer is set) is loaded (step S83), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S8).
4). The data of the input port 0 is set as the comparison value. In this case, the detection signal of the winning opening switch 24a is pushed out by the carry flag.

If the value of the carry flag is "1" (step S85), that is, if the detection signal of the winning opening switch 24a is on, the value of the switch timer is incremented by 1 (step S87). If the value after the addition is not 0, the added value is returned to the switch timer (steps S88 and S8).
9). When the value after the addition becomes 0, the added value is not returned to the switch timer. That is, if the value of the switch timer has already reached the maximum value (255), the value is not increased further.

If the value of the carry flag is "0", that is, if the detection signal of the winning opening switch 24a is in an off state, clear data is set in the switch timer (step S86). That is, if the switch is off, the value of the switch timer returns to zero.

Thereafter, the CPU 56 increments the pointer (the address of the switch timer) by 1 (step S90) and decrements the number of processes by 1 (step S91). If the number of processes has not become zero, the process returns to step S82. Then, the processing of steps S82 to S92 is repeated.

The processes of steps S82 to S92 are repeated for the number of processes, that is, eight times. In the meantime, the detection signals of the switches input to the 8 bits of the input port 0 are sequentially turned on or off. A check process is performed, and if it is in the ON state, the value of the corresponding switch timer is increased by one.

The CPU 56 executes the switch processing in step S
At 75, the data input to the input port 1 is input. Next, "4" is set as the number of processes (step S76), and the address of the switch timer for the winning ball count switch 301A is set in the pointer (step S77). Then, a switch check processing subroutine is called (step S78).

In the switch check processing subroutine,
Since the above-described processing is executed, steps S82 to S9 are performed.
2 is repeated for the number of processes, that is, four times. During that time, the detection signal of the switch input to the 4 bits of the input port 1 is sequentially checked to determine whether it is on or off. If it is in the ON state, the value of the corresponding switch timer is increased by one.

In this embodiment, since the game control process is started every 2 ms, the switch process is also executed once every 2 ms. Therefore, the switch timer is incremented by 1 every 2 ms.

FIGS. 21 to 23 are flowcharts showing an example of the prize ball processing in step S31 in the game control processing. In this embodiment, in the prize ball process, it is determined whether or not the winning opening switches 19a, 19b, 24a, 24b, the count switch 23, and the starting opening switch 17 have been reliably turned on. Is controlled to be sent to the payout control board 37,
In addition, the full tank switch 48 and the ball out switch 187
Is turned on without fail, and when turned on, processing such as control is performed so that a predetermined payout control command is sent to the payout control board 37.

In the prize ball processing, the CPU 56 sets “0” as an offset of the input determination value table (step S121), and sets “0” as an offset of the address of the switch timer (step S122). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Also,
Since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 14, the offset "0" of the address of the switch timer means that the switch timer corresponding to the winning opening switch 24a is designated. I do. Also, “4” is set as the number of repetitions (step S
123). Then, the switch-on check routine is called (step S124).

The input determination value table is a table in which a determination value is set for each switch to determine how many consecutive ONs have been detected to determine that the switch has been turned ON.
This is the M area. FIG. 26 shows a configuration example of the input determination value table. As shown in FIG. 26, in the input determination value table, “2”, “50”, “250”, “30”,
Determination values of “250” and “1” are set. Also,
In the switch-on check routine, the judgment value set at the address determined by the start address of the input judgment value table and the offset value is compared with the value of the switch timer determined by the start address of the switch timer and the offset value. If so, for example, a switch-on flag is set.

One example of the switch-on check routine is shown in FIG. In the switch-on check routine, the CPU 56 sets the start address of the input determination value table (see FIG. 26) (Step S101).
Then, an offset is added to the address (step S102), and a switch-on determination value is loaded from the address after the addition (step S103).

Next, the CPU 56 sets the start address of the switch timer (step S104), adds an offset to the address (step S105), and loads the value of the switch timer from the address after the addition (step S106). Since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 14, the value of the switch timer corresponding to the switch is loaded.

Then, the CPU 56 compares the value of the loaded switch timer with the switch-on determination value (step S107). If they match, a switch-on flag is set (step 108).

In this case, in the switch-on check routine, if the value of the switch timer corresponding to the winning opening switch 24a matches the switch-on determination value "2", the switch-on flag is set (step S1).
25). When the switch-on flag is set, 10 counters are incremented by 1 (step S126). The switch check-on routine is executed for the initially set number of repetitions while the offset of the address of the switch timer is being updated (step S129) (steps S127 and S128).
For a, 19b, 24a, and 24b, the value of the corresponding switch timer is compared with the switch-on determination value “2”. The ten counter is a counter that indicates the number of ten game ball payouts as prizes.

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S13).
0), “4” is set as the offset of the address of the switch timer (step S131). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 14, the offset “4” of the address of the switch timer indicates that the switch timer corresponding to the starting port switch 17 is designated. Means Then, the switch-on check routine is called (step S1).
32).

In the switch-on check routine,
If the value of the switch timer corresponding to the starting port switch 17 matches the switch-on determination value "2", the switch-on flag is set (step S133), and the six counters are incremented by 1 (step S134). . In addition,
The six counter is a counter that indicates the number of payouts of six game balls as prizes.

Next, the CPU 56 sets "0" as an offset of the input judgment value table (step S13).
5), “5” is set as the offset of the address of the switch timer (step S136). The offset “0” of the input judgment value table means that the first data of the input judgment value table is used. Further, since the switch timers are arranged in the same order as the bit order of the input port shown in FIG. 14, the offset “5” of the address of the switch timer indicates that the switch timer corresponding to the count switch 23 is designated. means. Then, the switch-on check routine is called (step S).
137).

In the switch-on check routine,
If the value of the switch timer corresponding to the count switch 23 matches the switch-on determination value "2", the switch-on flag is set (step S138).
The five counters are incremented by 1 (step S134). The 15 counter is a counter indicating the number of payouts of 15 game balls as prizes.

Further, the CPU 56 sets "1" as an offset of the input judgment value table (step S15).
0), “9” is set as the offset of the address of the switch timer (step S151). The offset “1” in the input judgment value table is equal to 2 in the input judgment value table.
This means that the second data “50” is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 14, the offset “9” of the address of the switch timer indicates that the switch timer corresponding to the full switch 48 is designated. Means Then, the switch-on check routine is called (step S152).

In the switch-on check routine,
If the value of the switch timer corresponding to the full tank switch 48 matches the full tank switch-on determination value "50", the switch-on flag is set (step S15).
3) The full tank flag is set (step S15)
4). Although not explicitly shown in FIG. 22, when the value of the switch timer corresponding to the full tank switch 48 becomes 0, the full tank flag is reset.

The CPU 56 sets “2” as the offset of the input judgment value table (step S15).
6), “0A (H)” is set as the offset of the address of the switch timer (step S157). The offset “2” in the input determination value table means that the third data “250” in the input determination value table is used. Further, since each switch timer is arranged in the same order as the bit order of the input port shown in FIG. 14, the offset “0A (H)” of the address of the switch timer is designated by the switch timer corresponding to the out-of-ball switch 187. Means to be done. Then, the switch-on check routine is called (step S158).

In the switch-on check routine,
If the value of the switch timer corresponding to the out-of-ball switch 187 matches the out-of-ball switch-on determination value "250", the switch-on flag is set (step S1).
59), a ball out flag is set (step S16)
0). Although not explicitly shown in FIG. 22, a switch-off timer corresponding to the out-of-ball switch 187 is prepared, and when its value reaches 50, the out-of-ball flag is reset.

Then, the CPU 56 checks whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command is sent to the payout control board 37. If it is not the payout stop state, it is checked whether the above-mentioned ball out-of-ball state flag or the full tank flag is turned on (step S202).

When either of them changes to the ON state,
A command transmission control process for payout stop state designation is performed (step S203). In the command transmission control process, after predetermined data is set in the command transmission table for the payout control command, a process of transmitting the payout control command is executed. In step S202, when one of the flags is already on, and the other flag is on, the command transmission control process (step S203) is not performed.

If the payout is stopped, it is checked whether both the out-of-ball state flag and the full state flag have been turned off (step S204). When both are turned off, a command transmission control process for payout stop release designation is performed (step S205).

Next, the CPU 56 sets a payout control command relating to the number of winning balls according to the winning in the command transmission table, and performs control to transmit a payout control command according to the set content. First, the values of the 15 counters are checked (step S221). As described above, the fifteen counters are counted up when the game ball wins the big winning opening and the count switch 23 is turned on. If the value of the fifteen counters is not 0, a command transmission control process for the fifteen winning ball number instructions is performed (step S22).
2). In the command transmission control process, after predetermined data is set in the command transmission table for the payout control command, a process of transmitting the payout control command is executed. Also,
The value of the 15 counters is decremented by one (step S223).
Further, 15 is added to the value stored in the total prize ball storage buffer (step S224).

The total prize ball number storage buffer is a buffer for storing the cumulative value of the prize ball numbers instructed to the payout control means (however, it is decremented when the payout is made).
It is formed in the backup RAM.

If the value of the 15 counter is 0, the value of the 10 counter is checked (step S225). As described above, the ten counters indicate that the gaming ball has won the winning opening and the winning opening switches 19a, 19b, 24a, 24b
Counts up when turns on. If the value of the ten counter is not 0, a command transmission control process for the ten winning ball number instructions is performed (step S226). Further, the value of the ten counters is decremented by one (step S22).
7). Further, 10 is added to the value stored in the total prize ball storage buffer (step S228).

If the value of the ten counter is 0, the value of the six counter is checked (step S231). As described above, the six counters are counted up when the game ball wins the starting winning port and the starting port switch 17 is turned on. If the value of the six counter is not 0, a command transmission control process relating to an instruction for the number of six winning balls is performed (step S232). Further, the value of the six counters is decremented by one (step S233). Further, 6 is added to the value stored in the total prize ball storage buffer (step S234).

As described above, when the payout control command for instructing the number of winning balls from the game control means to the payout control board 37 is to be output, the command transmission table is set, and then the command transmission table is set. The set payout control command is sent to the payout control board 37. Then, when the payout control command indicating the number of winning balls is transmitted, the awarding ball paying flag is turned on (step S235). When the award ball paying flag is on (step S236), the number of award balls actually paid out from the ball payout device 97 is monitored and the value stored in the total award ball number storage buffer is subtracted. A number subtraction process is performed (step S237). When the award ball payout flag changes from on to off, the lamp control board 35
A lamp control command instructing lighting of the prize ball lamp 51 is transmitted.

FIG. 25 is a flowchart showing an example of the winning ball number subtraction processing. In the prize ball number subtraction process, C
The PU 56 first loads the value stored in the total prize balls storage buffer (step S241). Then, it is determined whether or not the stored value is 0 (step S242). If it is 0, the process ends.

If it is not 0, the switch timer for the prize ball count switch is loaded (step S243), and the loaded value is compared with the ON determination value (in this case, "2") (step S244). If they match (step S24
5) Assuming that the prize ball count switch 301A has certainly turned on, that is, one game ball has surely
7 is subtracted from the value stored in the total prize ball storage buffer (step S246).

Further, the value of the award ball information counter is incremented by 1 (step S247). If the value of the prize ball information counter is 10 or more (step S248), the value of the prize ball information output counter is incremented by 1 (step S24).
9), the value of the prize ball information counter is reduced by -10 (step S)
250). The value of the prize ball information output counter is as shown in FIG.
Is referred to in the information output process (step S29) in the main process shown in (1), and if the value is 1 or more, one pulse is output as a prize ball signal (bit 7 of output port 5: see FIG. 13). Therefore, in this embodiment, 10
Each time one gaming ball is paid out as a prize ball, one prize ball signal is output outside the gaming machine.

When the value stored in the total prize ball storage buffer becomes 0 (step S251), the payout ball payout flag is cleared (step S252), and in order to notify that there is no remaining prize ball count, After setting command data indicating turning off of the prize ball lamp 51 in the command transmission table for the lamp control command (step S253), a lamp control command transmission process is executed (step S254).

FIGS. 27 to 29 are flowcharts showing an example of a non-maskable interrupt process (power supply stop process) executed in response to a power-off signal from the power supply board 910.

In the power supply stop processing, the CPU 56
Saves the AF register (accumulator and flag register) in a predetermined backup RAM area (step S451). Further, the interrupt flag is copied to the parity flag (step S452). The parity flag is formed in the backup RAM area. Further, the BC register, the DE register, the HL register, the IX register, and the stack pointer are saved in the backup RAM area (Steps S454 to S458). When the power is restored, the register contents are restored on the basis of the saved contents, and the interrupt permission state / prohibition state is internally set according to the contents of the parity flag.

Next, in this embodiment, for a predetermined period,
The detection signal of the winning ball count switch 301A is checked. When the award ball count switch 301A is turned on, the content of the total award ball number buffer is reduced by one.

In this embodiment, a counter for measuring a predetermined period is used to measure a predetermined period.
The value of the counter for the predetermined period measurement is decremented from the initial value m by one every time a loop of the switch detection process described below (a loop starting from S461 and returning to S461) is executed once.
When the value becomes 0, it is assumed that the predetermined period has ended. In the detection processing loop, although there is an exception, almost constant processing is performed. Therefore, a time that is m times the time required for one round of the loop substantially corresponds to a predetermined period.

For measuring the predetermined period, a built-in timer of CPU 56 may be used. That is, at the start of the switch detection process, a predetermined value (corresponding to a predetermined period) is set in the built-in timer. Then, the loop of the switch detection processing is 1
Each time it is executed, the count value of the built-in timer is checked. Then, when the count value becomes 0, it is assumed that the predetermined period has ended. Although an interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0, at this stage, the control is performed so as not to change the control contents (each value stored in the RAM). It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program.

During a predetermined period, the game ball is dropped from the ball payout device 97, and the prize ball count switch 30
The time is set to be equal to or longer than the time required to reach 1A. Assuming that the distance from the ball dispensing device 97 to the prize ball count switch 301A is L, the falling time t during that time is t = √ (2L /
g) (g: gravitational acceleration), so the predetermined period is set longer.

At least during a predetermined period during which the switch detection process is executed, the prize ball count switch 301A must be in a state capable of detecting a game ball. Therefore, in this embodiment, as shown in FIG.
A capacitor 923 as an auxiliary driving power source having a relatively large capacity is connected to the input side of the converter IC 922 in FIG. Therefore, even when the power supply to the gaming machine is stopped, the +12 V power supply voltage is maintained within the range in which the switch can be driven for a certain period, and the prize ball count switch 301A
Becomes operable. The capacity of the capacitor is determined so that the period is equal to or longer than the predetermined period.

Since the input port and the CPU 56 are also driven by the +5 V power supply created by the converter IC 922, they can operate for a relatively long time even when the power supply is stopped.

In step S461, an initial value n corresponding to a time of 2 ms is set in the 2 ms measurement counter. Then, until the value of the 2 ms measurement counter becomes 0 (step S462), the value of the 2 ms measurement counter becomes −
1 (step S463).

When the value of the 2 ms measurement counter becomes 0,
The input check of the detection signal of the winning ball count switch 301A is performed. That is, processing similar to the switch processing and switch check processing shown in FIGS. 19 and 20 is performed. Specifically, the data input to the input port 1 is input (step S464). Next, clear data (00) is set (step S4).
65). Also, the port input data, in this case, the input data from the input port 1 is set as the “comparison value” (step S466). Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S467).

Then, the switch timer pointed to by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S469). ). The data of the input port 1 is set as the comparison value. Then, in this case, the detection signal of the winning ball count switch 301A is pushed out by the carry flag.

If the value of the carry flag is "1" (step S470), that is, the award ball count switch 30
If the 1A detection signal is on, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is "0", that is, if the detection signal of the winning ball count switch 301A is in an off state, clear data is set in the switch timer (step S472).
That is, if the switch is off, the value of the switch timer returns to zero.

When the value of the switch timer becomes 2 (step S473), the value stored in the total prize ball storage buffer is decremented by 1 (step S474), and the value of the prize ball information counter is incremented by 1 (step S474). Step S475).
If the value of the award ball information counter is 10 or more (step S476), the value of the award ball information output counter is incremented by 1 (step S477), and the value of the award ball information counter is decreased by 10 (step S478).

Next, the value of the counter for measuring a predetermined period is
1 (step S479), and if the value is not 0, the process returns to step S461.

By the above processing, when the winning ball count switch 301A is turned on within a predetermined period, the value of the total winning ball storage buffer is decremented by one. Since the process for storing the contents of the backup RAM is performed after such a switch detection process, the total prize ball number storage buffer is always decremented by one for the prize balls that have been paid out. Therefore, it is possible to prevent inconsistency in the stored control state regarding the payout of the game balls. In the above switch detection processing, timer processing using a detection period counter is performed. That is, the prize ball count switch 30 is set every 2 ms.
The detection output of 1A is checked, and when the ON is detected twice consecutively, it is considered that the winning ball count switch 301A is surely turned ON. Therefore, erroneous switch-on detection is prevented. Also, in the switch detection processing, the calculation of the prize ball information output frequency counter for outputting the prize ball information to the outside of the gaming machine is also performed.
There is no discrepancy between the prize ball information output to the outside and the actual number of payout prize balls.

In this embodiment, the switch detection processing of only the prize ball count switch 301A is performed. However, the same applies to the start prize port switch and the V prize switch 22 and the count switch related to the large prize port. Switch detection processing may be performed. The same switch detection processing may be performed for other winnings. When such an on-check is also performed, even if a power failure occurs immediately after a game ball has won a winning hole, the winning is reliably detected and reflected in the saved game state.

When the predetermined period has elapsed (step S48)
0), that is, when the value of the counter for measurement for a predetermined period becomes 0, the designated value with backup (“55” in this example)
H ”) is stored in the backup flag (step S).
481). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S482 to S491). That is, first,
The clear data (00) is set in the checksum data area (step S482), and the checksum calculation start address is set in the pointer (step S483).
Also, the number of checksum calculations is set (step S
484).

Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S485). The calculation result is stored in the checksum data area (step S48).
6) Increase the value of the pointer by 1 (step S487),
The value of the number of checksum calculations is subtracted by 1 (step S4)
88). The processing of steps S485 to S488 is repeated until the value of the number of checksum calculation times becomes 0 (step S489).

When the value of the number of times of checksum calculation becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area (step S490). Then, the inverted data is stored in the checksum data area (step S491). This data is the parity data that is checked when the power is turned on. Then, R
An access prohibition value is set in the AM access register (step S492). Thereafter, the internal RAM 55 cannot be accessed.

Further, the CPU 56 sets the clear data (0
0) is set in an appropriate register (step S49).
3) The number of processes ("7" in this example) is set in another register (step S494). Further, the address of the output port 0 is set in the IO pointer (step S49).
5). Yet another register is used as the IO pointer.

Then, clear data is set at the address pointed to by the IO pointer (step S49).
6), increment the value of the IO pointer by 1 (step S49)
7), the value of the number of processes is subtracted by 1 (step S498).
If the value of the number of processes is 0
Repeat until. As a result, clear data is set to all output ports 0 to 6 (see FIGS. 12 and 13). As shown in FIGS. 12 and 13, in this example, “1” is in the ON state, and “0” which is the clear data is set.
Since "0" is set to each output port, all output ports are turned off.

Therefore, after the processing for saving the game state (in this example, generation of the checksum and prevention of RAM access), each output port is immediately turned off. In this embodiment, the RAM area in which data used in the game control process is stored is all backed up by power. Therefore, a process of generating a checksum indicating whether or not the content is correctly stored, and an R for preventing the content from being rewritten.
The AM access prevention process corresponds to a process for saving a gaming state.

Since each output port is immediately turned off after the processing for storing the game state is executed, it is possible to reliably prevent a situation in which the game state does not match the stored game state. When the processing shown in FIGS. 27 to 29 is executed, the supply of power to the gaming machine is stopped, so that the voltage applied to the electric components decreases. Then, when the applied voltage falls below the drivable voltage, the driving of the electric component is stopped. Therefore, when the power supply to the gaming machine is stopped, the driving of the electric components is stopped although there is a short delay.

However, if the clearing process for the output port as in this embodiment is not performed, after the game state is saved, the variable prize ball device while the game control means waits for the power supply to stop. In some cases, a further prize may be won. In such a case, when the power supply is resumed, the saved game state is restored, so the start winning storage number at the time of saving is displayed on the start storage display 18. Then, from the player's point of view, the stored value of the start winning prize may be reduced, and a trouble may occur.
However, in this embodiment, there is no possibility that such a trouble occurs. Further, in the case where the power supply stop processing is executed with the control for opening the special winning opening immediately before the occurrence of the power failure or the like, the power supply stop processing is executed, and the apparatus enters a standby loop, and then returns without stopping the power supply. In the embodiment, the phenomenon that the game control is in the standby loop but the special winning opening is kept open is prevented from occurring. In addition, it is possible to prevent a phenomenon that the variable display is started during the standby loop.

Further, after the game state is saved, a prize may be generated in the big prize hole as the variable prize ball device. In such a case, the winning number recognized by the player may be different from the winning number displayed on the display unit based on the saved game state when the power supply is restored, and a trouble may occur. However, in this embodiment, there is no possibility that such a trouble occurs.

When the clear processing for the output port is completed, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the power supply stop processing is executed in response to the NMI.
It may be connected to the maskable terminal of the PU 56 to execute the power supply stop processing by the maskable interrupt processing. Alternatively, the power-off signal may be input to the input port, and the power supply stop processing may be executed according to the check result of the input port.

In this embodiment, the register saving processing is performed at the beginning of the processing started in response to the power-off signal. However, when the register is not used in the switch detection processing, the register detection processing is performed. After execution, that is, before register backup processing and checksum calculation processing, register storage processing can be performed. In this case, the register saving processing, the backup flag setting processing, the checksum calculation processing, and the output port off setting processing can be regarded as the power supply stop processing. Furthermore, even when some registers are used in the switch detection processing, register saving processing can be performed on unused registers before setting the backup flag and calculating the checksum.

Note that the output port clearing process may be performed before the execution of the switch detection process (before step S460). During execution of the power supply stop processing, the CPU 56
The switches and the like are driven by the charging power of the capacitor. If the clearing process of the output port is performed before the execution of the switch detecting process, even if the special winning opening or the variable winning device is configured to be driven by an electric component such as a solenoid, they are driven. Therefore, the charging power of the capacitor and the like can be effectively used for the process when the power supply is stopped.

However, when the V winning switch 22 is detected after the power-off is detected, the output port of the solenoid 21 (for operating a member for guiding the large winning opening to the V winning switch) is operated. Is cleared after execution of the switch detection processing. In such a case, when a power failure occurs in a state where the V prize, which is a condition for the continuation right, is not performed, the game ball that has entered the special winning opening immediately before the power failure occurs is guided to the V prize switch 22 side. Can be. Therefore, it is possible to prevent the irrelevant continuation right from disappearing. In this case, the predetermined period is a period of time equal to or longer than the time required for the game ball that has won the big winning opening to reach the V winning switch 22. When a latch-type solenoid is used, the output port clearing process is not required.

Further, even if the special winning opening is closed by clearing the output port, there may be a game ball in the special winning opening. Therefore, in the switch detection processing executed in response to the power-off signal, the count switch 23 is used. It is desirable to also perform detection. The output port clearing process may be performed before the switch detection process, and the exceptional process is performed not only in the first-type pachinko gaming machine but also in the second-type pachinko gaming machine or the third-type pachinko gaming machine. The same applies to pachinko game machines.

FIG. 30 is a flow chart showing a part of the non-maskable interrupt processing (power supply stop processing) of the game control means according to another embodiment of the present invention. The flowchart shown in FIG. 30 is executed following the processing of steps S451 to S492 shown in FIGS. That is, in this embodiment, after the RAM access is prohibited (step S492), the head address of the clear data table is set in the pointer (step S501), and after the data clear processing is executed (step S501). S502), and enters a standby state waiting for a system reset. A predetermined register is used as a pointer.

FIG. 31 is an explanatory diagram showing an example of the configuration of the clear data table. In the example shown in FIG. 31, in the clear data table, the processing number data (“7” in this example), the address of the output port 0, the clear data to be set to the output port 0,. 6, the clear data to be set in the output port 6 is set. The output port address and the clear data are set in ascending order of the output port address.

FIG. 32 is a flowchart showing the data clear processing in step S502. In the data clear processing, the CPU 56 extracts the processing number data from the address indicated by the pointer (step S511). Then, the value of the pointer is incremented by 1 (step S512). Next, address data (address of the output port) is extracted from the address indicated by the pointer (step S51).
3). Further, the value of the pointer is increased by 1 (step S5).
14).

Then, clear data is extracted from the address indicated by the pointer (step S515), and the data is set to the address extracted in step S83 (step S516). Next, the value of the number of processes is decremented by 1 (step S517), and when the number of processes becomes 0, the data clearing process ends (step S518). If the number of processes is not 0, the process returns to step S511.

Even if the clear data table is used, the clear signal output process can be performed quickly, and the occurrence of inconsistency between the control state saved when the power supply to the gaming machine is stopped and the actual control state can be reduced. It can be effectively prevented. When the clear data table is used, the address data and the clear data do not have to be arranged in the order of addresses in the table, and the degree of freedom of the table configuration is increased.
For example, when it is desired not to clear the test signal in a gaming machine using the test signal or the like, by clearing the data relating to the output port related to the test signal from the table, the clearing process of the test signal can be easily omitted. Further, when there is an increase or decrease or a change in the output port, only the contents of the table need be changed, and there is no need to change the program.

FIG. 33 is a timing chart showing an example of how the input processing of the detection signal from the payout detecting means is executed. In this embodiment, the power-off signal is transmitted to the main board 31.
Is input to the payout control board 37 and the CP of the main board 31
It is input to U56 and the NMI terminal of the payout control CPU 371. The CPU 56 of the main board 31 executes the above-described power supply stop processing by the non-maskable interrupt processing.

As shown in FIG. 33, when a prize ball is paid out when the power-off signal is turned on (in this example, changed from a high level to a low level), the detection signal input processing from the payout detecting means is performed. The prize ball count switch 301A is turned on within a predetermined period to be executed. Therefore, the ball payout executed when the power-off signal is turned on can be reflected in the total winning ball count buffer when the power supply stop processing is executed.

When the voltage value of VSL further decreases to a predetermined value (+9 V in this example), the output of the reset IC 651 mounted on the main board 31 goes low as shown in FIG. The CPU 56 enters a system reset state. Note that the CPU 56 has completed the power supply stop processing before the system is reset.

When the voltage value of VSL further decreases and falls below a voltage capable of generating Vcc (+5 V for driving various circuits), each circuit cannot operate on each substrate. However, in the main board 31, the power supply stop processing is executed, and the CPU 56 is in a system reset state.

As described later, the payout control board 37
Similarly, the payout control CPU 371 enters the system reset state after performing the power supply stop processing.

The pachinko gaming machine 1 of the above embodiment is
The first-type pachinko gaming machine, in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a combination of a predetermined symbol, A third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize in a predetermined electric accessory which is opened when a stop symbol of a symbol variably displayed based on a start winning prize is a predetermined combination of symbols. Even so, the present invention can be applied.

FIG. 34 is an explanatory diagram showing an example of the game area 7 of the third type pachinko gaming machine. In this example, when there is a winning in the starting winning port 30A, the variable display section 9 starts variable display of symbols. When the stop symbol of the symbol is a predetermined symbol combination, the right-generating electric accessory 30
B is opened for a predetermined period to be in a state where it is easy to win. In this state, when a right is generated by winning the right-generating electric accessory 30B, a game ball entering the rotor 30C driven by a motor or the like is guided to the starting port switch of the large winning port 30D,
When the start port switch is detected, the special winning port 30D is opened. Each switch is provided for detecting a game ball which has won the starting winning port 30A, the right-generating electric accessory 30B, the rotor 30C, and the special winning port 30D.

In such a type 3 pachinko gaming machine, even when the control state is stored in response to the occurrence of a power failure or the like, the processing is started, for example, in response to a power-off signal. Rotor 30C by port clear processing
Stop the motor and the like for driving the motor. And the rotor 30C
The game ball guided to the starting port switch (the switch for detecting the game ball entering the rotor 30C) is subjected to the switch detection process for a predetermined period even after the power-off is detected. Can be detected. Therefore, when the power is restored, it is guaranteed that the operating condition of the special winning opening 30D is satisfied. In this case, the predetermined period is a period of time equal to or longer than the time required for the game ball to move from the portion of the rotor 30C that holds the game ball to the starting port switch. Further, the switch provided on the right-generating electric accessory 30B is also subjected to the detection processing for a predetermined period even after the power-off is detected, thereby preventing the right from being unduly erased. .

When all the switches are detected in the switch detection process in the process started in response to the generation of the power-off signal, the switch process shown in FIG. 19 is called during a predetermined period. You may. Then, in the case of such a configuration, the processing when the switch timer value reaches the ON determination value is also performed. For example, when the switch timer value of the winning ball switch reaches the ON determination value, a process for setting the number of winning balls is performed (increment of 15 counters, etc.), or the switch timer value of the V winning switch 22 becomes the ON determination value. Upon reaching, a process such as setting a flag indicating that there is a V winning is performed.

[0212] Hereinafter, the game state restoration processing will be described. FIG. 35 is a flowchart showing an example of the gaming state restoring process shown in step S10 of FIG. In this example, the CPU 56 restores the value stored in the backup RAM to each register (Step S91).
Then, based on the data stored in the backup RAM, the game state at the time of the power failure is confirmed and restored. That is, based on the data stored in the backup RAM, the solenoid 1
6 and the solenoid 21 are driven to restore the open state of the start winning port 14 and the opening / closing plate 20 (steps S92 and S9).
3). In addition, according to the value of the special symbol process flag and the normal symbol process flag that have been saved even during the power-off, the control command corresponding to the progress status of the special symbol process process and the normal symbol process process at the time of power-off, The information is sent to the symbol control board 80, the lamp control board 35, and the voice control board 70 (step S94).

As described above, in the game state restoring process, the state of various electric components is restored according to the restored internal state, and the symbol control board 80, the lamp control board 35, and the voice control board 70 are restored. Then, a control command for returning the control state to the power-off state (a control command for generating the control state at the time of power-off) is transmitted.
Such a control command is generally one or more control commands that were last sent out before power down.

When the game state is returned to the state at the time of power-off, in this embodiment, the CPU 56 restores the interrupt permission / prohibition state at the time of the previous power-off to restore the parity stored in the backup RAM. The value of the flag is confirmed (step S95). If the parity flag is off, interrupt permission setting is performed (step S96). However, if the parity flag is in the on state, the game state restoring process is terminated as it is (with the interrupt prohibition state set in step S1). The on state of the parity flag means that the interrupt was disabled at the time of the previous power-off, as shown in step S452 in FIG. Therefore, when the parity flag is in the ON state, the interruption is not permitted.

In this embodiment, the following state restoration can be performed by the above-described game state restoration processing.

The start winning opening 14 and the big winning opening (opening and closing plate 2)
The state of 0) is restored. Display state of normal symbols controlled by display control means (display state of variable display 10)
Is restored except when it is changing when the power is turned off. The display state of the special symbol controlled by the display control means (the display state of the variable display unit 9) is restored except for the case where it is changing when the power is turned off. Further, the variable display unit 9
Are restored except during the special symbol change and during the big hit game.

When the power is turned off during the change of the special symbol, information on the change time (for example, 10 seconds) of the variable display pattern and the time already executed (for example, 4 seconds) are backed up. Then, at the time of restoration, the main board 31 outputs a display control command indicating a display pattern and a display control command indicating a stop symbol to the display control board 80, and stops the symbol after a lapse of the remaining time (6 seconds in the above example). Output a display control command to cause Therefore, when the special symbol is changing when the power is turned off, the display state of the special symbol is variably displayed for the remaining time (6 seconds in the above example) not displayed at the time of restoration. The display control command indicating the display pattern output to the display control board 80 at the time of restoration may be the same as the display control command indicating the display pattern output before the power is turned off. It is good also as a command for displaying an image like "in the middle." In this case, the display "recovering from power failure" is displayed for the remaining time (6 seconds in the above example). The same control as described above is performed for the display state of the ordinary symbol when the power is turned off during the change of the special symbol.

When the power is cut off during the big hit game, the remaining time of the round or the interval between the rounds is restored when the power is cut off during the change of the special symbol as described above. , Display, sound, lamp,
While controlling the solenoid 21 and the like, the main board 31 outputs a display control command to the display control board 80 for designating a symbol at the time of confirmation (stop symbol) output before the power is turned off.
Thereby, the effect by the big hit symbol during the round or between the rounds becomes possible (for the model that performs the big hit with the big hit symbol), and the display control board 80 can also recognize the symbol displayed at the start of the change after the big hit end. .

Decoration lamp 2 controlled by lamp control means
5, start memory display 18, gate passage memory display 41,
The display states of the award ball lamp 51 and the ball out lamp 52 are restored. Game effect lamps / LEDs 28a, 28b, 2
The display state of 8c is restored except when the special symbol is being changed and the big hit is being played. However, if a big hit is being played when the power is turned off, the initial state of each control section can be restored. The control sections are, for example, a jackpot start notification state, a state before the opening of the special winning opening, a state during opening of the special winning opening, and a notification state of the big hit end. When the power is turned off during the change of the special symbol and the power is turned off, the game effect lamps / LEDs 28a, 28b, and 2 are provided for the remaining time, similarly to the display control of the variable display unit 9 and the variable display device 10 described above.
Although the display state of 8c may be controlled, it may be turned off or turned on or off in a pattern specific to turning off or restoring the power failure.

[0220] The sound generation state controlled by the voice control means is restored except when a special symbol is being changed or a big hit is being played. However, if a big hit is being played when the power is turned off, the initial state of each control section can be restored.
When the power is turned off during the special symbol change and the power is restored, the sound generation state is controlled for the remaining time in the same manner as the display control of the variable display unit 9 and the variable display device 10 described above. Alternatively, a sound pattern specific to silence or power recovery from a power failure (for example, a voice saying “power recovery is in progress”) may be output.

In this embodiment, at the time of restoration from power-off, a control command for restoring a state is sent from the game control means of the main board 31 to the display control means, the lamp control means and the voice control means. However, when the display control means, the lamp control means, and the sound control means are backed up by a power source, the display control means, the lamp control means, and the sound control means independently control without using a control command from the main board 31. The state may be restored.

As will be described later, the payout control board 37
The payout control means mounted on the power supply is backed up by a power supply, so that upon recovery from a power failure, the prize ball payout state and the ball lending control state are changed to the state at the time of the power failure (for a predetermined time after the voltage drop is detected). To the state after elapse of). In this embodiment, since the firing control board is connected to the payout control means, the control state of the firing control board 91 is similarly restored.

In the above embodiment, a case has been described in which the game control means performs the data storage processing and the recovery processing. However, the payout control means, the voice control means, the ramp control means, and the RAM in the display control means have been described.
May be backed up by a power source, and the payout control unit, the display control unit, the sound control unit, and the lamp control unit may also perform the above-described processing. However, the payout control means, the display control means, the sound control means, and the lamp control means do not need to perform the command transmission processing at the time of restoration.

Next, as an example of the case where the data storage processing and the restoration processing are performed in the electric component control means other than the game control means, the case where the data storage and the recovery are performed in the payout control means will be described.

FIG. 36 is a block diagram showing an example of a configuration around the payout control CPU 371. As shown in FIG. 36, the power-off signal from the power supply monitoring circuit (power supply monitoring means) of the power supply board 910 is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960. I have. Therefore, the payout control CPU 37
No. 1 can confirm the occurrence of power interruption by non-maskable interrupt processing.

CLK / TRG of payout control CPU 371
The INT signal from the main board 31 is connected to the two terminals. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 incorporated in the payout control CPU 371 is counted down. When the register value becomes 0, an interrupt occurs. Therefore, the timer counter register CLK / TRG
If the initial value of 2 is set to "1", an interrupt occurs in response to the input of the INT signal.

The payout control board 37 is also provided with a system reset circuit 975. In this embodiment,
Reset IC 97 in system reset circuit 975
Reference numeral 6 indicates that when the power is turned on, the output is set to the low level for a predetermined time determined by the capacity of the external capacitor, and the output is set to the high level after the predetermined time has elapsed. Also, reset IC 9
The monitor 76 monitors the power supply voltage of VSL, and sets the output to a low level when the voltage value falls below a predetermined value (for example, +9 V). Therefore, when the power is turned off, the signal from the reset IC 976 goes to a low level, so that the payout control CPU 371
Is reset.

Although the predetermined value for the reset IC 976 to detect the power-off is lower than the normal voltage, the payout control C
This is a voltage at which the PU 371 can operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage (+5 V in this example) required by the payout control CPU 371, the payout control CPU 371
The monitoring range can be extended for the voltage required by the 371. Therefore, more precise monitoring can be performed.

While power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supply supplied from the power supply board to the backup terminal. The contents are saved even if the power is turned off. Then, when the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to the normal operation state. At that time, since the necessary data has been backed up,
Upon recovery from a power failure or the like, it is possible to return to the payout control state at the time of the power failure.

As shown in FIG. 36, the output signal of the clear switch 921 mounted on the switch board 190 is input via the buffer circuit 372A for inverting the logic and the input port 372. In this example, the output signals of the prize ball count switch 301A and the ball lending count switch 301B are also input to the input port 372 via the buffer circuit 372A. According to such a configuration, the clear switch 92
If the output signal is a clear switch signal (low level signal) by switching 1, the clear switch signal is inverted (the signal output by the buffer circuit 372A after inverting the clear switch signal is called a clear switch signal). Is given to the payout control CPU 371, so that the payout control CPU 371 performs an initialization process described later.

In the configuration shown in FIG. 36, when power is turned on, system reset circuit 975 outputs a low level for a period determined by the capacity of the capacitor, and then outputs a high level. That is, the reset release timing is only once. However, the main substrate 31 shown in FIG.
As in the case of the above, a circuit configuration that generates a plurality of reset release timings may be used.

FIG. 37 is an explanatory diagram showing the assignment of output ports in this embodiment. As shown in FIG. 37, the output port C (address 00H) is
The output port of the drive signal output to 89. Also,
Output port D (address 01H) is 7 segment LE
This is an output port of a display control signal output to the error display LED 374 which is D. The output port E (address 02H) is an output port for outputting a drive signal output to the distribution solenoid 310 and an EXS signal and a PRDY signal to the card unit 50.

FIG. 38 is an explanatory diagram showing bit assignment of an input port in this embodiment. As shown in FIG. 38, the input port A (address 06H) is an input port for receiving an 8-bit payout control signal of the payout control command sent from the main board 31. Further, detection signals of the prize ball count switch 301A, the ball lending count switch 301B, and the motor position sensor are input to bits 0 to 2 of the input port B (address 07H), respectively. In bits 3 to 5, the BRDY signal, the BRQ signal, and the VL signal from the card unit 50 are input. The output signal of the clear switch 921 is input to bit 6.

FIG. 39 is a flowchart showing the main processing of the payout control CPU 371. In the main processing,
The payout control CPU 371 first makes necessary initial settings. That is, the payout control CPU 371 first sets interrupt prohibition (step S701). Next, the interrupt mode is set to the interrupt mode 2 (step S702), and a stack pointer designated address is set to the stack pointer (step S703). The payout control CPU 37
1 initializes a built-in device register (step S704), and initializes CTC and PIO (step S704).
After performing step 705), the RAM is set in an accessible state (step S706).

In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore,
In the internal device register setting process in step S704 and the process in step S705, a register setting for setting a channel to be used to the timer mode, a register setting for permitting interrupt generation, and a register for setting an interrupt vector The settings are made. Then, the interruption by the channel is used as a timer interruption. When it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

The interrupt vector set for the channel set in the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt processing. Specifically, the start address of the timer interrupt processing is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, the timer interrupt flag is set, and when it is detected in the main process that the timer interrupt flag is set, the payout control process is executed. That is, in the timer interrupt process, a setting for executing the payout control process, which is an example of the electrical component control process, is performed.

Another one of the built-in CTCs (channel 2 in this embodiment) is used as an interrupt generation channel for receiving a payout control command from the game control means. Is used in the counter mode. Therefore, in the setting processing of the internal device register in step S704 and the processing in step S705, the register setting for setting the channel to be used to the counter mode, the register setting for permitting the interrupt generation, and the interrupt vector setting are performed. Is set.

The interrupt vector set in the channel (channel 2) set in the counter mode corresponds to the start address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt processing is specified by the value set in the I register and the interrupt vector.

In this embodiment, the payout control CPU 3
At 71, the interrupt mode 2 is set. Therefore, the built-in CT
An interrupt process based on the count-up of C can be used. Further, it is possible to set an interrupt processing start address according to the interrupt vector transmitted by the CTC.

The interrupt based on the count up of the channel 2 (CH2) of the CTC is an interrupt generated when the value of the timer counter register CLK / TRG2 becomes "0". Therefore, for example, in step S705, the timer counter register C as a specific register
The initial value “1” is set in LK / TRG2. Also, C
The interruption based on the count-up of the channel 3 (CH3) of the TC is based on the internal clock (system clock) of the CPU.
Is counted down and the register value becomes "0", and is used as a 2 ms timer interrupt described later. Specifically, the register value of CH3 is subtracted in 1/256 cycle of the system clock. Step S7
At 05, the register of CH3 contains 2 as an initial value.
A value corresponding to ms is set.

An interrupt based on the count-up of CH2 of the CTC has a higher priority than an interrupt based on the count-up of CH3. Therefore, when the count-up occurs at the same time, an interrupt based on the count-up of CH2,
That is, the interrupt that triggers the execution of the command reception interrupt process has priority.

Next, the payout control CPU 371 outputs the clear switch 921 input through the input port 372.
In this example, the state of the output signal is checked once for a predetermined period (for example, 0.001 second) (step S707). When the clear switch 921 is on (the state in which the clear switch 921 is pressed), a low-level clear switch signal is output. Therefore, when the clear switch 921 is turned on, the payout control CPU 371 executes a normal initialization process (step S71).
1 to step S713). The configuration may be such that the CPU 56 checks the state of the output signal of the clear switch 921 twice or more.

If the clear switch 921 is not on (ie, if the clear switch 921 is not pressed), the payout control CPU 371 determines that backup data exists in the payout control backup RAM area. It is confirmed whether or not there is (Step S70)
8). That is, for example, similarly to the processing of the CPU 56 of the main board 31, it is determined whether or not backup data exists by determining whether or not a backup flag that is set when the power is turned off is in a set state. If the backup flag is set, it is determined that there is backup data.

After confirming that there is a backup, the payout control CPU 371 checks the data in the backup RAM area (parity check in this example). If the power is restored after an unexpected power failure, the backup R
Since the data in the AM area should have been saved, the check result becomes normal. If the check result is not normal, since the internal state cannot be returned to the state at the time of power-off, the initialization processing executed at the time of power-on without power recovery is executed.

If the check result is normal (step S
709), the payout control CPU 371 performs a payout state restoring process for returning the internal state to the state at the time of power-off (step S710). Then, the process returns to the address indicated by the PC (program counter) stored in the backup RAM area.

As described above, it is determined whether or not the game is restored to the game state at the time of power-off according to the operation state of the clear switch 921. At this time, if the clear switch 921 is on, the game state is determined. Since the recovery processing is not executed and the normal initialization processing is executed, the game clerk or the like can use the clear switch 921 when the power supply of the gaming machine is resumed.
By operating, it is possible to select whether or not to execute the game state restoration process based on the backup data stored in the backup data storage area (variable data storage means). Therefore, there is provided a gaming machine which can prevent a disadvantage from being brought to a player even if a power failure occurs, and can also improve convenience in operating a gaming machine in a gaming arcade.

[0247] When power is turned on, initialization processing is executed when backup data is not stored in the variable data storage means, and the clear switch 921 is turned off even when backup data is stored in the variable data storage means. The initialization process executed in the case of (1) is also used in the program. Therefore, even if control for improving the operational convenience at the game store is added, the program capacity does not increase so much.

In the initialization processing, the payout control CPU 371
Performs RAM clear processing first (step S71).
1). A CTC provided in the payout control CPU 371 so that a timer interrupt is periodically performed every 2 ms.
Are set (step S712). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited in step S701 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S713).

In this embodiment, the payout control CPU 3
The built-in CTC 71 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2
ms. And when a timer interrupt occurs,
As shown in FIG. 40, the payout control CPU 371 sets, for example, a timer interrupt flag indicating that a timer interrupt has occurred (step S721). Although it is clearly shown in FIG. 40 that the interruption is permitted (step S72).
0) In the 2 ms timer interrupt processing, the interrupt is first set to the permission state. That is, since the interrupt is permitted during the 2 ms timer interrupt process, the payout control command receiving process based on the input of the INT signal can be preferentially executed.

The payout control CPU 371 determines in step S7
At 24, when it is detected that the timer interrupt flag has been set, the payout control process from step S751 is executed. According to the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt processing, and the payout control processing is executed in the main processing. However, the payout control processing may be executed in the timer interrupt processing.

In the payout control processing, the payout control CPU
371 is the input port 37 via the relay board 72 first.
It is determined whether or not the prize ball count switch 301A and ball lending count switch 301B input to 2b are turned on (switch processing: step S751).

Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor for detecting the number of revolutions of the payout motor 289) to determine the state of the sensor (for example). Input determination processing: Step S752). The payout control CPU 371 further analyzes the received payout control command and executes processing according to the analysis result (command analysis execution processing: step S75).
3).

Next, the payout control CPU 371 sets the payout stop state if the payout stop instruction command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). ).
Further, a prepaid card unit control process is performed (step S755).

Next, the payout control CPU 371 performs control of paying out a lent ball in response to a ball lending request (step S756). At this time, the payout control CPU 371 sets the ball distribution member 311 to the ball lending side by the distribution solenoid 310.

Furthermore, the payout control CPU 371 performs a prize ball control process of paying out the prize balls of the number stored in the total number storage (step S757). At this time, the payout control CPU 371 sets the ball distribution member 311 to the winning ball side by the distribution solenoid 310. And output port 3
A drive signal is output to the payout motor 289 in the payout mechanism of the ball payout device 97 via the relay board 72c and the relay board 72, and a payout motor control process for rotating the payout motor 289 by a predetermined number of revolutions is performed (step S758). .

In this embodiment, the delivery motor 2
A stepping motor is used as 89, and a 1-2 phase excitation method is used to control them. Therefore,
Specifically, in the payout motor control processing, eight types of excitation pattern data are repeatedly output to the payout motor 289. In this embodiment, each excitation pattern data is output for 4 ms.

Next, error detection processing is performed, and a predetermined display is made on the error display LED 374 according to the result (error processing: step S759).

Note that the output port C is accessed in the payout motor control processing (step S758) in the payout control processing. The output port D is accessed in an error process (step S759) in the payout control process.
The output port E is accessed in the ball lending control process (step S756) and the prize ball control process (step S757) in the payout control process.

FIG. 41 is an explanatory diagram showing an example of use of the RAM incorporated in the payout control CPU 371. In this example,
In the backup RAM area, a total number storage (for example, 2 bytes) and a rental ball number storage are respectively formed.
The total number storage stores the total number of awarded ball payouts instructed from the main board 31 side. The rental ball number storage stores the number of unpaid ball rentals.

As described above, since the number of unpaid prize balls and the number of loaned balls are stored in the backup RAM area capable of holding the contents for a predetermined period, even if an unexpected power failure such as a power failure occurs, If the power is restored within a predetermined period, the prize ball processing and the ball lending processing stored in the backup RAM area can be continued. Therefore, the disadvantage given to the player can be reduced.

FIGS. 42 to 44 are flowcharts showing an example of the non-maskable interrupt processing executed in response to the power-off signal from the power supply board 910. In this example, the NMI
The power supply stop processing is executed according to the power supply stop signal. However, the power supply stop signal may be connected to the maskable terminal of the payout control CPU 371 and the power supply stop processing may be executed by the maskable interrupt processing. Alternatively, the power-off signal may be input to the input port, and the power supply stop processing may be executed according to the check result of the input port.

In the non-maskable interrupt processing, the payout control CPU 371 stores the AF register in the predetermined backup R
Save to the AM area (step S801). Further, the interrupt flag is copied to the parity flag (step S80).
2). The parity flag is formed in the backup RAM area. Also, BC register, DE register, HL
The registers, the IX register, and the stack pointer are saved in the backup RAM area (Steps S804 to S804)
08). When the power is restored, the register contents are restored on the basis of the saved contents, and the interrupt permission state / prohibition state is internally set according to the contents of the parity flag.

Next, the drive signal output to the payout motor 289 is turned off (step S761). Accordingly, the driving of the ball payout device 97 stops. Thereafter, in this embodiment, a prize ball count switch 301A (corresponding to a prize game medium detecting means) as a payout detecting means for a predetermined period.
And the detection signal of the ball lending count switch 301B (corresponding to a lending game medium detecting means) is checked. And
When the prize ball count switch 301A is turned on, the content of the total number storage is reduced by one. In addition, ball rental count switch 3
When 01B is turned on, the content of the stored number of lent balls is reduced by one.

In this embodiment, a counter for measuring a predetermined period is used to measure a predetermined period.
The value of the counter for the predetermined period measurement is decremented from the initial value m by one every time a switch detection processing loop (a loop starting from S763 and returning to S763) is executed once.
When the value becomes 0, it is assumed that the predetermined period has ended. In the detection processing loop, although there is an exception, almost constant processing is performed. Therefore, a time that is m times the time required for one round of the loop substantially corresponds to a predetermined period.

In order to measure the predetermined period, the payout control C
A built-in timer of the PU 371 may be used. That is, at the start of the switch detection process, a predetermined value (corresponding to a predetermined period) is set in the built-in timer. Then, every time the loop of the switch detection process is executed once, the count value of the built-in timer is checked. Then, when the count value becomes 0, it is assumed that the predetermined period has ended. Although an interrupt by the built-in timer can be used to detect that the value of the built-in timer has become 0, at this stage, the control is performed so as not to change the control contents (each value stored in the RAM). It is preferable to use a program configuration in which the count value of the built-in timer is read out and checked without using the program. The predetermined period is set to be equal to or longer than the time from when the game ball drops from the ball payout device 97 to when it reaches the prize ball count switch 301A or the ball lending count switch 301B.

At least during a predetermined period during which the switch detection process is executed, the prize ball count switch 301A and the ball lending count switch 301B must be in a state capable of detecting game balls. Therefore, in this embodiment, as shown in FIG. 10, a capacitor 923 as a relatively large-capacity auxiliary driving power supply is connected to the input side of the converter IC 922 in the power supply board 910. Therefore, even when the power supply to the gaming machine is stopped, the +12 V power supply voltage is maintained within the range in which the switches can be driven for a certain period of time, and the prize ball count switch 301A and the ball lending count switch 301B become operable. The capacity of the capacitor is determined so that the period is equal to or longer than the predetermined period.

The input port and payout control CPU
The 371 is also driven by the + 5V power supply created by the converter IC 922, so that it can operate for a relatively long time even when the power supply is stopped.

Further, in this embodiment, the distribution solenoid 310 is used to switch between the prize ball path and the lending ball path. Therefore, the capacitor 9 shown in FIG.
The capacity of 23 is such that the distribution solenoid 310 can be driven at least during the above-mentioned predetermined period.
The capacitor 923 is connected in parallel with the power line of VSL. However, since the game control means turns off the drive signal of another solenoid (for opening and closing a special winning opening) in response to the power-off signal, After the power-off signal is generated, the capacitor 923 is connected to the distribution solenoid 31 among the solenoids.
It is sufficient that only 0 can be driven.

Although the capacitor 923 used in this embodiment is one example of an auxiliary drive power supply, another capacitor may be used as the auxiliary drive power supply. At least during the above-mentioned predetermined period, the prize ball count switch 30
An auxiliary driving power supply of another mode can be used as long as it can drive the payout control means such as the 1A, the ball lending count switch 301B, the distribution solenoid 310, and the payout control CPU 371.

In the input processing (switch detection processing) of the detection signal from the payout detecting means, the payout control CPU 371 is used.
First, a value m corresponding to a predetermined period is set in a counter for measuring a predetermined period (step S762). Then, the payout control CPU 371 decrements the value of the counter for measurement for a predetermined period by one (step S763), and checks the value of the counter for measurement for a predetermined period (step S764). If the value is 0, the switch detection process ends, and the process shifts to a power supply stop process which is a process for saving the control state.

If the value of the counter for measurement for a predetermined period has not become 0, it is checked whether or not the award ball count switch is on (step S765). If it is ON, the value of the detection period counter is reduced by 1 (step S76).
6) It is checked whether the value of the detection period counter has become 0 (step S767). If it is 0, the detection signal of the prize ball count switch 301A is confirmed via the input port (step S768). Decrease the stored value by 1 (step S76)
9).

If it is determined in step S765 that the award ball count switch is not on, the detection signal of the award ball count switch 301A is confirmed via the input port (step S770). The count switch ON flag is set (step S771), and an initial value n is set in the detection period counter (step S772).

With the above processing, when the winning ball count switch 301A is turned on within a predetermined period, the value of the total number storage is decremented by one. Since the process for storing the contents of the backup RAM is performed after such a switch detection process, the total number storage is always decremented by one for the prize balls for which the payout has been completed. Therefore, it is possible to prevent inconsistency in the stored control state regarding the payout of the game balls. In the above switch detection processing, timer processing using a detection period counter is performed. That is,
Once the ON of the prize ball count switch 301A is detected, and after the elapse of a predetermined time (n times the processing time in the loop from S763 to S767 and returning to S763), the ON is not detected unless it is detected. Therefore, erroneous switch-on detection is prevented.

In the normal switch process (step S751 in FIG. 39), a timer process for preventing erroneous detection is performed. Therefore, such a normal switch process may be called. Although the timer process using the detection period counter is performed here, the timer in the switch detection process using the CPU built-in timer may be used similarly to the case where the CPU built-in timer may be used for measurement of a predetermined period. The processing may be realized.

If the award ball count switch is not being turned on and the on-state of the award ball count switch 301A cannot be detected, a switch detection process is performed on the ball lending count switch 301B. That is, the payout control C
The PU 371 checks whether or not the ball lending count switch is on (step S775). If it is on,
After reducing the value of the detection period counter by 1 (step S7)
76) It is checked whether the value of the detection period counter has become 0 (step S777). If it is 0, the detection signal of the ball lending count switch 301B is confirmed via the input port (step S778). If it indicates the ON state, it is determined that the ball lending count switch 301B is turned on without fail, and the lending ball is determined. The value of the number storage is reduced by 1 (step S779).

If it is confirmed in step S775 that the ball lending count switch is not on, the detection signal of the ball lending count switch 301B is confirmed via the input port (step S780). The count switch ON flag is set (step S781), and the initial value n is set in the detection period counter.
Is set (step S782).

With the above processing, if the ball lending count switch 301B is turned on within a predetermined period, the value of the lending ball number storage value is decremented by one. Since the process for storing the contents of the backup RAM is performed after such a switch detection process, the loaned ball number storage is always decremented by one for the loaned ball that has been paid out. Therefore, it is possible to prevent inconsistency in the stored control state regarding the payout of the game balls. In the above switch detection processing, timer processing using a detection period counter is performed. That is, unless the ball lending count switch 301B is kept on for a predetermined period of time or longer, it is not regarded as switch-on. Therefore, erroneous switch-on detection is prevented.

When the predetermined period has elapsed (step S76)
4), the payout control CPU 371 stores the designated value with backup ("55H" in this example) in the backup flag (step S809). The backup flag is formed in the backup RAM area. Then
Parity data is created by performing processing similar to that of the CPU 56 of the main board 31 and stored in the backup RAM area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S820). Thereafter, the internal RAM cannot be accessed.

Further, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S821), and sets the number of processes ("3" in this example) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Yet another register is used as the IO pointer.

Then, clear data is set at the address pointed to by the IO pointer (step S82).
4), increment the value of the IO pointer by 1 (step S82)
5), the value of the number of processes is subtracted by 1 (step S827).
If the value of the number of processes is 0 in the processes of steps S824 to S826,
Repeat until. As a result, clear data is set to all output ports CE (see FIG. 37). As shown in FIG. 37, in this example, “1” is on, and “00”, which is clear data, is set for each output port, so that all output ports are off.

Therefore, after the processing for saving the game state (in this example, generation of the checksum and prevention of RAM access) is performed, each output port is immediately turned off. In this embodiment, the RAM area in which data used in the payout control process is stored is all backed up by a power supply. Therefore, a process of generating a checksum indicating whether or not the content is correctly stored, and an R for preventing the content from being rewritten.
The AM access prevention process corresponds to a process for saving the payout control state.

As described above, in this embodiment, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the driving of the ball payout device 97 is stopped, and then the ball output device 97 receives the signal from the payout detection means for a predetermined period. Input processing of the detection signal is performed, and then processing for saving the payout control state is performed. Therefore,
The game balls that were in the process of being paid out when the power failure occurred are also reflected in the contents stored in the backup RAM.

That is, in this embodiment, if the control state is stored in the backup storage means when the power supply to the gaming machine is stopped, it is possible to prevent the occurrence of control inconsistency.

Note that the clearing process of the output ports other than the output port of the distribution solenoid 310 may be performed before the execution of the switch detecting process (before the step S761). During execution of the power supply stop processing, the payout control CPU 371
The switches and the like are driven by the charging power of the capacitor. When the output port clearing process is performed before the execution of the switch detection process, the charging power of the capacitor and the like can be efficiently used for the process at the time of stopping the power supply.

When the clear processing for the output port is completed, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

[0286] Here, the prize ball count switch 3
Timer (detection period counter) when detection signal of 01A or ball lending count switch 301B indicates ON state
If the detection signal indicates the ON state even when the timer expires, it is determined that the switch has been reliably turned on.
The configuration may be such that the detection signal is determined each time the ms timer (2 ms measurement counter) times out.

Also in this embodiment, the register saving processing is performed at the beginning of the processing started in response to the power-off signal. However, when the register is not used in the switch detection processing, the register detection processing is performed. After execution, that is, before register backup processing and checksum calculation processing, register storage processing can be performed. In this case, the register saving processing, the backup flag setting processing, the checksum calculation processing, and the output port off setting processing can be regarded as the power supply stop processing. Furthermore, even when some registers are used in the switch detection processing, register saving processing can be performed on unused registers before setting the backup flag and calculating the checksum.

FIG. 45 is a flowchart showing a part of the non-maskable interrupt processing using the clear data table of the payout control means according to another embodiment of the present invention. FIG.
The flowchart shown in FIG. 5 is executed following the processing in steps S801 to S820 shown in FIGS. That is, in this embodiment, after the RAM access is prohibited (step S820), the head address of the clear data table is set in the pointer (step S831), and after the data clear processing is executed (step S831). S832), and enters a standby state waiting for a system reset. A predetermined register is used as a pointer.

FIG. 46 is an explanatory diagram showing one configuration example of the clear data table. In the example shown in FIG. 46, in the clear data table, the processing number data (“3” in this example) and the address of the output port C (address 00)
H), clear data to be set to output port C,
.., The address of the output port E (address 02H) and clear data to be set in the output port E are set. The output port address and the clear data are set in ascending order of the output port address.

FIG. 47 is a flowchart showing the data clear processing in step S832. In the data clearing process, the payout control CPU 371 extracts the processing number data from the address indicated by the pointer (step S84).
1). Then, the value of the pointer is increased by 1 (step S8).
42). Next, address data (the address of the output port) is extracted from the address indicated by the pointer (step S843). Further, the value of the pointer is increased by 1 (step S844).

Then, clear data is extracted from the address indicated by the pointer (step S845), and the data is set to the address extracted in step S843 (step S846). Next, the value of the number of processes is decremented by 1 (step S847), and when the number of processes becomes 0, the data clearing process ends (step S848). Number of processes is 0
If not, the process returns to step S841.

Even if the clear data table is used, the clear signal output processing can be performed quickly, and the occurrence of inconsistency between the control state saved when the power supply to the gaming machine is stopped and the actual control state can be reduced. It can be effectively prevented. When the clear data table is used, the address data and the clear data do not have to be arranged in the order of addresses in the table, and the degree of freedom of the table configuration is increased.
Also, if there is an increase or decrease or change in the output port,
You only need to change the contents of the table, no program changes are required.

When clear data is 00H for all output ports, clear data need not be included in the clear data table. In that case, FIG.
S844, S8 in the data clear processing shown in FIG.
45 is unnecessary, and in step S846,
Clear data 00H is set at the address indicated by the address data.

In this embodiment, the total number of unpaid prize balls and loaned balls is stored, but when another storage method such as storing the number of payouts (for example, 25 per payout) is used. Even in this case, if the processing for inputting the detection signal from the payout detection means is executed for a predetermined period in response to the power-off signal, inconsistency occurs in the control state stored. Is prevented.

As described above, in each of the above-described embodiments, when the power-off signal is output in response to the occurrence of a power failure or the like, first, the driving of the payout device is stopped, and then the payout detecting means is stopped for a predetermined period. Is executed, and thereafter, processing for saving the payout control state is performed. Therefore, the game balls that were being paid out when the power failure occurred are also reflected in the contents stored in the backup RAM. Therefore, when the control state is stored in the backup storage unit when the power supply to the gaming machine is stopped, it is possible to prevent inconsistency or the like from occurring between the stored control state and the actual control state. it can.

Although the saved control state matches the actual control state, for example, when a player different from the player who played the game before the power was turned off plays the game, the control state is restored as it is. It is not preferable. In each of the above-described embodiments, it is determined whether or not to return to the game state at the time of power-off according to the operation state of the clear switch 921. At this time, if the clear switch 921 is on, Since the state restoring process is not executed and the normal initialization process is executed, the game store clerk or the like operates the clear switch 921 at the time of restarting the power supply of the gaming machine, so that the backup data storage area (variable data It is possible to select whether or not to execute the game state restoration processing based on the backup data stored in the storage means). In this way, it is possible not only to prevent inconsistency or the like from occurring between the stored control state and the actual control state, but also to improve the convenience in operating a gaming machine at a game arcade.

In the above-described embodiment, the operation of the ball dispensing device is stopped at the start of the interrupt process (in the above example, the non-maskable interrupt process) by the interrupt generated in response to the power-off signal, Input processing of the detection signal from the payout detection means was performed. However, when the power supply to the gaming machine is stopped, a first signal indicating that fact may be generated first, and a further signal may be generated when the voltage further decreases. Then, the operation of the ball payout device is stopped according to the first signal, the detection signal from the payout detection means is input, and the control state is backed up according to the second signal.
A process for storing in the AM may be performed.

FIG. 48 is a block diagram showing an example of the configuration of a power supply board 910A for performing such control. In this example, the power supply monitoring IC 93 is provided on the power supply board 910A.
2 is also installed. The power supply monitoring IC 932 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (for example, +24 V), it is determined that the power supply voltage has decreased, and a voltage drop signal (first signal) is output. When the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), the power supply monitoring IC 902 outputs a power supply cutoff signal (second signal) assuming that power supply cutoff occurs.

During the period from when the first signal is generated to when the second signal is generated, the game ball falls from the ball payout device 97 (or the prize ball payout device 97A or the loan ball payout device 97C). It is set to be equal to or longer than the time from the point in time until the ball reaches the prize ball count switch 301A or the ball lending count switch 301B. That is, the monitoring voltage of the power supply monitoring ICs 902 and 932 is set so as to be equal to or longer than that time. The output of the power supply monitoring IC 932 is supplied to the main board 31 and the payout control board 3 via the buffer circuits 939 and 940.
Reaches 7.

On the main board 31, the first signal, the voltage drop signal, is connected to the maskable external interrupt terminal of the CPU. Further, the power-off signal, which is the second signal, is connected to the non-maskable interrupt terminal as in the above-described embodiment. That is, the priority of the interrupt based on the second signal is higher than the priority of the interrupt based on the first signal.

FIGS. 48 and 49 are flowcharts showing an example of an interrupt process (voltage drop interrupt process) activated based on an interrupt generated in response to the generation of the first signal. The CPU 56 of the main board 31 stores the AF register (accumulator and flag register) in a predetermined backup RAM.
It is evacuated to the area (step S451). Further, the interrupt flag is copied to the parity flag (step S45).
2). The parity flag is formed in the backup RAM area. Also, BC register, DE register, HL
The registers, the IX register, and the stack pointer are saved in the backup RAM area (steps S454 to S454).
458).

Next, the CPU 56 sets an initial value n corresponding to a time of 2 ms in the 2 ms measurement counter (step S461). Then, the value of the 2 ms measurement counter is decremented by 1 until the value of the 2 ms measurement counter becomes 0 (step S 462) (step S 465). When the value of the 2 ms measurement counter becomes 0, the data input to the input port 1 is input (step S464). Next, clear data (00) is set (step S4).
65). Further, the input data from the input port 1 is set as a “comparison value” (step S466). Further, the address of the switch timer for the prize ball count switch 301A is set in the pointer (step S46).
7).

Then, the switch timer pointed to by the pointer (the address of the switch timer is set) is loaded (step S468), and the comparison value is shifted to the right (from the upper bit to the lower bit) (step S469). ). The data of the input port 1 is set as the comparison value. Then, in this case, the detection signal of the winning ball count switch 301A is pushed out by the carry flag.

If the value of the carry flag is "1" (step S470), that is, the award ball count switch 30
If the 1A detection signal is on, the value of the switch timer is incremented by 1 (step S471). If the value of the carry flag is "0", that is, if the detection signal of the winning ball count switch 301A is in an off state, clear data is set in the switch timer (step S472).
That is, if the switch is off, the value of the switch timer returns to zero.

When the value of the switch timer becomes 2 (step S473), the value stored in the total prize balls storage buffer is decremented by 1 (step S474), and the value of the prize ball information counter is incremented by 1 (step S474). Step S475).
If the value of the award ball information counter is 10 or more (step S476), the value of the award ball information output counter is incremented by 1 (step S477), and the value of the award ball information counter is decreased by 10 (step S478). Then, the process returns to step S461.

Since the power supply voltage decreases while the switch detection processing of steps S461 to S478 is being performed, the second signal should be generated. Therefore, a non-maskable interrupt occurs. FIG. 51 is a flowchart showing an example of the non-maskable interrupt.

In the non-maskable interrupt processing, the CPU 56
Is the backup specified value ("55H" in this example)
Is stored in the backup flag (step S48).
1). The backup flag is formed in the backup RAM area. Next, parity data is created (steps S482 to S491).

Then, after prohibiting RAM access (step S492), all output ports are turned off (steps S493 to S499). When the clear processing for the output port is completed, the CPU 56 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

With the above processing, when the prize ball count switch 301A is turned on within a predetermined period (a period from the first signal generation to the second signal generation), the value of the total prize ball number buffer is decremented by one. Since the process for storing the contents of the backup RAM is performed after such a switch detection process, the total prize ball number buffer is always decremented by one for the prize balls that have been paid out. Therefore, it is possible to prevent inconsistency in the stored control state regarding the payout of the game balls. As described above, during the predetermined period, the input check process may be performed on a detection signal of a detection unit (switch) other than the payout detection unit.

The output port clearing process is performed as shown in FIG.
Alternatively, it may be performed before the switch detection processing in the voltage drop interruption processing shown in FIG. 50 (after step S458).

In this embodiment, the register saving processing is performed at the beginning of the processing started in response to the voltage drop signal (first signal). However, when the register is not used in the switch detection processing, Can perform the register storage process after the switch detection process is performed, that is, in the process activated in response to the second signal. In this case, the register saving processing, the backup flag setting processing, the checksum calculation processing, and the output port off setting processing can be regarded as the power supply stop processing. Furthermore, even when some registers are used in the switch detection processing, the register saving processing can be performed on the unused registers in the processing started in response to the second signal.

FIG. 52 is a timing chart showing an example of how the detection signal input processing from the payout detecting means is executed. As shown in FIG. 52, when ball payout is executed around the time when the voltage drop signal is turned on (in this example, the level is changed from high level to low level), the input process of the detection signal from the payout detection means is executed. The prize ball count switch 301A is turned on within a period (a period before the second signal is generated). Therefore, the ball payout executed when the voltage drop signal is turned on can be reflected in the total prize ball count buffer.

Also on the payout control board 37, the first signal, the voltage drop signal, is connected to the maskable external interrupt terminal of the payout control CPU 371. Further, the power-off signal, which is the second signal, is connected to the non-maskable interrupt terminal as in the above-described embodiment. That is, the priority of the interrupt based on the second signal is higher than the priority of the interrupt based on the first signal.

FIG. 53 is a flowchart showing an example of an interrupt process (voltage drop interrupt process) started based on an interrupt generated in response to the generation of the first signal. The payout control CPU 371 first saves the AF register in a predetermined backup RAM area (step S801). Further, the interrupt flag is copied to the parity flag (step S802). The parity flag is formed in the backup RAM area. Further, the BC register, the DE register, the HL register, the IX register, and the stack pointer are saved in the backup RAM area (step S8).
04-808).

Next, the drive signal output to the payout motor 289 is turned off (step S761). Accordingly, the driving of the ball payout device 97 stops. Prize ball payout device 9
If 7A and the rental ball dispensing device 97C are separately provided, the driving of both is stopped.

Then, it is determined whether or not the award ball count switch is on (step S765). If it is ON, the value of the detection period counter is reduced by 1 (step S766), and it is confirmed whether the value of the detection period counter has become 0 (step S767). If it is 0,
The detection signal of the prize ball count switch 301A is confirmed via the input port (step S768). If the signal indicates an ON state, it is determined that the prize ball count switch 301A is reliably turned on and the value of the total number storage is reduced by one (1). Step S
769).

If it is confirmed in step S765 that the award ball count switch is not on, the detection signal of the award ball count switch 301A is confirmed via the input port (step S770). The count switch ON flag is set (step S771), and an initial value n is set in the detection period counter (step S772).

When the winning ball count switch 301A is turned on within a predetermined period by the above processing, the value of the total number storage is decremented by one. Since the process for storing the contents of the backup RAM is performed after such a switch detection process, the total number storage is always decremented by one for the prize balls for which the payout has been completed. Therefore, it is possible to prevent inconsistency in the stored control state regarding the payout of the game balls. In the above processing, a timer processing using a detection period counter is performed. That is, if ON is not detected even after a predetermined time (n times the processing time in the loop from S763 to S767 and returning to S763) after the ON of the prize ball count switch 301A is detected, the switch is not considered to be ON. . Therefore, erroneous switch-on detection is prevented.

If the award ball count switch is not on and the on-state of the award ball count switch 301A cannot be detected, a switch detection process is performed on the ball lending count switch 301B. The processing is the same as in the embodiment described above (see FIG. 43). While the switch detection processing is being performed on the prize ball count switch 301A and the ball lending count switch 301B, the power supply voltage decreases, so that the second signal should be generated. Therefore, a non-maskable interrupt occurs.

In this embodiment, also, at least until the second signal is generated, the award ball count switch 3
An auxiliary drive power supply (capacitor 923 in this example) that can drive the switch detection processing of the ball-counting switch 301B and the sorting solenoid 310 and the payout control unit is used.

[0321] Here, the prize ball count switch 3
Timer (detection period counter) when detection signal of 01A or ball lending count switch 301B indicates ON state
If the detection signal indicates the ON state even when the timer expires, it is determined that the switch has been reliably turned on.
The configuration may be such that the detection signal is determined each time the ms timer (2 ms measurement counter) times out.

The output port clearing process is performed as shown in FIG.
It may be performed before the switch detection processing in the voltage drop interruption processing shown (after step S808).

FIG. 54 is a flowchart showing an example of a non-maskable interrupt. In the non-maskable interrupt process, the payout control CPU 371 first stores the designated value with backup ("55H" in this example) in the backup flag (step S809). The backup flag is formed in the backup RAM area. Next, the same processing as that of the CPU 56 of the main board 31 is performed to create parity data and store it in the backup RAM area (steps S810 to S819). Then, an access prohibition value is set in the RAM access register (step S
820). Thereafter, the internal RAM cannot be accessed.

Further, the payout control CPU 371 sets the clear data (00) in an appropriate register (step S821), and sets the number of processes ("3" in this example) in another register (step S822). Further, the address of the output port C (“00H” in this example) is set in the IO pointer (step S823). Yet another register is used as the IO pointer.

Then, clear data is set at the address pointed to by the IO pointer (step S82).
4), increment the value of the IO pointer by 1 (step S82)
5), the value of the number of processes is subtracted by 1 (step S827).
If the value of the number of processes is 0 in the processes of steps S824 to S826,
Repeat until. As a result, clear data is set to all the output ports CE (see FIG. 36).

Upon completion of the clearing process for the output port, the payout control CPU 371 enters a standby state (loop state). Therefore, nothing is done until the system is reset.

In this embodiment, the power supply monitoring means mounted on the power supply board 910A (in this example, the power supply monitoring IC 9
02, 932) monitors the power supply, and outputs a first signal when the first condition (in this example, the +30 V power supply voltage is equal to or lower than +24 V) is satisfied, and outputs the second signal (in this example, +30 V in this example).
The second signal is output when the condition of (30 V power supply voltage becomes +22 V or less) is satisfied. The period from when the first signal is generated to when the second signal is generated is set to be equal to or longer than the time until the game balls paid out from the payout means reach the payout detection means. In addition, +2 used in this embodiment is used.
The conditions of 2V and + 24V are examples, and may have different values depending on the type of gaming machine.

Then, in the processing according to the first signal, first, after the driving of the payout device is stopped, the input processing of the detection signal from the payout detecting means is repeatedly executed, and thereafter, according to the second signal. Processing for saving the payout control state is performed. Therefore, the game balls that were being paid out when the power failure occurred are also detected by the processing according to the first signal.
This is reflected in the content stored in the backup RAM in the processing according to the second signal. Therefore, when the control state is stored in the backup storage unit when the power supply to the gaming machine is stopped, it is possible to prevent inconsistency or the like from occurring between the stored control state and the actual control state. it can.

When ball payout is executed around the time when the voltage drop signal is turned on (change from high level to low level in this example), a predetermined period during which input processing of the detection signal from the payout detection means is executed (second Before signal is generated)
The prize ball count switch 301A or ball lending count switch 301B is turned on. In this embodiment,
Since the switch input process is executed in the voltage drop interrupt process (see FIG. 53) activated in response to the generation of the first signal,
Therefore, the ball payout executed around the time when the voltage drop signal is turned on can also be reflected in the total number storage or the number of lent balls.

In this embodiment, the register saving processing is performed at the beginning of the processing started in response to the voltage drop signal (first signal). However, when the register is not used in the switch detection processing, Can perform the register storage process after the switch detection process is performed, that is, in the process activated in response to the second signal. In this case, the register saving processing, the backup flag setting processing, the checksum calculation processing, and the output port off setting processing can be regarded as the power supply stop processing. Furthermore, even when some registers are used in the switch detection processing, the register saving processing can be performed on the unused registers in the processing started in response to the second signal.

Further, in each of the above embodiments, the case where the game control means and the payout control means perform the switch detection processing in response to the power-off signal has been described. Also, when the control state saving process is performed, in response to the power-off signal, stop driving the predetermined electrical component, after confirming the detection signal of the switch means related to the electrical component for a predetermined period, The control state saving process may be configured to be performed.

Further, in each of the above embodiments, the clear switch 921 has a push button structure, but may have another structure. FIG. 55 is an external configuration diagram illustrating an example of a configuration of a clear switch 921 according to another embodiment mounted on a switch board 190. A clear switch 921 shown in FIG. 55 is a changeover switch 921 for selectively switching between “OFF”, “ON”, and “clear”.
a. In this example, “O” of the clear switch 921 is set.
When "FF" is selected, the operation is stopped without generating any signal, and when "ON" is selected, a high-level signal is output. Clear switch 92
1 indicates that power supply to the gaming machine 1 is turned on / off in this example.
The configuration is linked to a switch for switching off. Therefore, when "OFF" is selected by the clear switch 921, the power supply of the gaming machine 1 is stopped (the power of the gaming machine is off), and "ON" and "clear" are selected. When it is, the gaming machine 1 may be in the operating state (the power of the gaming machine is on). Further, when “clear” of the clear switch 921 is selected, a low-level clear signal may be output.

In each of the above embodiments, the power supply monitoring circuit is provided on the power supply board 910. However, the power supply monitoring circuit may be provided on the electric component control boards such as the main board 31 and the payout control board 37. Good. When the electric component control board on which the power supply circuit is mounted is configured, the power supply monitoring circuit is not mounted on the power supply board.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-type pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a winning start is a combination of a predetermined symbol. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine in which a predetermined gaming value can be given to a player, or a variable display based on a starting prize The present invention is applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol to be stopped becomes a predetermined combination of symbols. it can.

Further, the present invention is not limited to the pachinko game machine in which the game medium is a game ball, and the present invention can be applied to a slot machine or the like if an electric component for paying out the game medium is provided.

[0336]

As described above, according to the present invention, a game machine is a game machine that allows a player to play a predetermined game, and controls an electric component provided in the game machine. An electric component control microcomputer, a fluctuation data storage means for storing fluctuation data generated when the electric component control microcomputer performs control, and a fluctuation immediately before the power supply is stopped even when the power supply to the gaming machine is stopped. A storage content holding unit capable of holding the final storage content of the data storage unit, an initialization operation unit capable of initializing the variation data stored in the variation data storage unit, and an electric component control microcomputer. An output port for outputting predetermined data, the electric component control microcomputer performs a predetermined power supply stop processing when the power supply to the gaming machine is stopped. It is possible to perform, at the time of processing a power outage, since to perform the output port clearing process for clearing the data outputted to the output port,
The operating state of each electric component can be made consistent with the stored game state, and an appropriate control state can be stored. In addition, it is possible to prevent the stored control state from being restored according to the judgment of the game store clerk or the like.

When the electric component control microcomputer confirms that the initialization operation means is in a predetermined operation state at the time of restarting power supply, it is assumed that the final storage contents of the variation data storage means are to be initialized. Thus, in the initial stage of control resumption, it is possible to prevent the control state from being restored to the saved control state.

An input port for the electrical component control microcomputer to obtain predetermined data is provided, and an initialization signal output when the initialization operation means is in a predetermined operation state is input to the input port. In such a case, it is possible to introduce an initialization signal output according to the operation state of the operation of the initialization operation means with a simple configuration using an existing input port.

The electric component control microcomputer is a payout control microcomputer for controlling a payout means for paying out game media.
When the driving of the payout means is configured to be stopped, unnecessary payout is effectively prevented from being made.

If the electric component control microcomputer is a game control microcomputer for controlling the variable winning ball device, and the drive of the variable winning ball device is stopped by the output port clearing process, the variable winning ball device is set. It is possible to prevent the game medium from entering the variable winning ball device even though the ball device does not remain open and no winning is detected.

The game device includes game medium detection means for detecting game media, and power supply monitoring means for monitoring the state of a predetermined power supply used in the gaming machine. If it is detected that the game medium has entered a predetermined state, and if the input processing of the detection signal from the game medium detecting means is to be executed for a predetermined period, the game medium to be detected may be detected. It is possible to backup and store an appropriate control state regarding the number of game media.

If the game medium detecting means includes payout detecting means for detecting the game medium paid out by the payout means for paying out the game medium, the appropriate number of game medium payouts is determined. Backup storage becomes possible.

When the power supply monitoring means detects that the state of the power supply has reached a predetermined state, the electric component control microcomputer executes a process of inputting a detection signal from the game medium detection means. If the output port clear processing is performed before, the input processing from the game medium detecting means can be executed after the operation of the electric component is stopped. Becomes possible.

The initialization request detection determination period for determining whether or not the initialization operation means is in a predetermined operation state is a game medium detection determination period for determining whether the game medium is detected by the game medium detection means. If the period is different, the processing for determining the operation state of the initialization operation means and the processing for determining the presence of the game medium can be different processing.

If the electric component control microcomputer executes processing for prohibiting access to the variable data storage means in the processing at the time of power supply stop, there is a possibility that this will occur as the power supply voltage decreases. It is possible to reliably prevent the destruction of the content of the area (for example, RAM) in which the backup storage is stored due to a certain abnormal operation, and to surely protect the data stored in the RAM restored when the power is turned on thereafter. Can be.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an explanatory view showing each substrate provided on the back surface of the pachinko gaming machine.

FIG. 3 is a rear view of the mechanical panel of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a front view showing a configuration around an intermediate base unit installed on a mechanism plate.

FIG. 5 is an exploded perspective view showing a ball payout device.

FIG. 6 is a front view showing an example in which a game board on which a switch board is mounted is viewed from the front.

FIG. 7 is a circuit diagram illustrating an example of a configuration of a clear switch.

FIG. 8 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 9 is a block diagram showing components related to a prize ball, such as components of a payout control board and a ball payout device.

FIG. 10 is a block diagram illustrating a configuration example of a power supply board.

FIG. 11 is a block diagram illustrating a configuration example around a CPU on a main board.

FIG. 12 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 13 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 14 is an explanatory diagram showing an example of bit assignment of an input port.

FIG. 15 is a flowchart illustrating a main process executed by a CPU on a main board.

FIG. 16 is an explanatory diagram showing an example of a relationship between a backup flag and whether or not to execute a game state restoration process.

FIG. 17 is a flowchart showing a 2 ms timer interrupt process.

FIG. 18 is an explanatory diagram showing an example of forming a switch timer in a RAM.

FIG. 19 is a flowchart illustrating an example of a switch process.

FIG. 20 is a flowchart illustrating an example of a switch check process.

FIG. 21 is a flowchart illustrating an example of a prize ball process.

FIG. 22 is a flowchart illustrating an example of a prize ball process.

FIG. 23 is a flowchart illustrating an example of a prize ball process.

FIG. 24 is a flowchart showing a switch-on check process.

FIG. 25 is a flowchart illustrating an example of a winning ball number subtraction process.

FIG. 26 is an explanatory diagram showing a configuration example of an input determination value table.

FIG. 27 is a flowchart showing a non-maskable interrupt process in the game control means.

FIG. 28 is a flowchart showing a non-maskable interrupt process in the game control means.

FIG. 29 is a flowchart showing a non-maskable interrupt process in the game control means.

FIG. 30 is a flowchart showing another example of the power supply stop processing in the game control means.

FIG. 31 is an explanatory diagram showing a configuration example of a clear data table.

FIG. 32 is a flowchart showing data clear processing.

FIG. 33 is a timing chart showing an example of how a detection signal input process is executed.

FIG. 34 is an explanatory diagram illustrating an example of a gaming area of a third-type pachinko gaming machine.

FIG. 35 is a flowchart illustrating an example of a game state restoring process.

FIG. 36 is a block diagram illustrating a configuration example around a payout control CPU for power supply monitoring and power supply backup.

FIG. 37 is an explanatory diagram showing an example of bit assignment of an output port.

FIG. 38 is an explanatory diagram showing an example of bit assignment of an input port.

FIG. 39 is a flowchart showing a main process executed by the CPU in the payout control board.

FIG. 40 is a flowchart showing a 2 ms timer interrupt process.

FIG. 41 is an explanatory diagram showing one configuration example of a RAM in the payout control means.

FIG. 42 is a flowchart showing non-maskable interrupt processing in the payout control means.

FIG. 43 is a flowchart showing non-maskable interrupt processing in the payout control means.

FIG. 44 is a flowchart showing non-maskable interrupt processing in the payout control means.

FIG. 45 is a flowchart showing another example of the non-maskable interrupt processing in the payout control means.

FIG. 46 is an explanatory diagram showing a configuration example of a clear data table.

FIG. 47 is a flowchart showing data clear processing.

FIG. 48 is a block diagram showing another configuration example of the power supply board.

FIG. 49 is a flowchart showing a voltage drop interruption process of the game control means.

FIG. 50 is a flowchart showing a voltage drop interruption process of the game control means.

FIG. 51 is a flowchart showing another example of the non-maskable interrupt processing of the game control means.

FIG. 52 is a timing chart showing an example of how a detection signal input process is executed.

FIG. 53 is a flowchart showing a voltage drop interrupt process of a payout control unit.

FIG. 54 is a flowchart showing another example of the non-maskable interrupt processing of the payout control means.

FIG. 55 is an explanatory diagram showing an example of an external configuration of a clear switch according to another embodiment.

[Explanation of symbols]

 31 game control board (main board) 37 payout control board 54 ROM 55 RAM 56 CPU 57 I / O port 371 payout control CPU 921 clear switch

Claims (10)

[Claims] An electronic component control microcomputer for controlling an electrical component provided in the gaming machine, wherein the electronic component control microcomputer includes: an electronic component control microcomputer; A fluctuation data storage unit for storing fluctuation data generated when performing control, and the final storage contents of the fluctuation data storage unit immediately before the stop of power supply can be held even when power supply to the gaming machine is stopped. Storage content holding means, initialization operation means capable of initializing the variation data stored in the variation data storage means, and an output port for the electrical component control microcomputer to output predetermined data. The electric component control microcomputer can perform a predetermined power supply stop processing when the power supply to the gaming machine is stopped. In the power supply stop process, the gaming machine which is characterized in that the output port clearing process for clearing the data output to the output port. 2. The electric component control microcomputer according to claim 1,
2. The gaming machine according to claim 1, wherein when the power supply is restarted, when it is confirmed that the initialization operation means is in a predetermined operation state, the final storage content of the fluctuation data storage means is initialized. 3. An input port through which an electrical component control microcomputer acquires predetermined data is provided, and an initialization signal output when the initialization operation means is in a predetermined operation state is supplied to the input port. The gaming machine according to claim 2, which is input to the game machine. 4. The microcomputer for controlling an electric component,
4. The gaming machine according to claim 1, further comprising a payout control microcomputer for controlling payout means for paying out game media, wherein the output port clear processing stops driving the payout means. 5. The microcomputer for controlling an electric component,
5. The gaming machine according to claim 1, further comprising a game control microcomputer for controlling the variable winning ball device, wherein the drive of the variable winning ball device is stopped by an output port clearing process. 6. A game medium detection means for detecting a game medium, and a power supply monitoring means for monitoring a state of a predetermined power supply used in the gaming machine, wherein the electric component control means includes a power supply monitoring means 4. The method according to claim 1, wherein when a state of the power supply is detected to be a predetermined state, input processing of a detection signal from said game medium detecting means is executed for a predetermined period. 5. The gaming machine according to 5. 7. The gaming machine according to claim 6, wherein the game medium detecting means includes a payout detecting means for detecting the game medium paid out by the payout means for paying out the game medium. 8. The microcomputer for controlling an electric component,
When the power supply monitoring means detects that the state of the power supply has reached a predetermined state, performing output port clear processing before executing input processing of a detection signal from the game medium detection means. The gaming machine according to claim 6 or 7, wherein 9. An initialization request detection determination period for determining whether the initialization operation means is in a predetermined operation state is a game medium detection determination for determining whether a game medium is detected by the game medium detection means. 9. The gaming machine according to claim 6, wherein the period is different from the period. 10. The gaming machine according to claim 1, wherein the electric component control microcomputer executes processing for prohibiting access to the variable data storage means in the processing at the time of power supply stop.