JP4226611B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine in which a game is performed according to a player's operation, and particularly, a game is performed according to a player's operation in a gaming area on a gaming board. It relates to gaming machines.

  As an example of a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium is won in a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are awarded to the player There are things that will be paid out. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  Note that the game value is the right that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous for a player who is likely to win a ball, or the advantageous state for a player. Or a condition that a condition for giving out premium game media is easily established.

  In a pachinko game machine, the combination of a specific display mode with a predetermined display result of a variable display unit that displays special symbols is usually referred to as “big hit”. When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state in which a hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, among the combinations of display modes other than the “big hit” combination, the variable display in which the display result has already been derived and displayed at the stage where some of the display results of the plurality of variable display units have not yet been derived and displayed. A state in which the display mode of the part satisfies a display condition that is a combination of specific display modes is referred to as “reach”. Then, if the display result of the identification information variably displayed on the variable display portion does not satisfy the condition of “reach”, it becomes “missing”, and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

  The game progress in the gaming machine is controlled by game control means such as a microcomputer. The identification information, character image, and background image displayed on the variable display device are controlled by display control means that operates in accordance with display control command data from the game control means. In general, the identification information, character image, and background image displayed on the variable display device are a display control microcomputer and a video display processor that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side ( VDP), the program capacity of the display control microcomputer is large.

  Therefore, it is impossible to control identification information and the like displayed on the variable display device by the microcomputer of the game control means having a limited program capacity, and the display control microcomputer (separate from the microcomputer of the game control means) Display control means) is used. Therefore, the game control means for controlling the progress of the game needs to transmit a display control command to the display control means.

  In addition, when a game ball wins a winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board that controls the payout device.

  Furthermore, in such a gaming machine, a speaker is provided and various sound effects are emitted from the speaker as the game progresses in order to enhance the gaming effect. In addition, light emitters such as lamps and LEDs are provided in the game area and frame of the gaming machine, and the light emitters are turned on and off as the game progresses in order to enhance the game effect. Since the sound from the speaker and the lighting / extinguishing of each light emitter are controlled according to the progress of the game, these controls are generally performed by game control means for controlling the progress of the game. In that case, the control burden of the game control means is reduced by providing a sound control means for performing specific control on the speaker and a light emitter control means for performing specific control on the light emitter provided separately from the game control means. be able to.

  As described above, a gaming machine may be equipped with various control means in addition to the game control means. In that case, the game control means for controlling the progress of the game transmits each command indicating an operation instruction according to the game situation to each control means mounted on each control board. Hereinafter, the control means mounted on the game control board and other control boards may be referred to as electric component control means. Hereinafter, the game control board and other control boards may be referred to as electrical component control boards. The payout control unit is an example of a value addition control unit.

  The electric component control means on each electric component control board is often realized by a microcomputer. In the case of using a microcomputer, it is necessary to give a reset state to the microcomputer when the power is turned on, and then enter a reset release state. Therefore, each electric component control board is provided with a circuit for generating a reset signal.

  When a plurality of electrical component control boards are mounted, there may be a problem if the startup order and the shutdown order of each board are incorrect. Generally, the rise is performed when the reset signal is in the reset release state, and the fall is realized when the power supply voltage falls below a predetermined value.

  If the startup sequence and the shutdown sequence are not appropriate, for example, when a control command is transmitted from the game control board to each electrical component control board, the command receiving side is not the side that receives the command, even though the game control means sends the command. In some cases, the control means is not yet operable. In addition, even if the game control means sends a command, the control means on the command receiving side may already be inoperable. In this case, the game control means recognizes that the command has been sent, but the control means on the side that receives the command cannot receive the command. As a result, a control discrepancy occurs between the game control means and the other electrical component control means.

  When the startup control of each electrical component control means is performed by a reset circuit mounted on the electrical component control board, and the shutdown control is realized by a decrease in the power supply voltage, the electrical component control means is properly controlled. It is difficult to order the startup and shutdown. This is because the start-up control is independently performed on each board, and thus it is difficult to order the entire board. Moreover, since the power supply to all the boards is cut off at once when the power supply to the gaming machine is cut off, it is still difficult to manage the order of the shutdown.

Accordingly, an object of the present invention is to provide a gaming machine that can rationally manage the order of the shutdown of each electrical component control board in a configuration including a plurality of electrical component control boards.

The gaming machine according to the present invention is a gaming machine in which a player can play a predetermined game, and controls the progress of the game and transmits a payout control command indicating the number of winning balls when a winning is detected. A game control means comprising: a payout control means for paying out a prize ball based on reception of a payout control command from the game control means; and a power supply monitoring means for detecting a voltage drop of a predetermined potential power supply and outputting a detection signal. Indicates that data is stored in the game control backup RAM area in which the contents are stored even if the power to the gaming machine is cut off, and in accordance with the detection signal from the power supply monitoring means. The backup data shown is stored in the game control backup RAM area, and the check data is calculated by calculation based on the data in the game control backup RAM area. And the game control side power-off processing execution means for executing the game control-side power-off processing processing for storing the generated check data in the game control backup RAM area, and the payout control means includes a power supply for the gaming machine. The payout control backup RAM area that saves the contents even if it is cut off, and the payout control side power off process for saving the data in the payout control backup RAM area according to the detection signal from the power supply monitoring means And a payout control side power-off process execution means, and when a detection signal is output from the power supply monitoring means, the processing start time of the payout control side power-off process execution means is determined as a game control side power-off process. The game control means includes a delay means for delaying the processing start time of the execution means, and the game control means stores the backup data when the power supply to the gaming machine is started. On the condition that it is stored in the up RAM area, it is determined whether or not the storage content of the game control backup RAM area is normal based on the check data, and the storage contents of the game control backup RAM area are determined based on the determination If it is determined that the game state is normal, a game state recovery process is performed to return the control state to the state at the time of power- off.

  The gaming machine includes a power supply board that is provided separately from each electrical component control board and generates a power supply voltage used by each electrical component control board, and the startup management means is provided on the power supply board. Also good.

  The electric component control board includes a main board on which game control means for controlling the progress of the game is mounted, and a value addition control board on which value addition control means for performing control for giving a predetermined value to the player is mounted. The start-up management means may be configured to start up the game control means after starting up the value addition control means. In addition, the value is a game medium such as a game ball or coin that is paid out to a player when a predetermined condition such as winning is established, or a score given to a player when a predetermined condition such as winning is established. That is.

  The electrical component control board includes a main board on which game control means for controlling the progress of the game is mounted, and an effect control board on which effect control means for performing control related to the game effects are mounted, and the start-up management means The game control means may be started up after the effect control means on the effect control board is started up.

  The start-up management means may be configured to manage the output order of reset release signals that allow operation of the plurality of control means.

  The start-up management means may be configured to include delay means for delaying at least the output of the reset release signal to the main board.

  The start-up management means may be configured to control the output order of the reset release signal by monitoring the power supply voltage used in the gaming machine.

  The start-up management means may be configured to control the start order of power supply to the plurality of electrical component control boards.

  The start-up management unit may include a delay unit that delays at least the start of power supply to the main board.

According to the present invention, there is an effect that a situation in which a payout control command from the game control means cannot be received by the payout control means on the receiving side does not occur .

  When the startup management means is provided on the power supply board, the startup timing of each control means is created using the rise of the power supply voltage, so that startup management can be performed more easily.

  If the start-up management means is configured to start the game control means after starting the value addition control means, the value will be given when the game control means sends a control command to the value assignment control means. There is no case that the assignment control means has not been started, and the control command is reliably received.

  When the start-up management means is configured to start up the game control means after starting up the effect control means on the effect control board, the game control means sends a control command to the effect control board. When this is done, the production control means does not stand up, and the control command is reliably received.

  When the start-up management means is configured to manage the output order of reset release signals to a plurality of electrical component control boards, each control means is activated by the reset release signal, so start-up management is easy become.

  When the start-up management means includes at least a delay means for delaying the output of the reset release signal to the main board, when the game control means sends a control command to the other control means Therefore, the control means is not started up, and the control command is reliably received.

  When the start-up management means is configured to control the output order of the reset release signal by monitoring the power supply voltage used in the gaming machine, it can be appropriately set by appropriately setting the monitoring target voltage. A reset release signal can be output at a proper timing.

  When the start-up management means is configured to control the start order of power supply to a plurality of electrical component control boards, the start-up order should be managed by the power source that is the source of operation of each control means. Can do.

  When the start-up management means is configured to include at least a delay means for delaying the start of power supply to the main board, the start order of power supply can be easily managed.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front, FIG. 2 is a rear view showing each board disposed on the back of the pachinko gaming machine 1, and FIG. FIG. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to an image-type gaming machine or a slot machine.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing the stored balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, there is provided a variable display device 8 including a variable display unit 9 for variably displaying a plurality of types of symbols and a variable display 10 using 7 segment LEDs. Further, a passage memory display (ordinary symbol memory display) 41 composed of four LEDs is provided below the variable display 10. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passage gate 11 is guided toward the start winning opening 14 through the ball outlet 13. In the path between the passage gate 11 and the ball outlet 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 19, 24, and winning of each game ball to each of the winning holes 19, 24 is detected by correspondingly provided winning hole switches 19a, 24a. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when a prize ball is paid out is provided in the vicinity of one speaker 27, and a ball break lamp 52 that is lit when a supply ball is cut out in the vicinity of the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by 1.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, each board | substrate arrange | positioned at the back surface of the pachinko game machine 1 is demonstrated.
As shown in FIG. 2, on the back surface of the pachinko gaming machine 1, a ball storage tank 38 is provided above the mechanism plate in the frame 2 </ b> A, and the pachinko gaming machine 1 is installed above the gaming machine installation island. The game balls are supplied to the ball storage tank 38. The game balls in the ball storage tank 38 reach the ball payout mechanism (not shown) through the guide rod 39.

  On the back side of the gaming machine, there are installed a variable display control unit 29 for controlling the variable display unit 9, a game control board (main board) 31 on which a game control microcomputer and the like are mounted. Further, a payout control board 37 on which a payout control microcomputer for performing ball payout control and the like, and a hitting ball launching device for hitting a hitting ball into the game area 7 using the rotational force of the motor are installed. Furthermore, the sound control for controlling the sound generation from the decoration lamp 25, the game effect LED 28a, the game effect lamps 28b and 28c, the lamp control board 35 for sending signals to the prize ball lamp 51 and the ball break lamp 52, and the speaker 27. A launch control board 91 for controlling the board 70 and the ball hitting device is also provided. The payout control board 37 is also equipped with an error display LED 374.

  Furthermore, a power supply board 910 on which a power supply circuit for generating DC30V, DC21V, DC12V and DC5V is mounted is provided, and a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. Has been. The terminal board 160 includes at least a ball break terminal for introducing and outputting an output of a ball break detection switch 167, which will be described later, a prize ball terminal for outputting a prize ball number signal and a ball lending number signal. A ball lending terminal is provided for external output. Near the center, an information terminal board (external information output device) 34 having terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed.

  In FIG. 2, signals from the lamp control board 35 and the sound control board 70 are supplied to the game effect LED 28 a, game effect lamps 28 b and 28 c, the prize ball lamp 51, and the ball break lamp 52 provided on the frame side. The balance display board 74 on which the electrical relay board A77 and the frequency display LED and the like are mounted is shown, but other relay boards are also provided as necessary for signal relay.

  FIG. 3 is a rear view of the mechanism plate of the pachinko gaming machine 1 as seen from the back. The ball stored in the ball storage tank 38 passes through the guide rod 39, passes through the ball break detectors (ball break switches) 187a and 187b, and passes through the ball supply rods 186a and 186b as shown in FIG. To 97. The ball break switches 187a and 187b are switches that detect the presence or absence of a game ball in the game ball passage, but a ball break detection switch 167 that detects a shortage of supply balls in the ball tank 38 is also provided. The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45.

  Although not shown in FIG. 3, a ball sorting member is provided below the ball dispensing device 97. The ball sorting member is driven by a sorting solenoid. For example, when the solenoid is on, the ball sorting member falls to the right, and when the solenoid is off, the ball sorting member falls to the left. Below the sorting solenoid, a prize ball count switch and a ball lending count switch by proximity switches are provided. That is, in this embodiment, the winning ball payout and the ball lending are performed by the same ball payout device 97. However, a configuration in which the mechanism for paying out a prize ball and the mechanism for lending a ball are independent may be employed.

  A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A lot of prize balls based on the winnings are paid out, the hitting ball supply tray 3 is filled, and when the game balls are finally paid out after reaching the contact hole 45, the game balls are surplus through the surplus ball passage 46. It is guided to the ball receiving tray 4. When the game ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the ball hitting device 34 is also stopped.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. 4 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a display control board 80. The main board 31 includes a basic circuit 53 that controls the pachinko gaming machine 1 according to a program, a gate switch 12, a start port switch 17, a V count switch 22, a count switch 23, winning port switches 19a and 24a, and a winning ball count switch 301A. And a solenoid circuit 59 for driving a solenoid 16 for opening / closing the variable winning ball apparatus 15 and a solenoid 21 for opening / closing the opening / closing plate 20 in accordance with a command from the basic circuit 53. Has been.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the fact that the probability variation has occurred. An information output circuit 64 is provided for outputting the probability variation information and the like to a host computer such as a hall management computer.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is an example of storage means used as a work memory, a CPU 56 that performs control operations according to the program, and an I / O port unit 57. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in. A part or all of the RAM 55 is a backup RAM backed up by a backup power source.

  Further, the main substrate 31 has an address decoding circuit 67 that decodes an address signal supplied from the basic circuit 53 and outputs a signal for selecting any I / O port of the I / O port unit 57. Is provided. Note that there is switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

  Further, the CPU 56 is supplied with a reset signal and a power-off signal from the power supply board 910. When the reset signal is at a low level, the CPU 56 is in a reset state, and when the reset signal is at a high level, the CPU 56 is in an operable state. That is, the reset signal corresponds to a reset release signal at the time of rising. When the power-off signal is in a state indicating that the power-supply voltage has become a predetermined value or less, the CPU 56 executes a power-off process described later.

  The ball launching device that hits and launches the game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the start memory indicator 18, the gate passing memory indicator 41 and the decoration lamp 25 provided on the game board. At the same time, display control of the game effect lamps / LEDs 28a, 28b, 28c, the prize ball lamp 51 and the ball-out lamp 52 provided on the frame side is performed. Here, the lamp control means is an example of a light emitter control means. Further, display control of the variable display unit 9 that variably displays special symbols and the variable display 10 that variably displays normal symbols is performed by display control means mounted on the display control board 80.

  FIG. 5 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 5, the detection signal from the full switch 48 is input to the I / O port 57 of the main board 31 via the relay board 71. The full tank switch 48 is a switch for detecting a full tank of the surplus ball tray 4. Further, detection signals from the ball break switches 187a and 187b are also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71.

  The CPU 56 of the main board 31 instructs the payout prohibition when the detection signals from the ball break switches 187a and 187b indicate a ball dead state or when the detection signal from the full tank switch 48 indicates a full tank state. To issue a payout control command. When a payout control command for instructing payout is received, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, a detection signal from the prize ball count switch 301 </ b> A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A is provided at the lower part of the ball payout device 97, and detects a prize ball payout ball actually paid out.

  When there is a winning, a payout control command indicating the number of winning balls is input to the payout control board 37 from the output ports (ports 0, 1) 570, 571 of the main board 31. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). A payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 inputs a payout control command via the I / O port 372a, and drives the ball payout device 97 in accordance with the payout control command to perform prize ball payout.

  In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM. Further, a part or all of the RAM is a backup RAM backed up by a backup power source.

  In the main board 31, buffer circuits 620 and 68A are provided outside the output ports 570 and 571. As the buffer circuits 620 and 68A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to more reliably eliminate a signal line from which a signal may be given from the payout control board 37 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer drive signal to the buzzer board 75 via the output port 372g and the information output circuit 377. A buzzer is mounted on the buzzer substrate 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

  Further, a detection signal from the ball lending count switch 301B is input to the input port 372b of the payout control board 37 via the relay board 72. The ball lending count switch 301B is provided in the lower part of the ball dispensing device 97, and detects a lending ball actually paid out. A drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 via the output port 372c and the relay board 72. The game ball is paid out in accordance with the rotation of the payout motor 289.

  A ball distribution member is provided below the ball dispensing device 97. The ball distribution member is driven by a distribution solenoid 310. For example, when the solenoid 310 is on, the ball sorting member falls to the right side, and when it is off, the ball sorting member falls to the left side. Below the sorting solenoid 310, a prize ball count switch 301A and a ball lending count switch 301B by proximity switches are provided. At the time of winning a ball based on winning, the ball sorting member falls to the right, and the paid-out game ball passes the winning ball count switch 301A. At the time of lending a ball, the ball distribution member falls to the left side, and the paid-out game ball passes through the ball lending count switch 301B. Accordingly, the ball payout device 97 can change the payout flow path between the winning ball and the ball lending and pay out a predetermined number of game media.

  The payout control CPU 371 is supplied with a reset signal and a power-off signal from the power supply board 910. When the reset signal is at a low level, the payout control CPU 371 is in a reset state, and when the reset signal is at a high level, the payout control CPU 371 is in an operable state. When the power-off signal is in a state indicating that the power-supply voltage has become a predetermined value or less, the payout control CPU 371 executes a power-off process described later.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal ( PRDY signal) is exchanged via the I / O port 372f.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37.

  When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37. Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. At this time, the sorting solenoid 310 is in a driving state. That is, the ball distribution member is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed.

  As described above, the signal from the card unit 50 is input to the payout control board 37 that is directly connected to the card unit 50. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31.

  Further, the card balance display signal and the ball lending possible display signal indicating the balance of the prepaid card are transmitted to the balance display board 74 without going through the payout control CPU 371. The ball lending switch signal and the return switch signal sent from the balance display board 74 are also transmitted to the card unit 50 without going through the payout control CPU 371.

  In this embodiment, the case where the card unit 50 is provided is taken as an example. However, the present invention can also be applied to a case where a game ball corresponding to the amount of money is lent according to coin insertion. Further, in this embodiment, a case where a game ball is lent is taken as an example, but the present invention can be applied even if a score is added.

  In this embodiment, at least a part or all of the RAM in the main board 31 and the payout control board 37 is backed up by a backup power source. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are saved for a predetermined period. When each CPU detects a decrease in power supply voltage, it performs a predetermined process and waits for power recovery. Further, when the power is turned on, each CPU restores the state before the power is turned off based on the stored data when the data is stored in the RAM.

  In addition, in order to send commands to the payout control board 37, the display control board 80, the lamp control board 35, and the voice control board 70, an INT signal is sent from the output port (output port 0) 570 of the main board 31 to each electric component control board. Is output. In this case, for example, the output port 570 has an 8-bit configuration, where bit 0 is an INT signal to the payout control board 37, bit 1 is an INT signal to the display control board 80, and bit 2 is an INT signal to the lamp control board 35. The signal, bit 3, is used for outputting the INT signal to the audio control board 70.

  FIG. 6 shows the circuit configuration in the display control board 80. The LCD (Liquid Crystal Display) 82, the variable display 10, and the output port (ports 0 and 2) 570 of the main board 31 are examples of realizing the variable display unit 9. , 572 and the output buffer circuits 620 and 62A. The output port (output port 2) 572 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal).

  A reset signal is supplied from the power supply substrate 910 to the display control CPU 101. When the reset signal is at a low level, the display control CPU 101 is in a reset state, and when the reset signal is at a high level, the display control CPU 101 is in an operable state.

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When an INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, display control is performed via the input buffer circuit 105A. Receive commands. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the LCD 82 according to the input data, and outputs R, G, B signals and a synchronization signal to the LCD 82.

  6 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the LCD 82.

  The input buffer circuits 105 </ b> A and 105 </ b> B can pass signals only in the direction from the main board 31 toward the display control board 80. Therefore, there is no room for signals to be transmitted from the display control board 80 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute irreversible information input means together with the input ports. Even if the tampering is added to the circuit in the display control board 80, the signal output by the tampering is not transmitted to the main board 31 side.

  The outputs of the output ports 570 and 572 may be output to the display control board 80 as they are, but by providing the output buffer circuits 620 and 62A capable of transmitting signals only in one direction, the main board 31 and the display control board 80 are provided. One-way signal transmission can be made more reliable. That is, the output buffer circuits 620 and 62A constitute irreversible information output means together with the output ports.

  In addition, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added to the display control command between the substrates due to the presence of the noise filter 107, the influence is removed. Is done. A noise filter may also be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

  FIG. 7 is a block diagram showing signal transmission / reception portions in the main board 31 and the lamp control board 35. In this embodiment, the game effect LED 28a, the game effect lamps 28b and 28c provided on the outside of the game area 7, and the decoration lamp 25 provided on the game board are turned on / off, and the prize ball lamp 51 and the ball are out of play. A lamp control command indicating turning on / off of the lamp 52 is output from the main board 31 to the lamp control board 35. Further, a lamp control command indicating the number of lighting of the start memory display 18 and the gate passing memory display 41 is also output from the main board 31 to the lamp control board 35.

  A reset signal is supplied from the power supply board 910 to the lamp control CPU 351. When the reset signal is at a low level, the lamp control CPU 351 is in a reset state, and when the reset signal is at a high level, the lamp control CPU 351 is in an operable state.

  As shown in FIG. 7, the lamp control command related to the lamp control is output from the output ports (output ports 0 and 3) 570 and 573 of the I / O port unit 57 in the basic circuit 53. The output port (output port 3) 573 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

  On the lamp control board 35, the lamp control CPU 351 has a game effect LED 28 a and a game effect lamp in accordance with the turn-on / off pattern of the game effect LED 28 a, game effect lamps 28 b and 28 c and the decoration lamp 25 defined according to each control command. 28b, 28c, and the decoration lamp 25 are turned on / off signals. The on / off signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  In the main board 31, the CPU 56 outputs a control command for instructing the lighting of the prize ball lamp 51 when there is an unpaid prize ball remaining in the stored contents of the RAM 55, and the above-mentioned payout ball passage 186 a, When the ball break switches 187a and 187b (see FIG. 3) installed upstream of 186b no longer detect a game ball, a control command is output to instruct the ball break lamp 52 to be lit. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 in accordance with these control commands. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  Further, the lamp control CPU 351 outputs a light on / off signal to the start memory display 18 and the gate passage memory display 41 in accordance with the control command.

  As the input buffer circuits 355A and 355B, for example, 74HC540 and 74HC14 which are general-purpose CMOS-ICs are used. The input buffer circuits 355A and 355B can pass signals only in the direction from the main board 31 toward the lamp control board 35. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the lamp control board 35, the signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

  In the main board 31, buffer circuits 620 and 63A are provided outside the output ports 570 and 573. As the buffer circuits 620 and 63A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

  FIG. 8 is a block diagram showing a configuration example of the voice control command signal transmission portion of the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing voice output from the speaker 27 provided outside the gaming area 7 is output from the main board 31 to the voice control board 70 as the game progresses.

  A reset signal is supplied from the power supply board 910 to the audio control CPU 701. When the reset signal is at a low level, the voice control CPU 701 is in a reset state, and when the reset signal is at a high level, the voice control CPU 701 is in an operable state.

  As shown in FIG. 8, the voice control command is output from the output ports (output ports 0 and 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53. The output port (output port 4) 574 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the audio control board 70, each signal from the main board 31 is input to the audio control CPU 701 via the input buffer circuits 705A and 705B. When the audio control CPU 701 does not have an I / O port, an I / O port is provided between the input buffer circuits 705A and 705B and the audio control CPU 701.

  Then, for example, a voice synthesis circuit 702 using a digital signal processor generates voice and sound effects according to instructions from the voice control CPU 701 and outputs them to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the audio control CPU 701 to a level corresponding to the set volume and outputs the level to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

  As the input buffer circuits 705A and 705B, for example, 74HC540 and 74HC14, which are general-purpose CMOS-ICs, are used. The input buffer circuits 705A and 705B can pass signals only in the direction from the main board 31 toward the audio control board 70. Therefore, there is no room for signals to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if unauthorized modification is added to the circuit in the voice control board 70, a signal output by the unauthorized modification is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

  In the main board 31, buffer circuits 620 and 67A are provided outside the output ports 570 and 574. As the buffer circuits 620 and 67A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to further reliably eliminate a signal line from which a signal may be given from the voice control board 70 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

  FIG. 9 is a block diagram showing a launch control board 91 on which a payout control board 37 and control means for controlling the hitting ball are mounted. As shown in FIG. 9, the launch control signal is output to the launch control board 91 from the output port 372 d in the payout control board 37. In the launch control board 91, the launch control signal from the payout control board 37 is input to the motor drive circuit 813 via the buffer circuit 815.

  The motor drive circuit 813 generates, for example, a voltage that controls the rotational speed of the drive motor 94 in each period of a ball hitting operation for launching a game ball and a recovery / ball supply operation that is preparation for launching the next game ball. In the ball hitting operation period, a voltage that gradually increases corresponding to the rotation operation angle with respect to the operation knob 5 is generated, and in the recovery / ball supply operation period, a predetermined voltage is generated in advance.

  The touch sensor circuit 93 outputs a firing permission signal to the motor drive circuit 813 while the human body is in contact with the human body detection electrode attached to the operation knob 5. Further, the motor drive circuit 813 is given a firing control signal from the payout control board 37. When the firing control signal and the firing permission signal are turned on, the motor drive circuit 813 controls switching of the sequence operation during the ball hitting operation period and the recovery / ball replenishment operation period, and the drive pattern signal necessary for driving the drive motor 94 and A drive voltage switching signal is generated.

  FIG. 10 is a block diagram showing DC voltage and the like supplied from the power supply board 910 to each board. As shown in FIG. 10, a power supply circuit that generates various DC voltages is mounted on the power supply board 910. Moreover, AC24V is also supplied to each board | substrate as needed.

  In this embodiment, the main board 31 is supplied with DC30V, DC12V, DC5V and a backup power supply voltage (VBB). The lamp control board 35 is supplied with DC30V, DC21V, DC12V and DC5V. The payout control board 37 is supplied with AC24V, DC30V, DC12V, DC5V and backup power supply voltage (VBB). The launch control board 91 is supplied with DC30V, DC12V, and DC5V. The audio control board 70 is supplied with DC12 and DC5V. The display control board 80 is supplied with DC12V and DC5V. Further, a reset signal is supplied to each board from the power board 910.

  As shown in FIG. 10, the ground side of the voltage supplied to each substrate is commonly used in the power supply substrate 910. Therefore, the ground level in each substrate is common. Then, the voltage level can be used as it is as a signal transmitted from one substrate to another substrate. If there is a substrate whose ground level is not shared, in order to transmit signals to such a substrate, it is necessary to use a non-contact type information transmission means such as a photocoupler, which causes an increase in cost. However, when the ground level of all the substrates is shared as in this embodiment, it is not necessary to use a photocoupler or the like.

  FIG. 11 is a block diagram illustrating a configuration example of the power supply board 910 of the gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and each electric component control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 21V, + 12V, and + 5V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board.

  However, each connector reaching each electric component control board may be provided on the power supply board 910 to supply each voltage from the power supply board 910 to each board without going through the relay board.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. Capacitor 916 has power so that the storage state can be maintained with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is cut off (RAM that is backed up by power, that is, storage means that can be in the storage content storage state). Backup power supply. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  Further, a power supply monitoring IC 902 is mounted on the power supply board 910. The power monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output because the power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. The voltage drop signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed.

  Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the switch output becomes the power It is possible to enter a state of waiting for recovery and not detect switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 that is separate from the electrical component control board, a voltage drop signal can be supplied from the power monitoring circuit to the plurality of electrical component control boards. Even if there are any number of electrical component control boards that require a voltage drop signal, it is only necessary to provide one first power supply monitoring means. Therefore, each electrical component control means in each electrical component control board performs the return control described later. Even if it goes, the cost of the gaming machine does not rise so much.

  In the configuration shown in FIG. 11, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. However, for example, a configuration may be adopted in which one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board. Further, a buffer circuit corresponding to the number of substrates that require a voltage drop signal may be provided.

  Further, a reset management circuit 940 that supplies a reset signal to each board is mounted on the power supply board 910.

  FIG. 12 is a block diagram illustrating a configuration example of the reset management circuit 940. In the reset management circuit 940, the reset IC 651 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor when the power is turned on, and sets the output to the high level when the predetermined time elapses. The output of the reset IC 651 is supplied to the buffer circuits 961 to 964 and the delay circuit 960 via the circuits 941 to 949. The output of the delay circuit 960 is input to the buffer circuit 965. Then, the buffer circuits 961 to 965 are supplied as reset signals to the electric component control boards. Therefore, when the output of the reset IC 651 becomes high level, the CPU in each electric component control board becomes operable.

  The reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the power supply monitoring IC 902, and the voltage value is a predetermined value (from the power supply voltage value at which the power supply monitoring IC 902 outputs a voltage drop signal). (Low value) or less, it becomes low level. Therefore, the CPU 56 and the payout control CPU 371 are subjected to a predetermined power supply stop preparation process in response to a voltage drop signal (power-off signal) from the power monitoring IC 902, and then the system is reset.

  As shown in FIG. 12, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946.

  The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is supplied to each CPU via the buffer circuits 961 to 965. According to such a configuration, when the power is turned on, two reset signals (low level signals) are given to the reset terminal of each CPU, so that each CPU starts its operation reliably.

  For example, the detection voltage of the power supply monitoring IC 902 that is the first power supply monitoring circuit (voltage that outputs a voltage drop signal) is set to +22 V, and the detection voltage of the reset IC corresponding to the second power supply monitoring circuit is set to + 22V. + 9V. In such a configuration, since the first power monitoring circuit and the second power monitoring circuit monitor the voltage of the same power supply VSL, the timing when the first voltage monitoring circuit outputs the voltage drop signal. And the timing at which the second voltage monitoring circuit outputs the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from the start of the power supply stop preparation process according to the voltage drop signal from the first power supply monitoring circuit until the completion of the power supply stop preparation process with certainty.

  In this example, the first detection condition for the first power supply monitoring means to output the detection signal is that the + 30V power supply voltage has dropped to + 22V, and the second power supply monitoring means outputs the detection signal. The second detection condition that becomes is that the + 30V power supply voltage is lowered to + 9V. However, the voltage value used here is an example, and other values may be used.

  However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 and the payout control CPU 371 of the main board 31 and the payout control board 37, at least a part of the RAM is backed up by the backup power supply supplied from the power supply board 910. Even if the power to the gaming machine is cut off, the contents are preserved. When the + 5V power supply is restored, the reset signal from the reset management circuit 940 goes high, so that the CPU 56 and the payout control CPU 371 return to the normal operating state. At that time, since necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of occurrence of the power failure when recovering from the power failure.

  FIG. 12 shows a configuration in which a reset signal (low level signal) is given twice to the reset terminal of the CPU of each electrical component control board when the power is turned on. However, there is only one rise timing of the reset signal. However, when using a CPU that reliably releases reset, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the buffer circuits 961 to 964 and the delay circuit 960.

  In this embodiment, a reset signal is supplied from the power supply board 910 to the CPU of each electrical component control board. The delay circuit 960 delays a reset signal for the CPU 56 of the main board 31. Therefore, when the power is turned on, the reset signal for the CPU 56 of the main board 31 rises later than the reset signals for the CPUs of other electrical component control boards.

  For example, when the CPU 56 of the main board 31 outputs a control command to another electric component control board, since the CPU in the other electric component control board has already started, the control command is surely received on the electric component on the receiving side. Received by the CPU of the control board.

  FIG. 13 is a timing chart showing the state of output signals from the reset IC 651 of the reset management circuit 940 and its peripheral ICs. As shown in FIG. 13, the output of the reset IC 651 is that the level of the power supply voltage is a predetermined value (a level at which normal operation of each CPU can be ensured; in this example, each CPU can operate at +5 V, for example, +9 V). If it exceeds, it becomes high level. When the output of the reset IC 651 becomes a high level, the counter IC 941 is released from the clear state, and thus the counter IC 941 starts counting the output clock signal of the oscillator 943. The oscillation frequency of the oscillator 943 is, for example, 11.776 MHz.

  When the counter IC 941 counts 16 clocks, the Q5 output rises. Further, when 32 clocks are counted, the Q6 output rises to a high level. When the Q6 output of the counter IC 941 rises, the output of the FF 942 becomes high level. The IC 947 inverts the logical product of the Q6 output of the counter IC 941 and the output of the reset IC 651. The OR circuit 949 calculates the logical sum of the output of the IC 948 that inverts the output of the IC 947 and the output of the FF 942, and outputs a signal as shown in FIG.

  The buffer circuits 961 to 964 pass the output of the IC 949 as they are and output them as reset signals to CPUs other than the CPU 56 of the main board 31. Further, the buffer circuit 965 outputs a signal obtained by delaying the output of the IC 949 to the CPU 56 of the main board 31 as a reset signal.

  Therefore, when the gaming machine is turned on, as shown in FIG. 13 as IC 961-964 output and IC 965 output, the reset terminal of each CPU is once in a reset release state (high level) and then reset again (low level). ) Is supplied. That is, when the power is turned on, a low level signal that causes each CPU to be reset is generated twice. It can also be said that a high level indicating reset release has occurred twice. As a result, each CPU can be reliably started up by the second change from the low level to the high level even if it is not started up by the change from the low level to the high level indicating the first reset release. Therefore, game control is surely started when the gaming machine is powered on.

  As shown in FIG. 13, the timing at which the reset signal to the main board 31 is in the reset release state is later than the timing at which the reset signals to other boards are in the reset release state. Therefore, when the CPU 56 of the main board 31 outputs a control command to the other electric component control board, the CPU on the other electric component control board has already started up, so that the control command is surely received on the electric component on the receiving side. Received by the CPU of the control board.

  In this case, the reset management circuit 940 performs control so as to shift the reset release timing given to the main board 31 and the reset release timing sent to the other plurality of electric component control boards. It is also easy to shift the reset release timing given to the component control board. For example, in the circuit configuration shown in FIG. 12, if a delay circuit is placed in front of the buffer circuits 961 to 964 and a difference is provided between the delay amounts of the respective delay circuits, it is given to the main board 31 and other electric component control boards. A difference can be made between each reset release timing. That is, each electric component control means can be started in a predetermined order.

  When each of the electrical component control boards is configured to generate a reset signal used by itself, it is difficult to adjust the reset release timing of each reset signal, but in this embodiment, the power supply board 910 is used. Since the reset management circuit 940 in FIG. 10 collectively generates reset signals for the respective substrates, the startup sequence control can be easily adjusted.

  In this embodiment, the startup management unit as illustrated in FIG. 12 is mounted on the power supply board 910. However, a startup management board on which the startup management unit is mounted may be provided separately. However, since the reset signal is generally created by using the rise of the power supply voltage, there is an advantage that each reset signal can be created more easily when the power supply board 910 is used as a startup management board.

Next, the game control operation will be described.
FIG. 14 is a flowchart showing main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on and the reset of the CPU 56 is released, in the main process, the CPU 56 first performs necessary initial settings (step S1).

  Then, it is confirmed whether or not data protection processing of the backup RAM area (for example, power supply stop preparation processing such as addition of parity data) has been performed when the power is turned off (step S2). In this embodiment, when an unexpected power failure occurs, a power supply stop preparation process for protecting data in the backup RAM area is performed. When such processing is performed, it is assumed that there is a backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3).

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state). “55H” set in the backup flag area is data set when the data protection process of the backup RAM area is completed in the power supply stop preparation process, and is a parity code based on the data in the backup RAM area.

  When there is backup data in the backup RAM area, the CPU 56 performs data check (for example, parity check) in the backup RAM area (step S4). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state when the power is cut off, and therefore an initialization process that is executed when the power is turned on not when the power failure is restored is executed (steps S5 and S3).

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state to the state at the time of power-off (step S6). As shown in FIG. 15, when the value of the backup flag is set to “55H” and the check result is normal, the gaming state recovery process in step S6 is executed. Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored (step S7).

  When the execution of the normal initialization process (step S3) is completed, the main process proceeds to a loop process in which the monitoring of the timer interrupt flag (step S9) is confirmed. In the loop, display random number update processing (step S8) is also executed.

  In this embodiment, after the presence or absence of backup data is confirmed in step S2, the backup area is checked in step S4 when the backup data exists. Conversely, the check result of the backup area is After it is confirmed that the data is normal, the presence / absence of backup data may be confirmed. Further, it may be determined whether or not to execute the power failure recovery processing by confirming either one of the presence / absence of backup data or the check of the backup area.

  Further, for example, in the parity check (step S4) when determining whether or not to execute the power failure recovery process, that is, when determining whether or not to restore the gaming state, a special process in the stored RAM data If it is confirmed that the gaming machine is in a game standby state (not changing in design, not in big hit game, not in probable change, or without starting prize memory) by flag or the like and starting winning memory data The initialization process may be executed without performing the game state restoration process.

  FIG. 16 is a flowchart showing the initial setting process in step S1. In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1a). When the interrupt is prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designation address in the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d). Further, after initialization (step S1e) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set to an accessible state (step S1f).

  The CPU 56 used in this embodiment has the following three types of maskable interrupt (INT) modes. If interrupt mode 2 is set, interrupt requests from each built-in device can be easily processed, and interrupt processing can be set at an arbitrary position in the program. . When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  FIG. 17 is a flowchart showing the normal initialization process (step S3). As shown in FIG. 17, in the initialization process, a RAM clear process is performed (step S3a). Next, based on the address value of the work area initial setting table, it is initialized to a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) An initial value setting process (step S3b) for setting a value is performed.

  Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S3c). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interrupt is prohibited (see FIG. 16) in the initial setting process (step S1), the interrupt is permitted before the initialization process is completed (step S3d).

  Therefore, in this embodiment, the built-in CTC of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 18, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

  When detecting that the timer interrupt flag is set in step S9, the CPU 56 resets the timer interrupt flag (step S10) and executes a game control process (step S11). With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process, but the game control process may be executed in the timer interrupt process.

  FIG. 19 is a flowchart showing the game control process of step S11. In the game control process, the CPU 56 first inputs the states of the gate sensor 12, the start port sensor 17, the count sensor 23, and the winning port switches 19a and 24a via the switch circuit 58, and wins each winning port and winning device. It is determined whether or not there has been (switching process: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state.

  Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Furthermore, the CPU 56 sets a control command sent to the payout control board 37 or the like in a predetermined area of the RAM 55 and performs a process of sending the control command to each electric component control board (command control process: step S27). .

  Next, the CPU 56 performs a data output process for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is established (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in accordance with the drive command, thereby bringing the variable winning ball device 15 or the opening / closing plate 20 into an open state or a closed state.

  Then, the CPU 56 performs setting of the number of winning balls based on the detection output of the switches 17, 23, 19a, 24a for detecting winning in each winning opening (step S31). Specifically, a payout control command is output to the payout control board 37 in response to winning detection. The payout control CPU 371 mounted on the payout control board 37 drives the prize ball payout device 97A in accordance with the payout control command.

  As described above, the main process includes a process for determining whether or not to shift to the game control process, and the timer control process based on the timer interrupt periodically generated by the internal timer of the CPU 56 is used for the game control process. Since a flag for determining whether or not to shift is set, all the game control processes are executed reliably. In other words, until all the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all the processes in the game control process are completed. ing.

  Here, the game control process executed by the CPU 56 of the main board 31 is executed according to the flag set in the timer interrupt process based on the timer interrupt that the internal timer of the CPU 56 periodically generates. A hardware circuit that generates a signal periodically (for example, every 2 ms) is provided, a signal from the circuit is introduced into an external interrupt terminal of the CPU 56, and it is determined whether or not to shift to a game control process by the interrupt signal. A flag may be set for this purpose.

  FIG. 20 is a flowchart illustrating an example of a power failure occurrence NMI process executed in response to the NMI based on the power-off signal from the power supply board 910. In the power failure occurrence NMI process, the CPU 56 first stores the contents of the interrupt prohibition flag in the parity flag in order to back up the interrupt permission / prohibition state immediately before the power failure such as a power failure (step S41).

  Next, interrupt prohibition is set (step S42). In the power failure occurrence NMI processing, checksum generation processing is performed to ensure the storage of the RAM contents. If another interrupt process is performed during that process, it is possible that the CPU will not operate before the checksum generation process is completed. Setting is made so as not to occur. Note that steps S44 to S50 in the power failure occurrence NMI process are an example of a power supply stop preparation process. Further, when a CPU having a specification that does not cause other interrupts during the interrupt process is used, the process of step S42 is not necessary.

  Next, the CPU 56 checks whether or not the backup flag has already been set (step S42). If the backup flag is already set, no further processing is performed. If the backup flag is not set, the following power supply stop preparation process is executed. That is, the processing from step S44 to step S50 is executed.

  First, the contents of each register are stored in the backup RAM area (step S44). Thereafter, a backup flag is set (step S45). Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S46), the exclusive value is sequentially obtained for the initial value and the data in the backup RAM area, and then inverted (step S47). The calculated value is set in the backup parity data area (step S48). Further, the RAM access is prohibited (step S49). When the power supply voltage is lowered, the level of various signal lines may become unstable and the contents of the RAM may be altered, but if the RAM access is prohibited in this manner, the data in the backup RAM will be altered. There is no.

  Further, the CPU 56 outputs a clear signal to all output ports mounted on the main board 31. Then, all the output ports are cleared by a clear signal and turned off (step S50).

  Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the reset signal from the reset management circuit 940 becomes a low level and the operation is prohibited, the operation is internally stopped. Therefore, the CPU 56 reliably stops operation when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the RAM contents from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

  In this embodiment, in the power failure occurrence NMI processing, the program is looped at the final part, but a halt (HALT) instruction may be issued.

  Further, as described above, the backup flag that is set after the register contents are stored in the RAM area determines whether or not there is backup data to be restored when the power is turned on (whether or not it is restored from a power failure). Used when. Further, the processing of steps S41 to S50 is completed before the CPU 56 receives the system reset signal from the system reset circuit 65. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before receiving the system reset signal from the system reset circuit 65.

  In this embodiment, the backup flag is confirmed at the start of the power supply stop preparation process. If the backup flag is already set, the power supply stop preparation process is not executed. As described above, the backup flag is a flag indicating that the necessary data backup has been completed and the power supply stop preparation process has been completed. Therefore, for example, even if NMI occurs again for some reason in a loop waiting for resetting, the power supply stop preparation process is not executed repeatedly.

  However, if a CPU with specifications that do not cause other interrupts during interrupt processing is used, the determination in step S43 is unnecessary.

  FIG. 21 is an explanatory diagram for explaining an example of a backup parity data creation method. However, in the example shown in FIG. 21, the size of the data in the backup data RAM area is 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 21, initial data (00H in this example) is set in the backup check data area. Next, an exclusive logical sum of “00H” and “F0H” is taken, and an exclusive logical sum of “16H” is obtained. Further, an exclusive OR of the result and “DFH” is taken. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

  When power is turned on again, parity diagnosis is performed in the power failure recovery process. If all the data in the backup area is stored as it is, data as shown in FIG. 21 is set in the backup area when the power is turned on again.

  In the process of step S4, the CPU 56 performs the same process as the process executed in the power generation MNI process. That is, initial data (00H in this example) is set in the backup check data area, an exclusive OR of “00H” and “F0H” is taken, and an exclusive OR of “16H” is taken with the result. . Further, an exclusive OR of the result and “DFH” is taken. Then, a final calculation result obtained by inverting the result (“39H” in this example) is obtained. If all the data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is not “C6H”.

  Therefore, the CPU 56 compares the final calculation result with the data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

  As described above, in this embodiment, the game control means is provided with a storage means (a backup RAM in this example) that is backed up for a predetermined period even when the power of the gaming machine is cut off. The CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state recovery process (step S6) for recovering the game state based on the backup data if the storage means is in the backup state.

  In this embodiment, in the power supply board 910, the power monitoring IC 902 and the reset management circuit 940 monitor the same power supply voltage, but may monitor different power supply voltages. For example, the power monitoring IC 902 may monitor the + 30V power supply voltage, and the reset management circuit 940 may monitor the + 5V power supply voltage. The threshold of the system reset circuit 65 is set so that the timing at which the reset management circuit 940 sets the reset signal to a low level is later than the timing at which the power monitoring IC 902 generates the NMI interrupt signal (power-off signal). The level (voltage level that generates the system reset signal) is set. For example, the threshold is 4.25V. 4.25 V is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while.

  In the above embodiment, the CPU 56 detects the NMI interrupt signal (NMI interrupt signal from the power monitoring means) from the power supply board via the non-maskable interrupt terminal (NMI terminal). An interrupt signal may be introduced to a maskable interrupt interrupt terminal (IRQ terminal). In that case, a power supply stop preparation process is executed in the interrupt process (IRQ process). Further, an NMI interrupt signal from the power supply board may be detected via the input port. In that case, the input port is monitored in the main process.

  When an interrupt signal from the power supply board is detected via the IRQ terminal instead of the NMI interrupt signal, the IRQ interrupt mask is set at the start of the game control process in step S11 of the main process, and the game control The IRQ interrupt mask may be canceled at the end of processing. By doing so, an interruption is applied before and after the start of the game control process, and the game control process is not interrupted. Therefore, the command transmission is not interrupted when the payout control command is sent to the payout control board 37. Therefore, even when a power failure occurs, the payout control command and the like are reliably transmitted.

  FIG. 22 is a flowchart showing main processing of the payout control CPU 371. In the main process, the payout control CPU 371 first performs necessary initial settings (step S701).

  Then, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S702). That is, for example, similarly to the processing of the CPU 56 of the main board 31, whether or not backup data exists is confirmed by whether or not the backup flag that is set when the power is turned off is set. If the backup flag is set, it is determined that there is backup data. If it is determined that there is no backup data, there is no unpaid game ball at the previous power-off, and there is no need to return the internal state to the state at the time of power-off. Accordingly, the payout control CPU 371 executes an initialization process that is executed when the power is turned on but not when the power failure is restored (steps S702 and S703).

  When backup data exists in the backup RAM area, the payout control CPU 371 performs data check (parity check in this example) of the backup RAM area (step S704). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power-off, and therefore an initialization process that is executed at the time of power-on not at the time of power failure recovery is executed (steps S705 and S703).

  If the check result is normal, the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power is turned off (step S706). Then, it returns to the address indicated by the PC (program counter) stored in the backup RAM area (step S707).

  When execution of the normal initialization process (step S703) is finished, the main process executed by the payout control CPU 371 shifts to a loop process in which the monitoring of the timer interrupt flag (step S708) is confirmed.

  In this embodiment, after the presence / absence of backup data is confirmed in step S702, the backup area is checked in step S704 when the backup data exists. After confirming that the data is normal, the presence / absence of backup data may be confirmed. In addition, it may be configured to determine whether or not to execute the power failure recovery process by confirming either one of the presence / absence of backup data or the check of the backup area.

  Also, for example, when performing parity check (step S704) when determining whether or not to execute a power failure recovery process, that is, when determining whether or not to restore the gaming state, payout in the stored RAM data If it is confirmed from the game ball number data or the like that the gaming machine is in a payout waiting state (a state that is not in the middle of payout), the initialization process may be executed without performing the payout state recovery process.

  In the normal initialization process, as shown in FIG. 23, a register and RAM clear process (step S901) is performed, and a predetermined initial value is set (step S902). Then, interrupts are permitted before the initialization process is completed (step S903).

  In this embodiment, the built-in timer / counter of the payout control CPU 371 is set to repeatedly generate a timer interrupt. Further, the repetition period is set to 2 ms. Then, as shown in FIG. 24, when a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag (step S711). In FIG. 24, it is clearly indicated that the interrupt is permitted (step S710). In the 2 ms timer interrupt process, the interrupt permission state is first set. That is, the interrupt is permitted during the 2 ms timer interrupt process.

  When detecting that the timer interrupt flag is set in step S708, the payout control CPU 371 resets the timer interrupt flag (step S709) and executes a payout control process (step S710). With the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the payout control process is executed in the main process, but the payout control process may be executed in the timer interrupt process.

  When the power is turned on, the payout control CPU 371 can determine whether to perform normal initial setting processing or restore the paying-out state only by checking the data in the backup RAM area. That is, the payout process can be resumed for the game balls that have not been paid out by simple determination. Further, in this embodiment, as with the game control in the main board 31, the stored content is ensured by the parity check code.

  FIG. 25 is a flowchart showing the payout control process in step S710. In the payout control process, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 are turned on (switch process: Step S751).

  Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor that detects the rotation speed of the payout motor 289) and determining the state of the sensor (input determination processing). : Step S752). The payout control CPU 371 further analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S753).

  Next, the payout control CPU 371 sets the payout stop state if the payout stop instruction command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). Further, a prepaid card unit control process is performed (step S755).

  Further, the payout control CPU 371 performs control for paying out the rental balls in response to the ball rental request (step S756). Further, the payout control CPU 371 performs a prize ball control process for paying out a predetermined prize ball (step S757). Then, the payout control CPU 371 outputs a drive signal to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the ball lending control process in step S756 or the step S757. A payout motor control process for rotating the payout motor 289 by the number of rotations set in the prize ball control process is performed (step S758).

  In this embodiment, a stepping motor is used as the payout motor 289, and a 1-2 phase excitation method is used to control the payout motor 289. Therefore, specifically, eight types of excitation pattern data are repeatedly output to the payout motor 289 in the payout motor control process. In this embodiment, each excitation pattern data is output by 4 ms.

  Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759).

  Further, a process of outputting an information signal to the terminal board 160 is performed (output process: step S760). The information signal is a signal that is turned on for a predetermined time for each lending ball payout unit (for example, 25) and subsequently outputs OFF for a predetermined time.

  FIG. 26 is a flowchart showing an example of a power failure occurrence NMI process executed in response to the NMI based on the power-off signal from the power supply monitoring IC 902 of the power supply board 910. In the power failure occurrence NMI process, the payout control CPU 371 first stores the contents of the interrupt prohibition flag in the parity flag (step S801). Next, interrupt prohibition is set (step S802).

  In the power failure occurrence NMI process, a checksum generation process for ensuring the storage of the RAM contents is performed as in the process executed on the main board 31. If another interrupt process is performed during the process, it may be possible that the checkout generation process is not completed before the payout control CPU 371 drops to a voltage at which it cannot operate. The setting is made so that no other interruption occurs. Note that steps S804 to S810 in the power failure occurrence NMI process are an example of a power supply stop preparation process.

  Note that the processing in step S802 is not necessary when a CPU having a specification that does not cause other interrupts during the interrupt processing is used.

  Next, the payout control CPU 371 checks whether or not the backup flag has already been set (step S803). If the backup flag is already set, no further processing is performed. If the backup flag is not set, the following power supply stop preparation process is executed. That is, the processing from step S804 to step S810 is executed.

  First, the contents of each register are stored in the backup RAM area (step S804). Thereafter, a backup flag is set (step S805). Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S806), the exclusive value is sequentially obtained for the initial value and the data in the backup RAM area, and then inverted (step S807). The calculated value is set in the backup parity data area (step S808). In addition, the RAM access is prohibited (step S809). When the power supply voltage is lowered, the level of various signal lines may become unstable and the contents of the RAM may be altered, but if the RAM access is prohibited in this manner, the data in the backup RAM will be altered. There is no.

  Further, the payout control CPU 371 outputs a clear signal to all output ports. Accordingly, all the output ports are turned off by the clear signal (step S810).

  Next, the payout control CPU 371 enters a loop process. That is, no processing is performed. Therefore, before the reset signal from the reset management circuit 940 becomes a low level and the operation is prohibited, the operation is internally stopped. Therefore, the payout control CPU 371 reliably stops operation when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the RAM contents from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

  In this embodiment, in the power failure occurrence NMI processing, the program is looped at the final part, but a halt (HALT) instruction may be issued.

  Further, as described above, the backup flag that is set after the register contents are stored in the RAM area determines whether or not there is backup data to be restored when the power is turned on (whether or not it is restored from a power failure). Used when. Further, the processing of steps S801 to S810 is completed before the payout control CPU 371 reaches a low level from the reset signal from the power supply board 910. In other words, the detection voltage is set in the voltage monitoring IC 902 of the power supply board 910 so that the reset signal from the power supply board 910 is completed before the reset signal indicates the reset state.

  In this embodiment, the backup flag is confirmed at the start of the power supply stop preparation process. If the backup flag is already set, the power supply stop preparation process is not executed. As described above, the backup flag is a flag indicating that the necessary data backup has been completed and the power supply stop preparation process has been completed. Therefore, for example, even if NMI occurs again for some reason in a loop waiting for resetting, the power supply stop preparation process is not executed repeatedly.

  However, if a CPU with a specification that does not cause other interrupts during interrupt processing is used, the determination in step S803 is not necessary.

  In this embodiment, the payout control CPU 371 detects the NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) via the non-maskable external interrupt terminal (NMI terminal). The NMI interrupt signal may be introduced to a maskable interrupt terminal (IRQ terminal). In that case, the power failure occurrence NMI process shown in FIG. 26 is executed by the IRQ process. Further, an NMI interrupt signal may be detected via the input port. In that case, the input port is monitored in the main process executed by the payout control CPU 371.

  FIG. 27 is an explanatory diagram for explaining an example of a backup parity data creation method. However, in the example shown in FIG. 27, for the sake of simplicity, the size of the data in the backup data RAM area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 27, initial data (00H in this example) is set in the backup check data area. Next, an exclusive logical sum of “00H” and “F0H” is taken, and an exclusive logical sum of “16H” is obtained. Further, an exclusive OR of the result and “DFH” is taken. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

  When power is turned on again, parity diagnosis is performed in the power failure recovery process. If all the data in the backup area is stored as it is, data as shown in FIG. 27 is set in the backup area when the power is turned on again.

  In the process of step S704, the payout control CPU 371 performs the same process as the process executed in steps S806 and S807 of FIG. That is, initial data (00H in this example) is set in the backup check data area, an exclusive OR of “00H” and “F0H” is taken, and an exclusive OR of “16H” is taken with the result. . Further, an exclusive OR of the result and “DFH” is taken. Then, a final calculation result obtained by inverting the result (“39H” in this example) is obtained. If all the data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is not “C6H”.

  Therefore, the payout control CPU 371 compares the final calculation result with the data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

  Hereinafter, the payout state recovery process will be described. FIG. 28 is a flowchart showing an example of the payout state restoration process shown in step S706 of FIG. In this example, the payout control CPU 371 restores the value stored in the backup RAM to the register (step S861). And the process for recovering the payout state at the time of power failure is performed based on the data stored in the backup RAM. For example, an in-price ball processing flag is set.

  For example, when the number of unpaid winning balls, the number of unpaid rented balls, or both are stored in the backup RAM area when the power is restored, the payout process is restarted based on the stored number.

  As described above, in this embodiment, the payout control means is provided with a storage means (in this example, a backup RAM) that is backed up for a predetermined period of time even when the gaming machine is turned off. The payout control CPU 371 (specifically, the program executed by the payout control CPU 371) performs a payout state recovery process (step S706) for recovering the payout state based on the backup data if the storage means is in the backup state. Composed.

  In the configuration of the power supply board 910 illustrated in FIG. 11, a signal output from the power supply monitoring IC 902 is output as a power-off signal to the main board 31 via the buffer circuit 918, and the delay circuit 920 and the buffer circuit 919 are output. To the payout control board 37 as a power-off signal. Then, as shown in FIG. 29, when the power of the gaming machine is cut off, the power-off signal is supplied to the CPU 56 of the main board 31 earlier than the payout control CPU 371 of the payout control board 37.

  Therefore, as shown in FIG. 29, the CPU 56 of the main board 31 takes NMI earlier than the payout control CPU 371 of the payout control board 37. Since the power supply stop preparation process is started according to the NMI, at that time, the game control by the CPU 56 and the payout control by the payout control CPU 371 are stopped.

  That is, the fall management means mounted on the power supply board 910 performs sequence control such that the payout control means (value addition control means) is lowered after the game control means is lowered. Therefore, before the CPU 56 of the main board 31 outputs a control command to another electrical component control board, the CPU in the payout control means has not already fallen, and the control command from the main board 31 is received by the receiving side. There is no situation where the signal is not received by the CPU of the electrical component control board. In this embodiment, the fall management unit is realized by the power management IC 902, a reset management circuit 940 and a delay circuit 920 that can output a reset signal for stopping the operation of the control unit.

  Here, the fall management means controls the order of the fall between them by shifting the timing of the power cut signal given to the main board 31 and the power cut signal sent to the payout control means. Controlling the falling timing of the electrical component control board on which electrical component control means related to game effects such as a plurality of other electrical component control boards, for example, the display control board 70, the lamp control board 35, and the voice control board 80 are mounted. You can also. For example, in the circuit configuration shown in FIG. 12, a power-off signal may be output to the electrical component control board other than the main board 31 and the payout control board 371 via the buffer circuit.

  Then, if a delay circuit is placed in front of each buffer circuit and a difference is provided in the delay amount of each delay circuit, between each of the power-off signal output timings given to the main board 31 and other electric component control boards. You can make a difference. If the CPUs in the display control board 70, the lamp control board 35, the sound control board 80, etc. also stop the production control in response to the power-off signal, the electric component control means are lowered in a predetermined order. Will be able to.

  Further, as in this embodiment, the falling management unit in the power supply substrate 910 collectively manages the falling of the control unit in each substrate, so that the sequence control of the falling can be easily adjusted. For example, the falling order can be easily controlled by adjusting the delay amount of each delay circuit.

  In this embodiment, the fall management unit is mounted on the power supply board 910. However, the fall management unit including the fall management unit may be provided separately. However, since the signal for falling is generally generated by using the falling of the power supply voltage, when the falling management means is mounted on the power supply board 910, the falling management of each electric component control means is more controlled. There is an advantage that it can be easily performed.

  In the above embodiment, the start-up management unit manages the start-up sequence by adjusting the delay amount of the reset signal to each electrical component control unit, but the supply voltage supply start timing instead of the reset signal. It is also possible to manage the startup sequence by adjusting the.

  FIG. 30 is a block diagram illustrating a configuration example of a power supply board 910 on which a startup management unit that adjusts the supply start timing of the power supply voltage is mounted. In the embodiment shown in FIG. 30, the start of supply of + 30V, + 12V, + 5V and the backup power supply voltage to the main board 31 is delayed. That is, the delay circuit 971 delays the rise of the backup power supply voltage, and the delay circuit 972 delays the rise of + 5V. The delay circuit 973 delays the rise of + 12V, and the delay circuit 974 delays the rise of + 30V. The delay circuits 971, 972, 973, 974 can be realized by capacitors, for example.

  In FIG. 30, one connector 915 is shown, but a connector may be provided for each electrical component control board. In that case, for example, a connector for supplying various voltages to the main board 31, a connector for supplying various voltages to the lamp control board 35, and a connector for supplying various voltages to the payout control board 37. , A connector for supplying various voltages to the display control board 70, a connector for supplying various voltages to the sound control board 80, and a connector for supplying various voltages to the launch control board 91 are provided separately. It is done.

  Further, in the power supply board 910 shown in FIG. 30, only the rise of each voltage supplied to the main board 31 is delayed, so that only the rise of the game control means of the main board 31 is the rise of other electrical component control means. Later than. However, it is also possible to set the order of rising of each of the other electric component control means. For example, various voltages supplied to the lamp control board 35, the payout control board 37, the display control board 70, and the sound control board 80 are also supplied via the delay circuit, and the delay amount of each delay circuit can be provided with a difference. For example, the rise timing can be ordered among the game control means, the lamp control means, the payout control means, the display control means, and the sound control means.

  Furthermore, not all types of voltages used in the electrical component control board are subject to delay, but only power supply voltages used by the CPU may be subject to delay.

  FIG. 31 is a block diagram showing DC voltage and the like supplied to each substrate when the power supply substrate 910 shown in FIG. 30 is used. As shown in FIG. 30, various voltages reaching the main substrate 31 are supplied to the main substrate 31 after being delayed by the delay circuit.

  FIG. 32 is a block diagram showing still another embodiment of the rise management means. In the configuration shown in FIG. 32, a start-up management circuit 975 that outputs a start signal is mounted on the power supply board 910. Various voltages and reset signals are supplied from the power supply board 910 to the main board 31 and the sub board (the lamp control board 35, the payout control board 37, the display control board 70, and the voice control board 80) without delay.

  As illustrated in FIG. 33, when the reset signal indicates a reset release state, the CPU 56 of the main board 31 used in this embodiment first executes a security check program and then executes an initialization process. Further, when the reset signal indicates the reset release state, the CPUs of the sub-boards 35, 37, 70, and 80 enter a control state in which the control relating to the game effect is performed after the initialization process is executed. Then, the start-up management circuit 975 outputs an activation signal at the timing when the execution of the security check program of the CPU 56 is reliably completed. The activation signal is input to the input / output port 57 of the main board 31.

  When the CPU 56 of the main board 31 confirms that it has received an activation signal via the input / output port 57, it enters the game control state. Therefore, when the game control means enters the game control state, the CPUs of the sub-boards 35, 37, 70 and 80 are already in the control state. Therefore, for example, the control command sent from the main board 31 is reliably received by the CPUs of the sub boards 35, 37, 70 and 80.

  FIG. 34 is a block diagram showing still another embodiment of the rise management means. In the configuration shown in FIG. 34, a startup management circuit 976 that adjusts the rising timing of the reset signal for the main board 31 is mounted on the power supply board 910. Various voltages and reset signals are supplied from the power supply board 910 to the main board 31 and the sub board (the lamp control board 35, the payout control board 37, the display control board 70, and the voice control board 80) without delay.

  As shown in FIG. 35, when the reset signal indicates the reset release state, the CPUs of the sub-boards 35, 37, 70, and 80 output an operable signal after executing the initialization process. When the start-up management circuit 976 receives the operable signal, the start-up management circuit 976 raises a reset signal for the main board 31. In response to the rise of the reset signal, the main board 31CPU 56 enters the game control state after performing the initialization process. Therefore, when the game control means enters the game control state, the CPUs of the sub-boards 35, 37, 70 and 80 are already in the control state. Therefore, for example, the control command sent from the main board 31 is reliably received by the CPUs of the sub boards 35, 37, 70 and 80.

  In the configuration shown in FIG. 34, the start-up management circuit 976 may output an activation signal to the main board 31 when receiving the operable signal. In the case of such a configuration, the reset signal for the main board 31 enters the reset release state at the same timing as the reset signal for the sub boards 35, 37, 70, 80. In the main board 31, the activation signal from the power supply board 910 is input to the input / output port 57, and the CPU 56 enters the game control state when receiving the activation signal.

  In each of the above-described embodiments, the fall management unit performs the fall order management by adjusting the delay amount of the power-off signal to each electrical component control unit. It is possible to manage the shutdown of the electrical component control means.

  FIG. 36 is a block diagram showing another embodiment of the fall management means. In the configuration shown in FIG. 36, the fall management means is realized by a delay circuit 960 that delays a reset signal for the sub-boards 35, 37, 70, and 80. Note that the start-up management circuit 968 outputs a start signal to the main board 31 in response to the operable signals from the sub boards 35, 37, 70, and 80. In this embodiment, the CPUs of the main board 31 and the sub boards 35, 37, 70, 80 stop the control operation when the reset signal becomes low level.

  As shown in FIG. 37, the reset signal for the main board 31 rises earlier than the reset signals for the sub-boards 35, 37, 70, and 80. However, the CPU 56 of the main board 31 enters the gaming state only after receiving the activation signal. The start signal indicates an operable state when each CPU of the sub-boards 35, 37, 70, 80 enters the control state and outputs an operable signal. Therefore, when the CPU 56 of the main board 31 enters the game control state, that is, When starting up, the CPUs of the sub-boards 35, 37, 70 and 80 are already in the control state. That is, it has already stood up.

  When the power supply to the gaming machine is cut off and VSL becomes a predetermined value or less, the output of the reset IC 651 becomes low level. The output of the reset IC 651 is supplied to the main board 31 as it is, but is supplied to the sub-boards 35, 37, 70, and 80 via the delay circuit 960. Therefore, as shown in FIG. 37, the CPU 56 of the main board 31 falls earlier than the CPUs of the sub boards 35, 37, 70, 80.

  Therefore, for example, even when the game control means sends a control command to another electrical component control means immediately before the power is turned off, the control command is reliably received by the receiving electrical component control means. The

  In the configuration shown in FIG. 36, since the output of one delay circuit 960 is supplied to each sub-board 35, 37, 70, 80, the CPU of each sub-board 35, 37, 70, 80 falls simultaneously. However, if a delay circuit is placed in front of each of the buffer circuits 961 to 964 and a difference is provided between the delay amounts of the respective delay circuits, the order of lowering the main board 31 and the sub boards 35, 37, 70, and 80 will be described. Can be set arbitrarily.

  In the configuration shown in FIG. 36, since the output of the reset IC 651 is output as it is to the delay circuit 960 and the buffer circuit 965, one reset release operation (change from low level to high level) is performed when the power is turned on. However, ICs 941 to 949 as shown in FIG. 12 may be provided so that the reset release operation is performed twice.

  FIG. 38 is a block diagram showing another embodiment of the fall management means. In the configuration shown in FIG. 38, the fall management circuit 977 immediately cuts off various voltages supplied to the main board 31 via the switch circuit 978 when the output of the power monitoring IC 902 changes from high level to low level. . No particular control is performed on the various power supplies reaching the sub-boards 35, 37, 70, 80. Therefore, the voltage supplied to each sub-board 35, 37, 70, 80 maintains a potential at which each sub-board 35, 37, 70, 80 can operate for a while, but the voltage supplied to the main board 31. Is immediately shut off. As a result, the main board 31 falls earlier than the sub-boards 35, 37, 70, 80.

  FIG. 39 is a block diagram showing another embodiment of the rise management means. In the configuration shown in FIG. 38, reset ICs 931 and 932 are provided in the reset management circuit 940 serving as a startup management unit. As the reset ICs 931 and 932, the same IC as the power supply monitoring IC shown in FIG. The reset IC 931 sets the output to a high level when the +30 V power supply voltage (VSL) is +9 V or more, and sets the output to a low level when the +30 V power supply voltage (VSL) is lower than +9 V. The output of the reset IC 931 is supplied as a system reset signal to the CPU mounted on each sub board.

  The reset IC 932 sets the output to a high level when the + 30V power supply voltage (VSL) becomes + 7V or more, and sets the output to a low level when the + 30V power supply voltage (VSL) is lower than + 7V. The output of the reset IC 931 is supplied as a system reset signal to the CPU 56 mounted on the main board 31. In the reset ICs 931 and 932, voltages obtained by dividing the + 30V power supply voltage by resistors are input to the respective Vs terminals. The resistance values of the resistors are selected so that the reset ICs 931 and 932 can compare the + 30V power supply voltage (VSL) with + 7V or + 9V.

  As shown in FIG. 39, the reset release timing with respect to the CPU 56 of the main board 31 is also set to the reset release with respect to the CPU of the sub-board even with the configuration in which two reset ICs 931 and 932 that monitor different voltages and output a reset signal are provided. It can be later than the timing.

  When the outputs of the reset ICs 931 and 932 rise to a high level, the rise timing is delayed by a time determined by the capacitances of the capacitors C1 and C2.

  Therefore, as shown in FIG. 40, when the gaming machine is powered on and VSL rises to +7 V, the output of the reset IC 931 rises to a high level with a delay determined from the time point by the capacitance of the capacitor C1. When VSL rises to +9 V, the output of the reset IC 932 rises to a high level with a delay from that time by a time determined by the capacitance of the capacitor C2. The CPU on each sub-board starts operation when the output of the reset IC 931 rises to a high level and is released from the reset and starts its operation due to the difference in the initialization processing time of each CPU. Timing may vary.

  Therefore, in this embodiment, the capacitance of the capacitor C2 is made larger than the capacitance of the capacitor C1, and the timing at which the output of the reset IC 932 rises to a high level is delayed. With such a configuration, even when the CPU control start timing varies among the sub-boards, the CPUs on all the sub-boards always start control when the CPU 56 of the main board 31 starts operating. Can do. Further, when the power is cut off, the reset signal to the main board 31 falls at the level of + 9V, and each sub board falls when the drop of VSL to + 7V is detected. Therefore, the main board 31 can be lowered first. .

  In the configuration shown in FIG. 39, the reset signal rises only once when the power is turned on. However, as shown in FIG. 12, the reset signal rises twice when the power is turned on. Also good.

  In each of the embodiments described above, in a configuration including a plurality of electrical component control boards, the startup management means can control the startup sequence of the electrical component control boards. Therefore, the payout control board 37 is started up earlier than the main board 31, and an electrical component control board (for effect control) equipped with control means related to game effects such as the display control board 70, the lamp control board 35, and the voice control board 80, etc. It is easy to control so that the substrate) is started up earlier than the main substrate 31.

  In addition, the falling management means can control the order of lowering each electric component control board. Therefore, the main board 31 is an effect control board on which the payout control board 37 is lowered later than the main board 31 or a control means related to game effects such as the display control board 70, the lamp control board 35, and the voice control board 80 is mounted. It is easy to control to fall later.

  Meanwhile, the CPU 56 on the main board 31 and the payout control CPU 371 on the payout control board 37 perform power supply stop preparation processing according to the power-off signal from the power supply board 910 when the power supply is stopped, and then perform a looping operation. (See FIGS. 20 and 26). When the power supply is stopped, the system reset signal becomes low level after that and the CPU is reset.

  However, when an extremely short power interruption occurs, the system reset signal may not go low. In each of the above embodiments, the power cut-off signal is generated when the + 30V power supply voltage falls below + 22V, and the system reset signal becomes the low level when the + 30V power supply voltage falls below + 9V, so the + 30V power supply voltage becomes + 22V. If a power supply interruption that recovers before the voltage drops to + 9V occurs, the power supply stop signal is generated, so that the power supply stop preparation process starts, but the system reset signal is low. Not level. In such a case, the CPU cannot escape from the loop process in the power supply stop preparation process.

  FIG. 41 is a block diagram illustrating a configuration example of a power supply board that can avoid a situation in which it is not possible to escape from the loop process in the power supply stop preparation process even when an extremely short power supply interruption occurs. In the configuration shown in FIG. 41, a power monitoring IC 903 is mounted. When the + 30V power supply voltage (VSL) falls below 20V, the power supply monitoring IC 903 sets the output (the output of the RESET terminal) to a low level. In FIG. 41, in the power monitoring ICs 902 and 903, voltages obtained by dividing the + 30V power supply voltage by resistors are input to the respective Vs terminals. The resistance values of the resistors are selected so that the power monitoring ICs 902 and 903 can compare the + 30V power supply voltage (VSL) with + 22V or + 20V. The output of the IC 918 is supplied to the main board 31 and the payout control board 37 as a power-off signal.

  The output of the power monitoring IC 902 is latched by a latch circuit 981, and the output of the latch circuit 981 is a logic circuit that outputs a low level when both inputs are both at a low level (because it is equivalently an OR circuit. It is input to one input terminal of 982. The output of the power monitoring IC 903 is connected to the other input terminal of a logic circuit that outputs a low level when any of the inputs becomes a low level (hereinafter referred to as an AND circuit because it is equivalently an AND circuit). Entered. The output of the OR circuit 982 and the output of the reset management circuit 940 are input to the AND circuit 983, and the output of the AND circuit 983 is supplied to each substrate as a reset signal.

  FIG. 41 shows a configuration in which the same power-off signal is supplied to the main board 31 and the payout control board 37 for the sake of simplicity. As described above, the main board 31 is shown. The power-off signal corresponding to each of the payout control board 37 may be created, and the power-off signal to the payout control board 37 may be delayed. Further, the reset management circuit 940 may create a reset signal for each board and delay the reset signal for the main board 31 as in the case of the embodiment described above.

  FIG. 42A is an explanatory diagram illustrating an example of a relationship between a power-off signal and a system reset signal when the power monitoring IC 903 or the like is not provided. In the example shown in FIG. 42A, the + 30V power supply voltage (VSL) is lower than + 22V, but is restored before it decreases to + 9V. Accordingly, the power-off signal (low active) is output, but the reset signal remains at the high level. In such a case, the CPU cannot escape from the loop process in the power supply stop preparation process.

  However, according to the configuration shown in FIG. 41, as shown in FIG. 42B, when the + 30V power supply voltage (VSL) falls below + 22V, the low level is latched in the latch circuit 981, and the + 30V power supply voltage (VSL) ) Is less than + 20V, the output of the power supply monitoring IC 903 goes low, and the output of the OR circuit 982 goes low. As a result, the output of the AND circuit 983 becomes low level. That is, the system reset signal becomes low level. Thus, the CPU is system reset and can exit the loop process.

  FIG. 43 is a block diagram showing another configuration example of the power supply substrate 910. As shown in FIG. In the configuration shown in FIG. 43, the output of the power monitoring IC 902 is input to one input terminal of the AND circuit 983 via the delay circuit 984. The output of the reset management circuit 940 is input to the other input terminal of the AND circuit 983.

  According to the configuration shown in FIG. 43, as shown in FIG. 44, when the + 30V power supply voltage (VSL) falls below + 22V, the output (power-off signal) of the power monitoring IC 902 becomes low level. Since the signal is delayed by the delay circuit 986 and input to the AND circuit 983, the system reset signal supplied to the main board 31 and the payout control board 37 becomes low level. Thus, the CPU is system reset and can exit the loop process. The delay amount in the delay circuit 984 is set to a time sufficient for the CPU 56 of the main board 31 and the payout control CPU 371 of the payout control board 37 to complete the power supply stop preparation process.

  FIG. 43 shows a configuration in which the same power-off signal is supplied to the main board 31 and the payout control board 37 for the sake of simplicity. As described above, the main board 31 is shown. The power-off signal corresponding to each of the payout control board 37 may be created, and the power-off signal to the payout control board 37 may be delayed. Further, the reset management circuit 940 may create a reset signal for each board and delay the reset signal for the main board 31 as in the case of the embodiment described above.

It is the front view which looked at the pachinko game machine from the front. It is a rear view which shows each board | substrate arrange | positioned at the back surface of the pachinko gaming machine. It is the rear view which looked at the mechanism board of the pachinko game machine from the back. It is a block diagram which shows the circuit structure of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a display control board. It is a block diagram which shows the circuit structural example of a lamp control board. It is a block diagram which shows the circuit structural example of an audio | voice control board. It is a block diagram which shows the circuit structural example of a launch control board. It is a block diagram which shows the DC voltage etc. which are supplied to each board | substrate from a power supply board | substrate. It is a block diagram which shows one structural example of a power supply board. It is a block diagram which shows the structural example of a reset management circuit. It is a timing diagram which shows the mode of the output signal of reset IC and its periphery IC. It is a flowchart which shows the example of the main process which CPU in a main board | substrate performs. It is explanatory drawing which shows the example of the determination method of whether to perform a game state restoration process. It is a flowchart which shows the example of an initialization process. It is a flowchart which shows the example of an initialization process. It is a flowchart which shows the example of a 2ms timer interruption process. It is a flowchart which shows the example of a game control process. It is a flowchart which shows the example of a power failure generation | occurrence | production NMI process. It is explanatory drawing for demonstrating the example of the backup parity data creation method. It is a flowchart which shows the example of the main process which CPU for payout control performs. It is a flowchart which shows an example of the initialization process of CPU for payout control. It is a flowchart which shows the example of the timer interruption process of payout control CPU. It is a flowchart which shows the example of the payout control process which CPU for payout control performs. It is a flowchart which shows the example of a power failure generation | occurrence | production NMI process. It is explanatory drawing for demonstrating the example of the backup parity data creation method. It is a flowchart which shows the example of the payout state recovery process which CPU for payout control performs. It is a timing diagram which shows the example of the power supply fall at the time of the power failure of a game machine, or the mode of an NMI signal. It is a block diagram which shows the other structural example of a power supply board. It is a block diagram which shows the DC voltage etc. which are supplied to each board | substrate. It is a block diagram which shows other embodiment of start-up management means. FIG. 33 is a timing chart for explaining the operation of the start-up management means shown in FIG. 32. It is a block diagram which shows other embodiment of start-up management means. FIG. 35 is a timing chart for explaining the operation of the start-up management means shown in FIG. 34. It is a block diagram which shows other embodiment of fall management means. It is a timing diagram for demonstrating operation | movement of the fall management means shown in FIG. It is a block diagram which shows other embodiment of fall management means. It is a block diagram which shows other embodiment of a start-up management means. FIG. 40 is a timing chart showing the operation of the start-up management means shown in FIG. 39. It is a block diagram which shows the other structural example of a power supply board. It is explanatory drawing which shows the relationship between a power-off signal and a reset signal. It is a block diagram which shows the further another structural example of a power supply board. It is explanatory drawing which shows the relationship between a power-off signal and a reset signal.

Explanation of symbols

1 Pachinko machine 31 Main board 35 Lamp control board 37 Dispensing control board 56 CPU
70 Display control board 80 Audio control board 371 CPU for payout control
910 Power supply board 902 Power supply monitoring IC
920 delay circuit 940 reset management circuit 960 delay circuit 971, 972, 973, 974 delay circuit 968, 975, 976 rise management circuit 977 fall management circuit

Claims (1)

A gaming machine in which a player can play a predetermined game,
Game control means for controlling the progress of the game and transmitting a payout control command indicating the number of winning balls when a winning is detected;
A payout control means for paying out a prize ball based on reception of a payout control command from the game control means;
Power supply monitoring means for detecting a voltage drop of a predetermined potential power supply and outputting a detection signal;
The game control means includes
A backup RAM area for game control in which contents are saved even if the power supply to the gaming machine is cut off,
In accordance with a detection signal from the power supply monitoring means, backup data indicating that data is stored in the game control backup RAM area is stored in the game control backup RAM area, and the game control backup RAM is stored. Game control side power-off process execution means for generating check data by calculation based on area data and storing the generated check data in the game control backup RAM area for executing a game control-side power-off process ,
The payout control means includes:
A payout control backup RAM area where the contents are stored even if the power to the gaming machine is cut off,
In accordance with a detection signal from the power supply monitoring means, a payout control side power-off process execution means for executing a payout control-side power-off process for storing data in the payout control backup RAM area,
Delay means for delaying the processing start time of the payout control side power-off process execution means when compared with the processing start time of the game control side power-off processing execution means when a detection signal is output from the power supply monitoring means With
The game control means is configured to provide the game control backup based on the check data on condition that the backup data is stored in the game control backup RAM area when power supply to the gaming machine is started. A game for executing a determination as to whether or not the storage contents of the RAM area are normal, and if the determination determines that the storage contents of the backup RAM area for game control are normal, the game for returning the control state to the state when the power is turned off A gaming machine characterized by performing state restoration processing .

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