JP4065888B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine in which a game is performed according to a player's operation, and particularly, a game is performed according to a player's operation in a gaming area on a gaming board. It relates to gaming machines.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit capable of changing the display state is provided, and is configured to give a predetermined game value to the player when the display result of the variable display unit becomes a predetermined specific display mode There is.

  The game value means that the state of the variable winning ball device provided in the gaming area of the gaming machine is advantageous to a player who is easy to win and a right to become advantageous to the player. Or a condition that a condition for paying out premium game media is easily established. Also, when a predetermined amount of game balls or coins are awarded or points are added in accordance with the establishment of a predetermined condition such as winning, these are called values.

  In a pachinko game machine, the combination of a specific display mode with a predetermined display result of a variable display unit that displays special symbols is usually referred to as “big hit”. When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Further, when a predetermined condition (for example, winning in the V zone provided in the big prize opening) is not established at the time when the big prize opening is closed, the big hit gaming state is ended.

  In addition, among the combinations of display modes other than the “big hit” combination, the display results that are already deterministic or temporary at the stage where some of the display results of the plurality of variable display portions are not yet derived and displayed. A state in which the display mode of the variable display unit in which “” is derived and displayed satisfies a display condition that is a combination of specific display modes is referred to as “reach”. Then, when the display result of the identification information variably displayed on the variable display section does not satisfy the condition of “big hit”, it becomes “disconnected”, and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

  When a game ball wins a winning opening provided on the game board, a predetermined number of prize balls are paid out. Since the progress of the game is controlled by the game control means mounted on the main board, the number of winning balls based on the winning is determined by the game control means and transmitted to the payout control board having the payout control means. Hereinafter, control means other than the game control means may be referred to as electric component control means, respectively. The payout control unit is an example of a value addition control unit.

  When various electric component control means are provided separately from the game control means, a control command must be transmitted from the game control means to each electric component control means. If these control commands are not reliably received by each electrical component control control means, the control of the gaming machine will be hindered. For example, if the payout control means mistakenly receives a control command, the payout of the prize ball is not made or the wrong number of prize balls is paid out.

  Further, when the types of microcomputers used as the electric component control means are different, the time required for each electric component control means to take in commands may vary. Then, even if the command transmission control of the game control means for a certain electrical component control control means is appropriate, if the command transmission control is applied to the command transmission processing for other electrical component control control means, the electrical component control control means There is also a possibility that the command cannot be imported correctly.

  Therefore, in the gaming machine having a configuration in which a command is sent from the game control means to at least the payout control means, the game control means can reliably transmit the command to the payout control means, An object of the present invention is to provide a gaming machine that can reduce the program capacity of the game control means.

The gaming machine according to the present invention performs a game using a game ball, is provided with a variable display unit capable of variably displaying the identification information, and the display result of the variable display unit becomes a predetermined specific display mode. A gaming machine that gives a player a predetermined gaming value, a game controlling microcomputer that controls the progress of the game and outputs a command as command information (for example, a gaming control microcomputer including a CPU 56), and game control A plurality of electric component control microcomputers (for example, a microcomputer including a display control CPU 101) that receives electric commands from the microcomputer and performs electric component control processing for controlling electric components provided in the gaming machine according to the received commands. And a payout control microcomputer including a payout control CPU 371). The plurality of electric component control microcomputers control a payout control microcomputer for controlling a ball payout device (for example, a ball payout device 97) as an electric component for paying out a game ball, and a variable display unit as an electric component. Including a display control microcomputer (for example, a microcomputer including the display control CPU 101). The game control microcomputer is variable when the variable display section starts variable display of identification information on the display control microcomputer. It includes command output means for outputting information capable of specifying the display mode as a command, and outputting information capable of specifying the stop of the identification information as a command when the variable display of the identification information is terminated. The command is command data of 2 bytes. (See FIG. 21 and FIG. 22), and the game control microcontroller The computer outputs command data (see FIG. 20) for outputting command data and command data to the payout control microcomputer and display control microcomputer (see FIG. 20). In the command output process, the command data for the payout control microcomputer and the display control microcomputer and the fetch signal are output by calling the same subroutine (see FIG. 30). After outputting the command data of the first byte in the command and outputting the capture signal, the command data of the second byte is output after the elapse of a predetermined period (for example, period C in FIG. 20), and the game control microcomputer A predetermined period of time with a microcomputer for payout control Each of the display control microcomputers outputs the command data as a value equal to or greater than the maximum period among the periods required for receiving the command data.

Another aspect of the gaming machine according to the present invention is a specific display mode in which a game is performed using a game ball, a variable display unit capable of variably displaying identification information is provided, and a display result of the variable display unit is predetermined. A gaming machine that gives a player a predetermined gaming value when it becomes a game controlling microcomputer that controls the progress of the game and outputs a command as command information (for example, a gaming control microcomputer including a CPU 56) ) And a plurality of electric component control microcomputers (for example, for lamp control) that receive electric commands from the game control microcomputer and perform electric component control processing for controlling electric components provided in the gaming machine according to the received commands A microcomputer including a CPU 351 and a payout control microcomputer including a payout control CPU 371 And a plurality of electric component control microcomputers are provided in the game machine and a payout control microcomputer for controlling a ball payout device (for example, a ball payout device 97) as an electric component for paying out game balls. and have luminous body as electrical components (e.g., lamp or LED) emitting regime patronized microcomputer (e.g., a microcomputer including a lamp control CPU 351) for controlling the and a microcomputer for game control, emission regime patronized When the variable display of the identification information on the variable display unit is started to the microcomputer, information that can specify the display mode of the light emitter corresponding to the variable display mode of the identification information on the variable display unit is output as a command. When the variable display is finished, information that can identify the stop of identification information is output as a command. Includes command output means for, command consists of two bytes of command data (Fig. 21, see FIG. 23), the microcomputer for game control, and command data to the payout control microcomputer emission regime patronized microcomputer A command output process (see FIGS. 29 and 30) for outputting a take-in signal (see FIG. 20) designating take-in of command data is executed, and in the command output process, a payout control microcomputer and a light emitter control micro The command data for the computer and the capture signal are output by calling the same subroutine (see FIG. 30), and the game control microcomputer outputs the capture data by outputting the command data of the first byte in the command. , A predetermined period (for example, period C in FIG. 20) After the elapse of time, the second byte command data is output, and the game control microcomputer outputs a predetermined period of time, which is the maximum period required for each of the payout control microcomputer and the light emitter control microcomputer to receive the command data. Command data is output as a value equal to or greater than the period.

  The predetermined period is preferably longer than the period (for example, period A in FIG. 20) from when the command data is output until the capture signal is output.

  The electrical component control microcomputer executes predetermined periodic interrupt processing (see FIG. 35) for performing electrical component control processing in accordance with an interrupt generated at a predetermined cycle, and takes in from the game control microcomputer A command reception process (see FIG. 38) for receiving a command output by the game control microcomputer is executed in response to an interrupt based on the signal input, and the command reception process is prioritized over the periodic interrupt process. (For example, the interrupt permission state is set during the 2 ms timer interrupt process).

According to the first aspect of the present invention, the gaming machine, the gaming control microcomputer , commands the display controlling microcomputer to specify information that can specify the variable display mode when starting the variable display of the identification information in the variable display unit. And a command output means for outputting, as a command, information capable of specifying the stop of the identification information when the variable display of the identification information is finished , outputting command data of the first byte in the command, After the output, the command data of the second byte is output after the elapse of a predetermined period. The predetermined period is the maximum of the period required for each of the payout control microcomputer and the display control microcomputer to receive the command data. Since it is configured to output command data as a value over the period, the game control micro In a gaming machine configured to send a command from a computer to a payout control microcomputer and a display control microcomputer, the command can be reliably transmitted to the payout control microcomputer and the display control microcomputer. is there. Further, it is possible to reduce the program capacity related to command transmission of the game control microcomputer.

According to the second aspect of the present invention, when the game control microcomputer starts the variable display of the identification information on the variable display section on the light emitter control microcomputer, the variable display mode of the identification information on the variable display section is displayed. Including command output means for outputting information capable of specifying the display mode of the light emitter corresponding to the command as a command, and outputting information capable of specifying the stop of the identification information as a command when the variable display of the identification information is terminated. After outputting the first byte of command data and outputting the capture signal, the second byte of command data is output after a predetermined period of time, and the predetermined period is determined by each of the payout control microcomputer and the light emitter control microcomputer. As a value greater than or equal to the maximum period of time required to receive command data. In a gaming machine configured to send commands to the payout control microcomputer and the light emitter control microcomputer from the game control microcomputer, the payout control microcomputer and the light emitter control There is an effect that the command can be reliably transmitted to the microcomputer. Further, it is possible to reduce the program capacity related to command transmission of the game control microcomputer.

In the third aspect of the invention, the predetermined period is longer than the period from the output of the command data to the output of the capture signal, so that the receiving-side electric component control microcomputer can receive the command reliably. As well as shortening the time required to complete the transmission of one control signal.

In the invention according to claim 4 , the electrical component control microcomputer executes a predetermined periodic interrupt process for performing an electrical component control process in response to an interrupt generated at a predetermined cycle, and from the game control microcomputer. Because the command reception process for receiving the command output by the microcomputer for game control is executed in response to the interrupt based on the input of the input signal, the command reception process is executed with priority over the periodic interrupt process. The longest time required for command reception processing is determined, and it is possible to accurately determine how long the predetermined period should be.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. 1 is a front view of the pachinko gaming machine 1 as seen from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the mechanism plate of the pachinko gaming machine 1 as seen from the back. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and may be a coin gaming machine, for example. It can also be applied to image-type gaming machines and slot machines.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing the stored balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, there is provided a variable display device 8 including a variable display section 9 for variably displaying a plurality of kinds of symbols and a variable display 10 using 7 segment LEDs. Further, a passage memory display (ordinary symbol memory display) 41 composed of four LEDs is provided below the variable display 10. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passage gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the path between the passing gate 11 and the ball outlet 13, there is a gate switch 12 that detects a hit ball that has passed through the passing gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An opening / closing plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 19, 24, and winning of each game ball to each of the winning holes 19, 24 is detected by correspondingly provided winning hole switches 19a, 24a. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when a prize ball is paid out is provided in the vicinity of one speaker 27, and a ball break lamp 52 that is lit when a supply ball is cut out in the vicinity of the other speaker 27. Is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by one.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back surface of the variable display device 8, as shown in FIG. 2, a ball storage tank 38 is provided on the upper part of the mechanism plate 36, and a game ball is received from above in a state where the pachinko gaming machine 1 is installed on the gaming machine installation island. The sphere storage tank 38 is supplied. The game balls in the ball storage tank 38 reach the ball payout device through the guide rod 39.

  The mechanism plate 36 includes a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A relay board 33 for relaying signals between the variable display control unit 29 and the game control board 31, and a payout control board 37 on which a prize ball control microcomputer for performing payout control of game balls is mounted. ing. Further, at the lower part of the mechanism plate 36, a hitting ball launching device 34 that launches a hitting ball into the game area 7 using the rotational force of the motor, game effect lamps / LEDs 28a, 28b, 28c, a prize ball lamp 51, and a ball break lamp A lamp control board 35 for sending a signal to 52 is installed.

  FIG. 3 is a rear view of the mechanism plate of the pachinko gaming machine 1 as seen from the back. The balls stored in the ball storage tank 38 pass through the guide rod 39 and pass through the ball break detectors (ball break switches) 187a and 187b, as shown in FIG. 3, through the ball supply rods 186a and 186b. Device 97 is reached. The ball break switches 187a and 187b are switches that detect the presence or absence of a game ball in the game ball passage, but a ball break detection switch 167 that detects a shortage of supply balls in the ball tank 38 is also provided. The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A lot of premium balls based on the winnings are paid out and the hitting ball supply tray 3 becomes full. Finally, when the game balls reach the contact port 45 and further game balls are paid out, the game balls are surplus via the surplus ball passage 46. It is guided to the ball receiving tray 4. When the game ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the ball hitting device 34 is also stopped.

  Next, the configuration of the intermediate base unit installed on the mechanism plate 36 will be described. In the intermediate base unit, ball supply rods 186a and 186b and a ball dispensing device 97 are installed. As shown in FIG. 4, connection concave protrusions 182 are formed on the upper and lower sides of the intermediate base unit. The connection concave protrusion 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

  A passage body 184 is fixed to the upper part of the intermediate base unit. A ball dispensing device 97 is fixed to the lower part of the passage body 184. The passage body 184 has payout ball passages 186a and 186b for flowing down two rows of game balls whose flow direction has been changed to the left and right directions by a curve rod 174 (see FIG. 3). On the upstream side of the payout ball passages 186a, 186b, ball break switches 187a, 187b are installed. The ball cut switches 187a and 187b detect the presence or absence of a game ball in the payout ball passages 186a and 186b. When the ball cut switches 187a and 187b no longer detect a game ball, The rotation of the ball (not shown in FIG. 4) is stopped and the ball payout is immobilized.

  The ball break switches 187a and 187b are locked by locking pieces 188 at positions where it can be detected that about 27 to 28 game balls are present in the payout ball passages 186a and 186b. In other words, the ball break switches 187a and 187b have a maximum payout amount per unit of prize balls (15 in this embodiment) and a maximum payout amount per unit of ball lending (100 yen: 25 in this embodiment). It is installed at a position where the above can be confirmed.

  The central portion of the passage body 184 is formed in a shape that curves to the left and right so as to weaken the ball pressure of the game ball flowing down inside. A stop hole 189 is formed between the payout ball passages 186a and 186b. A mounting boss provided in the intermediate base unit is fitted into the back surface of the stop hole 189. In this state, the set screw is screwed, and the passage body 184 is fixed to the intermediate base unit. The passage body 184 can be aligned by the locking protrusion 185 provided on the intermediate base unit before being screwed.

  Below the passage body 184, a ball stopper 190 is provided for supplying the game ball to the ball payout device 97 and stopping the supply of the game ball to the ball payout device 97 in the event of a failure. A ball payout device 97 installed below the ball stopper 190 is housed in a rectangular parallelepiped case 198. Projections are provided at four places on the left and right sides of the case 198. The lower end of the case 198 is fitted into the elastic engagement piece provided at the lower part of the intermediate base unit in a state where each protrusion is engaged with the positioning protrusion provided on the intermediate base unit.

  FIG. 5 is an exploded perspective view of the ball dispensing device 97. The configuration and operation of the ball dispensing device 97 will be described with reference to FIG. In the ball dispensing device 97 in this embodiment, a stepping motor (dispensing motor) 289 rotates a screw 288 to pay out pachinko balls one by one. Note that the ball payout device 97 pays out not only a prize ball based on a prize but also a game ball to be lent.

  As shown in FIG. 5, the ball dispensing device 97 has two cases 198a and 198b. Engagement protrusions 280 are provided at two positions on the left and right sides of the cases 198a and 198b. In addition, ball supply paths 281a and 281b are formed in the cases 198a and 198b, respectively. The ball supply paths 281a and 281b have curved surfaces 282a and 282b, and ball feed horizontal paths 284a and 284b are formed below the ends of the curved surfaces 282a and 282b. Furthermore, ball discharge paths 283a and 283b are formed at the ends of the ball feed horizontal paths 284a and 284b.

  The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b are formed in front of partition walls 295a and 295b that divide the cases 198a and 198b in the front-rear direction. Further, a ball pressure buffering member 285 is sandwiched between the cases 198a and 198b in front of the partition walls 295a and 295b. The ball pressure buffering member 285 distributes the balls supplied to the ball dispensing device 97 to the left and right sides and guides the balls to the ball supply paths 281a and 281b.

  In addition, below the ball pressure buffering member 285, a payout motor position sensor using a light emitting element (LED) 286 and a light receiving element (not shown) is provided. The light emitting element 286 and the light receiving element are provided at a predetermined interval. The tip of the screw 288 is inserted within this interval. The ball pressure buffering member 285 is completely housed and fixed inside the cases 198a and 198b.

  Screws 288 that are rotated by a payout motor 289 are disposed in the ball feed horizontal paths 284a and 284b. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 is fitted into fixing grooves 291a and 291b formed at the rear of the partition walls 295a and 295b. In this state, the motor shaft of the payout motor 289 protrudes in front of the partition walls 295a and 295b, so that the screw 288 is fixed in front of the protrusion. On the outer periphery of the screw 288, there is provided a spiral projection 288a for moving the game ball placed on the ball feed horizontal paths 284a, 284b forward by the rotation of the payout motor 289.

  A recess is formed at the tip of the screw 288 so as to accommodate the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, during one rotation of the screw 288, the light from the light emitting element 286 is detected twice by the light receiving element through the notch 292.

  In other words, the payout motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position, and detects that the payout operation has been performed. The wiring from the light emitting element 286, the light receiving element, and the payout motor 289 are collectively drawn out from a drawing hole formed below the rear portions of the cases 198a and 198b and connected to the connector.

  When the payout motor 289 rotates in a state where the game ball is placed on the ball feed horizontal paths 284a and 284b, the game ball is moved forward on the ball feed horizontal paths 284a and 284b by the spiral protrusion 288a of the screw 288. Moving. And finally, it falls to the ball discharge paths 283a and 283b from the end of the ball feed horizontal paths 284a and 284b. At this time, the left and right ball feed horizontal paths 284a and 284b are alternately dropped. That is, each time the screw 288 is rotated halfway, one game ball falls from one side. Therefore, each time one game ball falls, the light from the light emitting element 286 is detected by the light receiving element.

  As shown in FIG. 4, a ball sorting member 311 is provided below the ball dispensing device 97. The ball sorting member 311 is driven by the sorting solenoid 310. For example, when the solenoid 310 is on, the ball sorting member 311 falls to the right, and when it is off, the ball sorting member 311 falls to the left. Below the sorting solenoid 310, a prize ball count switch 301A and a ball lending count switch 301B by proximity switches are provided. At the time of a winning ball based on winning, the ball sorting member 311 falls to the right side, and balls from the ball discharge paths 283a and 283b both pass the winning ball count switch 301A. Further, at the time of lending a ball, the ball sorting member 311 falls to the left side, and balls from the ball discharge paths 283a and 283b both pass the ball lending count switch 301B. Accordingly, the ball payout device 97 can change the payout flow path between the winning ball and the ball lending and pay out a predetermined number of game media.

  In this way, by providing the ball sorting member 311, the ball that has fallen through the two ball passages passes only one of the prize ball count switch 301 </ b> A and the ball lending count switch 301 </ b> B. Accordingly, the number of winning balls or the number of balls lent can be immediately grasped from the detection outputs of the winning ball count switch 301A and the ball lending count switch 301B without determining whether the ball is a winning ball or a lending ball.

  In this embodiment, a ball payout device 97 for paying out game balls by rotation of a stepping motor is used as a ball payout device for paying out game balls by driving an electric drive source. A ball payout device having a structure for delivering a game ball may be used, or a ball payout device having a structure in which a stopper is removed by driving of an electric drive source and the game ball is paid out by its own weight may be used.

  FIG. 6 is a block diagram illustrating an example of a circuit configuration in the main board 31. 6 also shows a payout control board 37, a lamp control board 35, a sound control board 70, a launch control board 91, and a display control board 80. The main board 31 includes a basic circuit 53 that controls the pachinko gaming machine 1 according to a program, a gate switch 12, a start port switch 17, a V count switch 22, a count switch 23, winning port switches 19a and 24a, and a winning ball count switch 301A. And a solenoid circuit 59 for driving a solenoid 16 for opening / closing the variable winning ball apparatus 15 and a solenoid 21 for opening / closing the opening / closing plate 20 in accordance with a command from the basic circuit 53. Has been.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the fact that the probability variation has occurred. An information output circuit 64 is provided for outputting the probability variation information and the like to a host computer such as a hall management computer.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is an example of storage means used as a work memory, a CPU 56 that performs control operations according to the program, and an I / O port unit 57. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

  Further, the main board 31 includes a system reset circuit 65 for resetting the basic circuit 53 when power is turned on, and an address signal supplied from the basic circuit 53 to decode any I / O port unit 57. An address decode circuit 67 for outputting a signal for selecting the / O port is provided. Note that there is also switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the lamp control means mounted on the lamp control board 35 controls the display of the start memory indicator 18, the gate passing memory indicator 41 and the decoration lamp 25 provided on the game board. At the same time, display control of the game effect lamps / LEDs 28a, 28b, 28c, the prize ball lamp 51 and the ball-out lamp 52 provided on the frame side is performed. Here, the lamp control means is an example of a light emitter control means. Further, display control of the variable display unit 9 for variably displaying the special symbol and the variable display 10 for variably displaying the normal symbol is performed by display control means mounted on the display control board 80.

  FIG. 7 shows the circuit configuration in the display control board 80. The LCD (Liquid Crystal Display) 82, the variable display 10, and the output port (ports 0 and 2) 570 of the main board 31 are examples of realization of the variable display unit 9. , 572 and the output buffer circuits 620 and 62A. The output port (output port 2) 572 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal).

  The display control CPU 101 operates in accordance with a program stored in the control data ROM 102. When an INT signal is input from the main board 31 via the noise filter 107 and the input buffer circuit 105B, display control is performed via the input buffer circuit 105A. Receive commands. As the input buffer circuits 105A and 105B, for example, general-purpose ICs 74HC540 and 74HC14 can be used. When the display control CPU 101 does not have an I / O port, an I / O port is provided between the input buffer circuits 105A and 105B and the display control CPU 101.

  Then, the display control CPU 101 performs display control of the screen displayed on the LCD 82 in accordance with the received display control command. Specifically, a command corresponding to the display control command is given to the VDP 103. The VDP 103 reads out necessary data from the character ROM 86. The VDP 103 generates image data to be displayed on the LCD 82 according to the input data, and outputs R, G, B signals and a synchronization signal to the LCD 82.

  7 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, animal, or an image made up of characters, figures, symbols, or the like displayed on the LCD 82.

  The input buffer circuits 105 </ b> A and 105 </ b> B can pass signals only in the direction from the main board 31 toward the display control board 80. Therefore, there is no room for signals to be transmitted from the display control board 80 side to the main board 31 side. That is, the input buffer circuits 105A and 105B constitute irreversible information input means together with the input ports. Even if the tampering is added to the circuit in the display control board 80, the signal output by the tampering is not transmitted to the main board 31 side.

  The outputs of the output ports 570 and 572 may be output to the display control board 80 as they are, but by providing the output buffer circuits 620 and 62A capable of transmitting signals only in one direction, the main board 31 and the display control board 80 are provided. One-way signal transmission can be made more reliable. That is, the output buffer circuits 620 and 62A constitute irreversible information output means together with the output ports.

  In addition, for example, a three-terminal capacitor or a ferrite bead is used as the noise filter 107 that cuts off the high-frequency signal. However, even if noise is added to the display control command between the substrates due to the presence of the noise filter 107, the influence is removed. Is done. A noise filter may also be provided on the output side of the buffer circuits 620 and 62A of the main board 31.

  FIG. 8 is a block diagram showing signal transmission / reception portions in the main board 31 and the lamp control board 35. In this embodiment, the game effect LED 28a, the game effect lamps 28b and 28c provided on the outside of the game area 7, and the decoration lamp 25 provided on the game board are turned on / off, and the prize ball lamp 51 and the ball are out of play. A lamp control command indicating turning on / off of the lamp 52 is output from the main board 31 to the lamp control board 35. Further, a lamp control command indicating the number of lighting of the start memory display 18 and the gate passing memory display 41 is also output from the main board 31 to the lamp control board 35.

  As shown in FIG. 8, the lamp control command related to the lamp control is output from the output ports (output ports 0 and 3) 570 and 573 of the I / O port unit 57 in the basic circuit 53. The output port (output port 3) 573 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. When the lamp control CPU 351 does not include an I / O port, an I / O port is provided between the input buffer circuits 355A and 355B and the lamp control CPU 351.

  In the lamp control board 35, the lamp control CPU 351 performs the game effect LED 28 a and the game effect lamp according to the turn-on / off pattern of the game effect LED 28 a, the game effect lamps 28 b and 28 c and the decoration lamp 25 defined according to each control command. 28b, 28c, and the decoration lamp 25 are turned on / off signals. The on / off signal is output to the game effect LED 28a, the game effect lamps 28b and 28c, and the decoration lamp 25. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  In the main board 31, the CPU 56 outputs a control command for instructing the lighting of the prize ball lamp 51 when there is an unpaid prize ball remaining in the stored contents of the RAM 55, and the above-mentioned payout ball passage 186 a, When the ball break switches 187a and 187b (see FIG. 3) installed upstream of 186b no longer detect a game ball, a control command is output to instruct the ball break lamp 52 to be lit. In the lamp control board 35, each control command is input to the lamp control CPU 351 via the input buffer circuits 355A and 355B. The lamp control CPU 351 turns on / off the prize ball lamp 51 and the ball-out lamp 52 in accordance with these control commands. The on / off pattern is stored in the built-in ROM or external ROM of the lamp control CPU 351.

  Further, the lamp control CPU 351 outputs a light on / off signal to the start memory display 18 and the gate passage memory display 41 in accordance with the control command.

  As the input buffer circuits 355A and 355B, for example, 74HC540 and 74HC14 which are general-purpose CMOS-ICs are used. The input buffer circuits 355A and 355B can pass signals only in the direction from the main board 31 toward the lamp control board 35. Therefore, there is no room for signals to be transmitted from the lamp control board 35 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the lamp control board 35, the signal output by the unauthorized modification is not transmitted to the main board 31 side. Note that a noise filter may be provided on the input side of the input buffer circuits 355A and 355B.

  In the main board 31, buffer circuits 620 and 63A are provided outside the output ports 570 and 573. As the buffer circuits 620 and 63A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line that can give a signal from the lamp control board 70 to the main board 31 is further reliably eliminated. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 63A.

  FIG. 9 is a block diagram showing a configuration example of the voice control command signal transmission portion of the main board 31 and the voice control board 70. In this embodiment, a voice control command for instructing voice output from the speaker 27 provided outside the gaming area 7 is output from the main board 31 to the voice control board 70 as the game progresses.

  As shown in FIG. 9, the voice control command is output from the output ports (output ports 0 and 4) 570 and 574 of the I / O port unit 57 in the basic circuit 53. The output port (output port 4) 574 outputs 8-bit data, and the output port 570 outputs a 1-bit INT signal. In the audio control board 70, each signal from the main board 31 is input to the audio control CPU 701 via the input buffer circuits 705A and 705B. When the audio control CPU 701 does not have an I / O port, an I / O port is provided between the input buffer circuits 705A and 705B and the audio control CPU 701.

  Then, for example, a voice synthesis circuit 702 using a digital signal processor generates voice and sound effects according to instructions from the voice control CPU 701 and outputs them to the volume switching circuit 703. The volume switching circuit 703 sets the output level of the audio control CPU 701 to a level corresponding to the set volume and outputs the level to the volume amplification circuit 704. The volume amplifier circuit 704 outputs the amplified audio signal to the speaker 27.

  As the input buffer circuits 705A and 705B, for example, 74HC540 and 74HC14, which are general-purpose CMOS-ICs, are used. The input buffer circuits 705A and 705B can pass signals only in the direction from the main board 31 toward the audio control board 70. Therefore, there is no room for signals to be transmitted from the voice control board 70 side to the main board 31 side. Therefore, even if unauthorized modification is added to the circuit in the voice control board 70, a signal output by the unauthorized modification is not transmitted to the main board 31 side. A noise filter may be provided on the input side of the input buffer circuits 705A and 705B.

  In the main board 31, buffer circuits 620 and 67A are provided outside the output ports 570 and 574. As the buffer circuits 620 and 67A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to further reliably eliminate a signal line from which a signal may be given from the voice control board 70 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 67A.

  FIG. 10 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 10, the detection signal from the full switch 48 is input to the I / O port 57 of the main board 31 via the relay board 71. The full tank switch 48 is a switch for detecting a full tank of the surplus ball tray 4. The detection signal from the ball break switch 187 (187a, 187b) is also input to the I / O port 57 of the main board 31 through the relay board 72 and the relay board 71.

  The CPU 56 of the main board 31 issues a payout prohibition when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Send a control command. When a payout control command for instructing payout is received, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, a detection signal from the prize ball count switch 301 </ b> A is also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A is provided in a payout mechanism portion of the ball payout device 97, and detects a prize ball payout ball actually paid out.

When there is a winning, a payout control command indicating the number of winning balls is input to the payout control board 37 from the output ports (ports 0, 1) 570, 571 of the main board 31. The output port (output port 1) 571 outputs 8-bit data, and the output port 570 outputs a 1-bit strobe signal (INT signal). A payout control command indicating the number of winning balls is input to the I / O port 372a via the input buffer circuit 373A. The INT signal is input to the interrupt terminal of the payout control CPU 371 via the input buffer circuit 373B. The payout control CPU 371 inputs a payout control command via the I / O port 372a, and drives the ball payout device 97 in accordance with the payout control command to perform prize ball payout.
In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  In the main board 31, buffer circuits 620 and 68A are provided outside the output ports 570 and 571. As the buffer circuits 620 and 68A, for example, general-purpose CMOS-ICs 74HC250 and 74HC14 are used. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, it is possible to more reliably eliminate a signal line from which a signal may be given from the payout control board 37 to the main board 31. be able to. A noise filter may be provided on the output side of the buffer circuits 620 and 68A.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer is mounted on the buzzer substrate 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

  Furthermore, detection signals from the prize ball count switch 301A and the ball lending count switch 301B are input to the input port 372b of the payout control board 37 via the relay board 72. The ball lending count switch 301B is provided in a payout mechanism portion of the ball payout device 97, and detects a lending ball actually paid out. A drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the I / O port 372f.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37. Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. At this time, the sorting solenoid 310 is in a driving state. That is, the ball distribution member 311 is directed to the ball lending side. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed.

  As described above, all signals from the card unit 50 are input to the payout control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31.

  In this embodiment, the case where the card unit 50 is provided is taken as an example. However, the present invention can also be applied to a case where a game ball corresponding to the amount of money is lent according to coin insertion. Further, in this embodiment, a case where a game ball is lent is taken as an example, but the present invention can be applied even if a score is added.

  In this embodiment, at least the RAMs on the main board 31 and the payout control board 37 are backed up by a backup power source. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are saved for a predetermined period. When each CPU detects a decrease in power supply voltage, it performs a predetermined process and waits for power recovery. Further, when the power is turned on, each CPU restores the state before the power is turned off based on the stored data when the data is stored in the RAM.

  In addition, as described above, an INT signal is output from the output port (output port 0) 570 of the main board 31 in order to send commands to the payout control board 37, the display control board 80, the lamp control board 35, and the voice control board 70. Output to each electrical component control board. In this case, for example, the output port 570 has an 8-bit configuration, where bit 0 is an INT signal to the payout control board 37, bit 1 is an INT signal to the display control board 80, and bit 2 is an INT signal to the lamp control board 35. The signal, bit 3, is used for outputting the INT signal to the audio control board 70.

  FIG. 11 is a block diagram showing a configuration example around the CPU 56. As shown in FIG. 11, a voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is connected to the non-maskable interrupt terminal (XNMI terminal) of the CPU 56. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. VSL is the largest DC voltage used in gaming machines, and is + 30V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt process. In this embodiment, the first power supply monitoring circuit is mounted on a power supply board described later.

  Although the system reset circuit 65 is also shown in FIG. 11, in this embodiment, the system reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, when the power is turned on, the reset IC 651 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level when the predetermined time elapses. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and the voltage value is a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage is lower than the power supply voltage value), a low level voltage drop signal is generated. Therefore, the CPU 56 performs a predetermined power supply stop process in response to the voltage drop signal from the first power supply monitoring circuit, and then the system is reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

  As shown in FIG. 11, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the first power supply monitoring circuit (voltage that outputs a voltage drop signal) is + 22V, and the detection voltage of the second power supply monitoring circuit is + 9V. In such a configuration, since the first power monitoring circuit and the second power monitoring circuit monitor the voltage of the same power supply VSL, the timing when the first voltage monitoring circuit outputs the voltage drop signal. And the timing at which the second voltage monitoring circuit outputs the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from when the power supply stop process is started in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop process is reliably completed.

  In this example, the first detection condition for the first power supply monitoring means to output the detection signal is that the + 30V power supply voltage has dropped to + 22V, and the second power supply monitoring means outputs the detection signal. The second detection condition that becomes is that the + 30V power supply voltage is lowered to + 9V. However, the voltage value used here is an example, and other values may be used.

  However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if the power to the gaming machine is cut The When the +5 V power supply is restored, a reset signal is issued from the system reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is stored in the backup RAM, it is possible to return to the gaming state at the time of occurrence of the power failure when recovering from the power failure.

  11 shows a configuration in which a reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on. However, even if the rising timing of the reset signal is only once, the reset is surely released. When using the CPU to be used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  The CPU 56 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The PIO has 4 bits PB0 to PB3 and 1 byte port PA0 to PA7. The ports PB0 to PB3 and PA0 to PA7 can be set to either input / output. However, the built-in PIO is not used in this embodiment. In that case, for example, all the ports are set to the input mode, and all the ports are connected to the ground level. When the power is turned on, the PIO is automatically set to the input mode.

  FIG. 12 is a block diagram illustrating a configuration example of the power supply board 910 of the gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and each electric component control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 22V, + 12V, and + 5V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board. Note that a power switch 918 for stopping or starting the power supply to the gaming machine is installed on the input side of the transformer 911.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. Capacitor 916 has power so that the storage state can be maintained with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is cut off (RAM that is backed up by power, that is, storage means that can be in the storage content storage state). Backup power supply. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  The power supply board 910 is mounted with a power monitoring IC 902 that constitutes the first power monitoring circuit described above. The power monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output because the power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. The voltage drop signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the power supply is turned on before the switch output shows the on state. It is possible to enter a state of waiting for recovery and not detect switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the voltage drop signal can be supplied from the first power supply monitoring circuit to the plurality of electric component control boards. Even if there are any number of electrical component control boards that require a voltage drop signal, it is only necessary to provide one first power supply monitoring means. Therefore, each electrical component control means in each electrical component control board performs the return control described later. Even if it goes, the cost of the gaming machine does not rise so much.

  In the configuration shown in FIG. 12, the detection output (voltage drop signal) of the power monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. However, for example, a configuration may be adopted in which one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board. Further, a buffer circuit corresponding to the number of substrates that require a voltage drop signal may be provided.

Next, the operation of the gaming machine will be described.
FIG. 13 is a flowchart showing main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first performs necessary initial settings (step S1).

  Then, it is confirmed whether or not data protection processing of the backup RAM area (for example, power failure occurrence NMI processing such as addition of parity data) has been performed when the power is turned off (step S2). In this embodiment, when an unexpected power failure occurs, processing for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3). In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area when the power is turned off. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state). “55H” set in the backup flag area is data set when the data protection process in the backup RAM area is completed in the power failure occurrence NMI process, and is a parity code based on the data in the backup RAM area.

  When there is backup data in the backup RAM area, the CPU 56 performs data check (for example, parity check) in the backup RAM area (step S4). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state when the power is cut off, and therefore an initialization process that is executed when the power is turned on not when the power failure is restored is executed (steps S5 and S3).

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state to the state at the time of power-off (step S6). As shown in FIG. 14, when the value of the backup flag is set to “55H” and the check result is normal, the gaming state recovery process of step S6 is executed. Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored (step S7).

  When the execution of the normal initialization process (step S3) is completed, the main process proceeds to a loop process in which the monitoring of the timer interrupt flag (step S9) is confirmed. In the loop, display random number update processing (step S8) is also executed.

  In this embodiment, after the presence or absence of backup data is confirmed in step S2, the backup area is checked in step S4 when the backup data exists. Conversely, the check result of the backup area is After it is confirmed that the data is normal, the presence / absence of backup data may be confirmed. Further, it may be determined whether or not to execute the power failure recovery processing by confirming either one of the presence / absence of backup data or the check of the backup area.

  Further, for example, in the parity check (step S4) when determining whether or not to execute the power failure recovery process, that is, when determining whether or not to restore the gaming state, a special process in the stored RAM data If it is confirmed that the gaming machine is in a game standby state (not changing in design, not in big hit game, not in probable change, or without starting prize memory) by flag or the like and starting winning memory data The initialization process may be executed without performing the game state restoration process.

  FIG. 15 is a flowchart showing the initial setting process in step S1. In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1a). When the interrupt is prohibited, the CPU 56 sets the interrupt mode to the interrupt mode 2 (step S1b), and sets the stack pointer designation address in the stack pointer (step S1c). Then, the CPU 56 initializes the built-in device register (step S1d). Further, after initialization (step S1e) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set to an accessible state (step S1f).

  The CPU 56 used in this embodiment has the following three types of maskable interrupt (INT) modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S1b of the initial setting process.

  FIG. 16 is a flowchart showing the normal initialization process (step S3). As shown in FIG. 16, in the initialization process, a RAM clear process is performed (step S3a). Next, based on the address value of the work area initial setting table, it is initialized to a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a payout command storage pointer, etc.) An initial value setting process (step S3b) for setting a value is performed. Then, a CTC register set in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S3c). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value. Since the interruption is prohibited (see FIG. 15) in the initial setting process (step S1), the interruption is permitted before the initialization process is completed (step S3d).

  Therefore, in this embodiment, the built-in CTC of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 17, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S12).

  When detecting that the timer interrupt flag is set in step S9, the CPU 56 resets the timer interrupt flag (step S10) and executes a game control process (step S11). With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process, but the game control process may be executed in the timer interrupt process.

  As described above, in this embodiment, the interrupt mode 2 is set in the initial setting process for the CPU 56 incorporating the CTC and PIO. Therefore, a periodic timer interrupt process using the built-in CTC can be easily realized. Also, the timer interrupt process can be set at an arbitrary position on the program. In addition, switch detection processing using the built-in PIO can be easily realized by interrupt processing. As a result, it is possible to obtain effects such as a simplified program configuration and a reduced number of program development steps.

  In this embodiment, it is determined whether or not to restore the power-off state based on the presence or absence of backup data. Accordingly, when the power is turned on at the time of power restoration after a power failure, it can be determined whether or not to restore the power-off state according to the contents of the backup data storage area.

  In addition, since it is determined whether or not to restore to the power-off state depending on the backup data status, depending on the status of the contents of the backup data storage area when the power is turned on when the power is restored after a power failure, etc. Thus, it can be determined whether or not to restore the power-off state.

  FIG. 18 is a flowchart showing the game control process of step S11. In the game control process, the CPU 56 first inputs the states of the gate sensor 12, the start port sensor 17, the count sensor 23, and the winning port switches 19a and 24a via the switch circuit 58, and wins each winning port and winning device. It is determined whether or not there has been (switching process: step S21).

  Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 performs a process of setting a control command sent to the payout control board 37 and the like in a predetermined area of the RAM 55 and sending the control command (command control process: step S27).

  Next, the CPU 56 performs a data output process for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is established (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in accordance with the drive command, thereby bringing the variable winning ball device 15 or the opening / closing plate 20 into an open state or a closed state.

  Further, the CPU 56 performs setting of the number of winning balls based on the detection output of the switches 17, 23, 19a, 24a for detecting winning at each winning opening (step S31). Specifically, a payout control command is output to the payout control board 37 in response to winning detection. The payout control CPU 371 mounted on the payout control board 37 drives the ball payout device 97 according to the payout control command.

  As described above, the main process includes a process for determining whether or not to shift to the game control process, and the timer control process based on the timer interrupt periodically generated by the internal timer of the CPU 56 is used for the game control process. Since a flag for determining whether or not to shift is set, all the game control processes are executed reliably. In other words, until all the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all the processes in the game control process are completed. ing.

  Here, the game control process executed by the CPU 56 of the main board 31 is executed according to the flag set in the timer interrupt process based on the timer interrupt that the internal timer of the CPU 56 periodically generates. A hardware circuit that generates a signal periodically (for example, every 2 ms) is provided, a signal from the circuit is introduced into an external interrupt terminal of the CPU 56, and it is determined whether or not to shift to a game control process by the interrupt signal. A flag may be set for this purpose.

  Even in such a configuration, the determination of the flag is not performed until all of the game control processes are executed, so that it is guaranteed that all the processes in the game control process are completed.

  FIG. 19 is an explanatory diagram showing an example of a command form of a payout control command sent from the main board 31 to the payout control board 37. In this embodiment, the payout control command has a 2-byte structure, the first byte represents MODE (type of control content), and the second byte represents EXT (details of control content). Note that the command form shown in FIG. 19 is an example, and other command forms may be used. The first bit (bit 7) of the MODE data is always “1”, and the first bit (bit 7) of the EXT data is always “0”.

  FIG. 20 is a timing chart showing the relationship between an 8-bit control signal (in this case, a payout control signal) and an INT signal (in this case, a payout control signal INT) constituting a control command for each electrical component control means. is there. As shown in FIG. 20, after the MODE or EXT data is output to the output port (in this case, port 1), when the period indicated by A elapses, the CPU 56 outputs an INT signal that is a signal indicating data output. Turn on the. Further, when the period indicated by B elapses, the INT signal is turned off. Further, when there is data to be transmitted next, that is, after the MODE data is transmitted, the second byte of data is transmitted to the output port after a period indicated by C. Regarding the second byte data, the periods A and B are the same as in the first byte.

  The period A is a period required for the CPU 56 to prepare to send a command, that is, a process required to set a send command in the buffer, and to stabilize data on the control signal line (in this case, the payout control signal line). Is the period. The period B is a period for stabilizing the INT signal. The period C is a period in which the electrical component control means (in this case, the payout control means) is set so that data can be taken in reliably. In the period C, the data on the signal line does not change. That is, the data output is maintained until the period of C elapses.

  As will be described later, in this embodiment, a payout control command to the payout control board 37, a display control command to the display control board 80, a lamp control command to the lamp control board 35, and a voice control command to the voice control board 70 are used. Are sent out using the same routine (common module). Therefore, during the period of C, that is, the period from when the INT signal related to the first byte is turned off to the start of data transmission of the second byte, the reception processing time in the electrical component control means that takes the longest time for command reception processing. Is set to be longer.

  Each electrical component control unit detects that the INT signal has changed from the on state (high level) to the off state (low level), and starts a 1-byte data capturing process by, for example, an interrupt process.

  Since the period of C is longer than the reception processing time in the electrical component control means that takes the longest time for command reception processing, even if the game control means controls the command transmission processing for each electrical component control means with the common module, Even the electric component control means can reliably receive the control command from the game control means.

  In this embodiment, the CPU 56 operates with a system clock of (11.776 / 2) MHz. Specifically, 138 states (1 state = [2 / 11.776] μs) are applied to the period A, 82 states are applied to the period B, and 251 states are applied to the period C. Therefore, the period C is longer than the period A. That is, the CPU 56 is ready to send the next data after a predetermined period of time has elapsed after executing the INT signal output process, but during the predetermined period (C period), the data is sent before the INT signal output process. Is longer than the period (period A) from when the INT signal starts to be output. As described above, the period A is a stabilization period in the command signal line, and the period C is a period for securing the time required for the receiving side to capture data. Therefore, by making the period A shorter than the period C, it is possible to obtain an effect that the electric component control means on the receiving side can reliably receive a command, and it is necessary to complete the transmission of one command. There is also an effect of shortening the period.

  FIG. 21 is an explanatory diagram showing an example of the contents of the payout control command. In the example shown in FIG. 21, the command FF00 (H) with MODE = FF (H) and EXT = 00 (H) is a payout control command for designating a payout enabled state. That is, the command FF00 (H) is specified as information indicating whether or not a game ball can be given by MODE = FF (H), and is specified as payable by EXT = 00 (H). The A command FF01 (H) with MODE = FF (H) and EXT = 01 (H) is a payout control command for designating a payout stop state. That is, the command FF01 (H) is specified as information indicating whether or not a game ball can be given by MODE = FF (H), and the command FF01 (H) cannot be paid out by EXT = 01 (H). Identified. Further, the command F0XX (H) of MODE = F0 (H) is a payout control command for designating the number of prize balls. That is, the command F0XX (H) is specified to be information indicating the number of prize balls given by MODE = F0 (H), and the number of payouts is specified by EXT = XX (H).

  When the payout control means receives the payout control command of FF01 (H) from the game control means of the main board 31, the payout payout and ball lending are stopped, and when the payout control command of FF00 (H) is received, the payout ball payout And you can rent a ball. When a payout control command for designating the number of prize balls is received, prize ball payout control is performed according to the number designated by the received command.

  The payout control command is sent only once so that the payout control means can recognize it. In this example, “recognizable” means that the INT signal is turned on, and “recognizable only once” means that in this example, each of the first and second bytes of the payout control signal is sent. In response, the INT signal is turned on only once.

  Further, since one command (command information) has a 2-byte structure, the influence of noise can be reduced. In other words, if one command is composed of 1-byte command data, it may be received as it is even if data corruption occurs due to noise, and erroneous control may be performed. If so, the control based on the command is started only when both are correctly received, so that the possibility of malfunction can be reduced compared to the case of the 1-byte configuration.

  FIG. 22 is an explanatory diagram showing an example of the contents of the display control command. The display control command also has a 2-byte structure of MODE and EXT. In the example shown in FIG. 22, commands 8000 (H) to 8022 (H) and 8100 (H) to 8122 (H) are display controls for designating a variation pattern of a special symbol in the variable display unit 9 that variably displays the special symbol. It is a command. Note that the command for specifying the variation pattern also serves as a variation start instruction. The command 88XX (X = any value of 4 bits) is a display control command relating to a variation pattern of a normal symbol variably displayed on the variable display 10. The command 89XX is a display control command for designating a normal symbol stop symbol. Command 8AXX (X = any value of 4 bits) is a display control command for instructing stop of variable symbol display.

  Commands 91XX, 92XX, and 93XX are display control commands for designating a stop symbol in the middle left of the special symbol. The command A0XX is a display control command for instructing to stop the special symbol variable display. The command BXXX is a display control command that is sent from the start of the big hit game to the end of the big hit game. The commands C000 and EXXX are display control commands relating to the display state of the variable display unit 9 that is not related to special symbol fluctuations and jackpot games. When the display control means of the display control board 80 receives the above-described display control command from the game control means of the main board 31, the display state of the variable display section 9 and the variable display 10 is changed according to the contents shown in FIG. To do.

  FIG. 23 is an explanatory diagram showing an example of the contents of the lamp control command. The lamp control command also has a 2-byte configuration of MODE and EXT. In the example shown in FIG. 23, commands 8000 (H) to 8022 (H) and 8100 (H) to 8122 (H) designate a lamp / LED display control pattern corresponding to the variation pattern of the special symbol in the variable display unit 9. This is the lamp control command to be performed. The command A0XX (X = any value of 4 bits) is a lamp control command for instructing a lamp / LED display control pattern when the variable symbol special display is stopped. The command BXXX is a lamp control command for instructing a lamp / LED display control pattern from the start of the jackpot game to the end of the jackpot game. The command C000 is a lamp control command for instructing a lamp / LED display control pattern during a customer waiting demonstration.

  The commands 8XXX, AXXX, BXXX and CXXX are ramp control commands sent from the game control means in accordance with the game progress status. When the lamp control means receives the above-described lamp control command from the game control means of the main board 31, the lamp / LED display state is changed according to the contents shown in FIG.

  The command E0XX is a lamp control command indicating the number of lighting of the start memory display 18. For example, the lamp control means turns on the number of displays designated by “XX” in the start memory display 18. The command E1XX is a lamp control command indicating the number of lighting of the gate passing memory display 41. For example, the lamp control means turns on the number of displays designated by “XX” in the gate passing storage display 41. That is, these commands are commands for instructing the control of the light emitters provided for informing the information of the reserved number. In addition, the command regarding the number of lighting of the start memory | storage display 18 and the gate passage memory | storage display 41 may be comprised so that increase / decrease in the number of lighting may be shown.

  Commands E200 and E201 are lamp control commands relating to the display state of the winning ball lamp 51, and commands E300 and E301 are lamp control commands relating to the display state of the ball-out lamp 52. When the lamp control means receives the lamp control command of “E201” from the game control means of the main board 31, the lamp control means sets the display state of the prize ball lamp 51 as a predetermined display state when there is a prize ball remaining, and “E200” When the lamp control command is received, the display state of the prize ball lamp 51 is set to a display state determined in advance as a case where no prize ball remains. When the lamp control command “E300” is received from the game control means of the main board 31, the display state of the ball break lamp 52 is changed to the display state with a ball, and when the lamp control command “E301” is received, the ball break lamp 52 is displayed. The display state of is set to the display state when the ball is out. That is, commands E200 and E201 are commands indicating control of a light-emitting body provided for notifying a player or the like that there is a non-prize ball, and commands E300 and E301 are supply balls. This is a command indicating that a light-emitting body provided for notifying a player or a game clerk that the game has expired is controlled.

  The command E400 is changed from a specific gaming state (high probability state or short-time state, high probability state in this example) to a normal state (low probability state or non-time-short state, low probability state in this example) when the gaming machine is turned on. This is a lamp control command for instructing a lamp / LED display control pattern at the time of transition. The command E401 is a lamp / LED display when a transition is made from a normal state (low probability state or non-time-short state, in this example low probability state) to a specific gaming state (high probability state or time-short state, in this example high probability state). This is a lamp control command for designating a control pattern. The command E402 is a lamp control command for instructing a lamp / LED display control pattern when an error occurring during the big hit game is canceled. The command E403 is a lamp control command for instructing a lamp / LED display control pattern when an error of the count switch 23 occurs. That is, these commands are commands for instructing the gaming state to be notified by the light emitter. In this embodiment, when the lamp control means receives a command instructing to notify the gaming state, the lamp control means uses a part or all of the decoration lamp 25, the game effect LED 28a, and the game effect lamps 28b and 28c, Turn on / off control to notify the gaming state. Note that the decoration lamp 25, the game effect LED 28a, and the game effect lamps 28b and 28c may each be composed of a collection of a plurality of light emitters. Notifying the gaming state using a part of 28c also means that, for example, a part of the plurality of light emitters constituting the decorative lamp 25 may be used.

  FIG. 24 is an explanatory diagram showing an example of the contents of a voice control command. The voice control command also has a 2-byte configuration of MODE and EXT. In the example shown in FIG. 24, the command 8XXX (X = any value of 4 bits) is a voice control command for designating a sound generation pattern in a special symbol variation period. The command BXXX (X = any value of 4 bits) is a voice control command for designating a sound generation pattern from the start of the jackpot game to the end of the jackpot game. Other commands are voice control commands that are not related to special symbol changes and jackpot games. When the voice control means of the voice control board 70 receives the above-described voice control command from the game control means of the main board 31, the voice output state is changed according to the contents shown in FIG.

  FIG. 25 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56. The special symbol process shown in FIG. 25 is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process, the CPU 56 performs any one of the steps S300 to S309 shown in FIG. 25 according to the internal state after performing the fluctuation shortening timer subtraction process (step S310).

  In the fluctuation shortening timer subtraction process in step S310, whether or not a condition for shortening the variation time of the special symbol is satisfied (for example, a predetermined time elapses from the start winning detection until the process based on the start winning is executed). The process of subtracting the fluctuation shortening timer for confirming whether or not) is performed. And in each process of step S300-S309, the following processes are performed.

  Special symbol variation waiting process (step S300): Waiting for the start opening sensor 17 to be turned on after hitting the start winning opening 14 (the winning opening of the variable winning ball apparatus 15 in this embodiment). When the start opening sensor 17 is turned on, if the start winning memory number is not full, the start winning memory number is incremented by 1 and a jackpot determining random number or the like is extracted.

  Special symbol determination process (step S301): When variable symbol special display can be started, the number of start winning memories is confirmed. If the start winning memorized number is not 0, it is determined whether to win or not according to the extracted value of the big hit determination random number.

  Stop symbol setting process (step S302): The stop symbol of the middle left and right symbols is determined.

  Reach operation setting process (step S303): It is determined whether or not a reach operation is performed according to the value of the reach determination random number, and a change period during reach is determined according to the value of the reach type determination random number.

  All symbol variation start processing (step S304): Control is performed so that the variation display unit 9 starts variation of all symbols. At this time, a control command for instructing the right / left middle final stop symbol and the variation mode is transmitted to the display control board 80. When the process is finished, the internal state (process flag) is updated to shift to step S305.

  All symbols stop waiting process (step S305): When a predetermined time has elapsed, control is performed so that all symbols displayed on the variable display unit 9 are stopped. If the stop symbol is a combination of jackpot symbol, the internal state (process flag) is updated to shift to step S306. If not, the internal state is updated to shift to step S300.

  Big winning opening opening process (step S306): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. When the process is finished, the internal state (process flag) is updated to shift to step S307.

  Processing during opening of the special winning opening (step S307): Control for sending display control command data of the large winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the final closing condition of the big prize opening is satisfied, the internal state is updated to shift to step S308.

  Specific area valid time processing (step S308): The presence or absence of passage of the V count switch 22 is monitored, and processing for confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S306. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the internal state is updated to shift to step S309.

  Big hit end process (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated to shift to step S300.

  As described above, when a hit ball is won at the start winning opening 14, the CPU 56 determines whether or not to make a big hit or not, a stop symbol, a reach mode, or a probability change in the special symbol process. A control command such as a display control command according to the determination is sent to an electrical component control means such as a display control means. For example, in the display control means, display control of the variable display unit 9 is performed in accordance with a display control command from the main board 31. Also, control commands are sent to the display control board 80, the lamp control board 35, and the voice control board 70 as the game progresses. The command sending method is as described above.

  FIG. 26 is a flowchart showing a portion related to prize ball control in the switch process (step S21) in the game control process shown in FIG. In the switch process, the CPU 56 sets a ball break state flag when the ball break switch 187 detects a ball break (steps S121 and S122). Further, when it is detected by the ball break switch 187 that the ball is not broken, the ball break state flag is reset (steps S121 and S123).

  Next, when the lower pan full tank is detected by the full tank switch 48, a full tank flag is set (steps S124 and S125). Further, when it is detected by the full tank switch 48 that the lower pan is not full, the full tank flag is reset (steps S124 and S126).

  Further, when it is detected that the count switch 23 is turned on, the 15 counter is incremented by 1 (steps S131 and S132), and when any of the winning opening switches 19a and 24a is detected, the 10 counter is incremented by 1 ( In steps S133 and S134), when it is detected that the start port switch 17 is turned on, the six counters are incremented by one (steps S135 and S136).

  In this embodiment, 15 winning balls are paid out for winning through the big winning opening, 6 winning balls are paid out for winning through the starting winning opening 14, and the other winning openings 19, 24 and winning prizes. It is assumed that 10 winning balls are paid out for winning through the ball apparatus. The 15-counter is a counter for counting the number of winnings at the big winning opening, the 10-counter is a counter for counting the number of winnings at the normal winning opening, and the 6-counter is a winning at the starting winning opening. It is a counter for counting numbers.

  FIG. 27 is a flowchart showing an example of a winning ball signal process (step S31) in the game control process shown in FIG. In this example, in the winning ball signal processing, the CPU 56 first confirms whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop state designation command is sent to the payout control board 37. If it is not in the payout stop state, it is confirmed whether or not the above-described ball-out state flag or full tank flag is turned on (step S202).

  When any of them changes to the on state, the command transmission table relating to the designation of the payout stop state is set (step S203). The command transmission table will be described in detail later. In step S202, when one of the flags is already on and the other flag is on, the command transmission table is not set (step S203).

  If it is in the payout stop state, it is checked whether both the ball-out state flag and the full tank flag are turned off (step S204). When both are turned off, the command transmission table relating to the payout stop cancellation designation is set (step S205).

  Next, the CPU 56 performs control to set a payout control command related to the number of winning balls corresponding to the winning in the command transmission table. First, the value of the 15 counter is checked (step S211). As described above, the 15 counter is counted up when the game ball wins the big winning opening and the count switch 23 is turned on. If the value of the 15 counter is not 0, a command transmission table for 15 prize ball number instructions is set (step S212). Further, the value of the 15 counter is decremented by -1 (step S213).

  If the value of the 15 counter is 0, the value of the 10 counter is checked (step S215). As described above, the 10 counter is counted up when the game ball has won a winning opening and the winning opening switches 19a and 24a are turned on. If the value of the 10 counter is not 0, the command transmission table for the 10 winning ball number instructions is set (step S216). Further, the value of the 15 counter is decremented by 1 (step S217).

  If the value of the 10 counter is 0, the value of the 6 counter is checked (step S221). As described above, the six counter is counted up when the game ball wins the start winning opening and the start opening switch 17 is turned on. If the value of the six counter is not 0, the command transmission table for the six prize ball number instructions is set (step S222). Further, the value of the six counter is decremented by 1 (step S223).

  As described above, when the game control means tries to output a payout control command to the payout control board 37, the command transmission table is set. FIG. 28A is an explanatory diagram showing a configuration example of the command transmission table. One command transmission table is composed of 3 bytes, and INT data is set in the first byte. Further, MODE data of the first byte of the payout control command is set in the command data 1 of the second byte. Then, in the command data 2 of the third byte, EXT data of the second byte of the payout control command is set.

  Although the EXT data itself may be set in the area of the command data 2, the command data 2 may be set with data for designating the address of the table storing the EXT data. . In this embodiment, if bit 7 (work area reference bit) of command data 2 is 0, it indicates that EXT data itself is set in command data 2. Such EXT data is data in which bit 7 is 0. If the work area reference bit is 1, it indicates that the other 7 bits are an offset for designating the address of the table storing the EXT data.

  In this embodiment, a plurality of command transmission tables are prepared, and the command transmission table to be used is designated by a pointer. The plurality of command transmission tables are used as a ring buffer. Therefore, the CPU 56 sets INT data, command data 1 and command data 2 in the command transmission table pointed to by the writing pointer in the winning ball signal processing. Then, the value of the write pointer is updated. Since one command transmission table has a 3-byte configuration, specifically, the write pointer value is +3.

  In the process shown in FIG. 27, only a command transmission table setting process related to one payout control command is performed per process, but a plurality of command transmission tables are provided, so that a plurality of command transmission table setting processes are provided. You may comprise so that it may perform. For example, when a plurality of winnings are stored in 15 counters, 10 counters, and 6 counters, a plurality of command transmission table setting processes may be performed in one winning ball signal process.

  Here, the payout control command will be described. However, when the display control command, the lamp control command, and the voice control command are transmitted, the INT data, the command data are displayed in the command transmission table as shown in FIG. 1 and command data 2 are set. At that time, INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the write pointer.

  FIG. 28 (B) is an explanatory diagram showing a configuration example of INT data. Bit 0 in the INT data indicates whether or not a payout control command should be sent to the payout control board 37. If bit 0 is “1”, it indicates that a payout control command should be sent. Therefore, the CPU 56 sets “01 (H)” in the INT data in the winning ball signal processing.

  It should be noted that bits 1, 2, and 3 of the INT data are bits indicating whether or not a display control command, a lamp control command, and a voice control command should be sent, respectively, and the CPU 56 is a timing at which those commands should be sent. Then, INT data, command data 1 and command data 2 are set in the command transmission table pointed to by the pointer by special symbol process processing or the like. When these commands are transmitted, the corresponding bit of the INT data is set to “1”, and MODE data and EXT data are set to the command data 1 and the command data 2.

  FIG. 29 is a flowchart showing a processing example of command control processing (step S27) in the game control processing shown in FIG. The command control process is a process including a command output process. In the command control process, the CPU 56 first saves the address (contents of the read pointer) of the command transmission table to the stack or the like (step S231). Then, the INT data of the command transmission table pointed to by the read pointer is loaded into the argument 1 (step S232). The argument 1 is input information for a command transmission process to be described later. Further, the address indicating the command transmission table is incremented by 1 (step S233). Therefore, the address indicating the command transmission table matches the address of the command data 1.

  Therefore, the CPU 56 reads the command data 1 and sets it as the argument 2 (step S234). The argument 2 is also input information for a command transmission process to be described later. Then, the command transmission processing routine is called (step S235).

  FIG. 30 is a flowchart showing a command transmission routine. In the command transmission routine, the CPU 56 first sets the data set as the argument 1, that is, the INT data, in the work area determined as the comparison value (step S251). Next, the number of transmissions = 4 is set in the work area determined as the number of processes (step S252). Then, the address of port 1 (output port 571) for outputting the payout control signal is set to the IO address (step S253).

  Next, the CPU 56 shifts the comparison value to the right by 1 bit (step S254). As a result of the shift process, it is confirmed whether or not the carry bit has become 1 (step S255). When the carry bit becomes 1, it means that the rightmost bit in the INT data is “1”. In this embodiment, four shift processes are performed. For example, when it is specified that a payout control command should be sent, the carry bit is set to 1 in the first shift process.

  When the carry bit becomes 1, the data set in the argument 2, in this case, command data 1 (that is, MODE data) is output to the address set as the IO address (step S 256). Since the address of port 1 (output port 571) is set as the IO address when the first shift processing is performed, the MODE data of the payout control command is eventually output to port 1.

  Next, the CPU 56 adds 1 to the IO address (step S257) and subtracts 1 from the number of processes (step S258). If port 1 is indicated before addition, the address of port 2 (output port 572) is set as the IO address by the addition processing for the IO address. Port 2 (output port 572) is a port for outputting a display control command. Then, the CPU 56 confirms the value of the number of processes (step S259), and if the value is not 0, returns to step S254. In step S254, the shift process is performed again.

  In the second shift process, the value of bit 1 in the INT data is pushed out, and the carry flag is set to “1” or “0” depending on the value of bit 1. Therefore, it is checked whether or not it is specified that the display control command should be sent. Similarly, it is checked whether or not the lamp control command and the voice control command are to be transmitted by the third and fourth shift processes. As described above, when each shift process is performed, an IO address corresponding to a command (payout control command, display control command, lamp control command, voice control command) checked by the shift process is set in the IO address. Has been. Therefore, when the carry flag becomes “1”, a control command is sent to the corresponding output port (port 1 to port 4). That is, a single common module can perform control command transmission processing for each electric component control means.

  In addition, since it is determined to which electrical component control means the control command should be output only by the shift processing, the process for determining to which electrical component control means the control command should be output is simplified. It has become.

  Next, the CPU 56 reads the content of the argument 1 in which the INT data before the start of the shift process is stored (step S260), and outputs the read data to the port 0 (output port 570) (step S261). In the INT data, the bit corresponding to the output bit of the INT signal corresponding to the control command (payout control command, display control command, lamp control command, voice control command) output in the processing of steps S251 to S259 is “1”. It has become. Therefore, the INT signal corresponding to the control command (payout control command, display control command, lamp control command, voice control command) output to any of the ports 1 to 4 is turned on.

  Next, the CPU 56 sets a predetermined value in the wait counter (step S262), and subtracts one by one until the value becomes 0 (steps S263 and S264). This process is a process for setting the period B shown in FIG. When the value of the wait counter becomes 0, clear data (00) is set (step S265), and the data is output to port 0 (step S266). Therefore, the INT signal is turned off. Then, a predetermined value is set in the wait counter (step S262), and 1 is subtracted by one until the value becomes 0 (steps S268 and S269). This process is a process for setting the period C shown in FIG.

  Therefore, the value set in the wait counter in step S267 is a value such that the period C is sufficient to ensure that all electrical component control means that are subject to receiving control commands perform command reception processing. is there. The value set in the wait counter is a value such that the period C is longer than the time required for the processing in steps S251 to S259.

  As described above, the MODE data of the first byte of the control command is transmitted. Therefore, the CPU 56 adds 1 to the value indicating the command transmission table in step S236 shown in FIG. Therefore, the command data 2 area of the third byte is designated. The CPU 56 loads the contents of the indicated command data 2 into the argument 2 (step S237). Further, it is confirmed whether or not the value of bit 7 (work area reference bit) of the command data 2 is “0” (step S239). If not 0, the head address of the command extended data address table is set in the pointer (step S239), and the value of bit 6 to bit 0 of the command data 2 is added to the pointer to calculate the address (step S240). Then, the data of the area pointed to by the address is loaded into the argument 2 (step S241).

  In the command extension data address table, EXT data that can be sent to the electrical component control means is sequentially set. Therefore, if the value of the work area reference bit is “1” by the above processing, the EXT data in the command extended data address table corresponding to the contents of the command data 2 is loaded into the argument 2 and the work area reference bit If the value is “0”, the contents of the command data 2 are loaded into the argument 2 as they are. Even when EXT data is read from the command extension data address table, bit 7 of the data is “0”.

  Next, the CPU 56 calls a command transmission routine (step S242). Therefore, the EXT data is transmitted at the same timing as the transmission of MODE data. Thereafter, the CPU 56 restores the address of the command transmission table (step S243), and updates the value of the read pointer indicating the command transmission table (step S244). Since one command transmission table has a 3-byte structure, specifically, the value of the read pointer is +3.

  As described above, the control command (payout control command, display control command, lamp control command, voice control command) having a 2-byte configuration is transmitted to the corresponding electrical component control means. When the falling of the INT signal is detected in the electrical component control means, the control command capturing process is started. However, any electrical component control means receives a new signal from the game control means before the capturing process is completed. It is not output to the signal line. That is, reliable command reception processing is performed in each electric component control means. In addition, each electric component control means may start taking in the control command at the rising edge of the INT signal. Further, the polarity of the INT signal may be reversed from that shown in FIG.

  In this embodiment, a plurality of command transmission tables are used as a ring buffer. In the command control process shown in FIG. 29, command output control is performed for the command transmission table pointed to by the read pointer, and command transmission is performed. In the process of setting data in the table, for example, the winning ball signal process shown in FIG. 27, the command setting process is performed for the command transmission table indicated by the writing pointer. Therefore, even if a plurality of command transmission requests are generated at the same time, command output processing based on these requests is executed without any problem.

  Next, command reception processing and the like in the electrical component control means will be described. Here, a command reception process and the like in the payout control means will be described.

  FIG. 31 is a block diagram illustrating a configuration example around the payout control CPU 371. As shown in FIG. 31, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is connected to the non-maskable interrupt terminal (XNMI terminal) of the payout control CPU 371 via the buffer circuit 960. Has been. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. VSL is the largest DC voltage used in gaming machines, and is + 30V in this example. Therefore, the payout control CPU 371 can confirm the occurrence of power interruption by the interrupt process.

  The payout control CPU 371 used in this embodiment also incorporates PIO and CTC, like the CPU 56 of the main board 31. However, the built-in PIO is not used in this embodiment. In that case, for example, all the ports are set to the input mode, and all the ports are connected to the ground level.

  Similarly to the CPU 56 of the main board 31, the payout control CPU 371 can be set to any one of the interrupt modes 0 to 2, and the CTC can operate in the timer mode or the counter mode as described below. is there. In this embodiment, channel 3 of the built-in CTC is used in the timer mode, and channel 2 is used in the counter mode. Channel 3 is used as a timer interrupt generation source, and channel 2 is used for receiving a payout control command. The payout control CPU 371 has a built-in CTC having a plurality of channels. The operation mode can be set for each channel.

  Counter mode: When the rising or falling edge of the clock signal is input to the CLK / TRG terminal of the payout control CPU 371, the count value is decremented by one. If interrupt generation permission is set for the channel, an interrupt is generated when the count value reaches 0, and the initial value is reloaded into the counter. If an interrupt vector has been set, the interrupt vector is transmitted onto the internal data bus when the count value reaches zero.

  Timer mode: The count value is decremented by -1 based on a clock signal obtained by dividing the system clock (internal clock) by 1/16 or 1/256. If interrupt generation permission is set for the channel, an interrupt is generated when the count value reaches 0, and the initial value is reloaded into the counter. If an interrupt vector has been set, the interrupt vector is transmitted onto the internal data bus when the count value reaches zero.

  An INT signal (payout control signal INT) from the main board 31 is connected to the CLK / TRG2 terminal of the payout control CPU 371. When a clock signal is input to the CLK / TRG2 terminal, the value of the timer counter register CLK / TRG2 (CTC channel 2 counter) incorporated in the payout control CPU 371 is down-counted. When the register value becomes 0, an interrupt occurs. Therefore, if the initial value of the timer counter register CLK / TRG2 is set to “1”, an interrupt is generated according to the input of the INT signal.

  Although a system reset circuit 975 is also mounted on the payout control board 37, in this embodiment, the system reset circuit 975 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, when the power is turned on, the reset IC 976 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level when the predetermined time elapses. In addition, the reset IC 976 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit mounted on the power supply board 910, and the voltage value falls below a predetermined value (for example, + 9V). Then, a low level voltage drop signal is generated. Therefore, when the power is turned off, the payout control CPU 371 is system-reset by the voltage drop signal from the reset IC 976 becoming low level. As shown in FIG. 31, the voltage drop signal is the same output signal as the reset signal.

  The predetermined value for the reset IC 976 to detect power-off is lower than the normal voltage, but is a voltage that allows the payout control CPU 371 to operate for a while. In addition, since the reset IC 976 is configured to monitor a voltage higher than the voltage required by the payout control CPU 371 (in this example, +5 V), the monitoring range for the voltage required by the payout control CPU 371 is used. Can be spread. Therefore, more precise monitoring can be performed.

  While power is not supplied from the + 5V power supply, at least a part of the internal RAM of the payout control CPU 371 is backed up by connecting the backup power supplied from the power supply board to the backup terminal, and the power to the gaming machine is cut off. The contents are saved. When the + 5V power supply is restored, a reset signal is issued from the system reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, since necessary data is backed up, it is possible to return to the gaming state at the time of the power failure when recovering from the power failure.

  As described above, in this embodiment, the first power supply monitoring circuit mounted on the power supply board 910 monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, and When the voltage of the power source falls below a predetermined value, a voltage drop signal (power failure detection signal) is generated. At the timing when the power-off detection signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is secured for the payout control CPU 371 of the payout control board 37 that operates at the IC drive voltage to perform a predetermined power supply stop process.

  Also in this case, the first power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, but the timing of generating the power supply interruption detection signal is the IC drive. The monitoring target voltage may not be the voltage of the highest power supply VSL as long as the operation time required for the electric component control means operating at the voltage to perform the predetermined power supply stop process is ensured. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off detection signal may be generated at such a timing that the operation time for the electrical component control means to perform the predetermined power supply stop process is secured. it can.

  In this case, as described above, since the voltage supplied to various switches of the gaming machine such as the prize ball count switch 301A is + 12V, the monitoring target voltage can be expected to prevent erroneous switch-on detection when the power is turned off. A voltage is preferred. That is, it is preferable that the voltage drop can be detected before the +12 V power supply voltage, which is the voltage supplied to the switch (switch voltage) starts to drop. Therefore, it is preferable to monitor a voltage higher than at least the switch voltage.

  In the configuration shown in FIG. 31, the system reset circuit 975 outputs a low level during a period determined by the capacitance of the capacitor when power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, as in the case of the main board 31 shown in FIG. 11, a circuit configuration that generates a plurality of reset release timings may be used.

  FIG. 32 is a flowchart showing main processing of the payout control CPU 371. In the main process, the payout control CPU 371 first performs necessary initial settings (step S701).

  FIG. 33 is a flowchart showing the initial setting process in step S701. In the initial setting process, the payout control CPU 371 first sets the interrupt prohibition (step S701a). Next, the payout control CPU 371 sets the interrupt mode to interrupt mode 2 (step S701b), and sets the stack pointer designation address in the stack pointer (step S701c). The payout control CPU 371 initializes the built-in device register (step S701d), initializes the CTC and PIO (step S701e), and then sets the RAM in an accessible state (step S701f).

  In this embodiment, one channel of the built-in CTC is used in the timer mode. Accordingly, in the built-in device register setting process in step S701d and the process in step S701e, register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set. Then, the interrupt by the channel is used as the timer interrupt described above. If it is desired to generate a timer interrupt every 2 ms, for example, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

  The interrupt vector set for the channel set to the timer mode corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interrupt process, a timer interrupt flag is set. When it is detected in the main process that the timer interrupt flag is set, a payout control process is executed. That is, in the timer interrupt process, settings for executing a payout control process, which is an example of an electrical component control process, are made.

  Further, another channel of the built-in CTC is used in the counter mode. Accordingly, in the built-in device register setting process in step S701d and the process in step S701e, register setting for setting the channel to be used to the counter mode, register setting for permitting interrupt generation, and setting an interrupt vector. The register is set.

  The interrupt vector set for the channel set to the counter mode corresponds to the head address of the command reception interrupt process described later. Specifically, the start address of the command reception interrupt process is specified by the value set in the I register and the interrupt vector.

  In this embodiment, the interruption mode 2 is also set in the payout control CPU 371. Therefore, it is possible to use an interrupt process based on counting up the built-in CTC. Further, it is possible to set an interrupt processing start address corresponding to the interrupt vector transmitted by the CTC.

  The interrupt based on the count-up of the CTC channel 2 (CH2) is an interrupt that occurs when the value of the timer counter register CLK / TRG2 described above becomes “0”. Therefore, for example, in step S701e, the initial value “1” is set in the timer counter register CLK / TRG2. An interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”. Used as an interrupt. Specifically, the register value of CH3 is subtracted at 1/256 period of the system clock. In step S701e, the CH3 register is set to a value corresponding to 2 ms as an initial value. In this embodiment, the interrupt address for CH2 is 0074H, and the interrupt address for CH3 is 0076H.

  Then, the payout control CPU 371 checks whether backup data exists in the payout control backup RAM area (step S702). That is, for example, similarly to the processing of the CPU 56 of the main board 31, whether or not backup data exists is confirmed by whether or not the backup flag that is set when the power is turned off is set. If the backup flag is set, it is determined that there is backup data. If it is determined that there is no backup data, there is no unpaid game ball at the previous power-off, and there is no need to return the internal state to the state at the time of power-off. Accordingly, the payout control CPU 371 executes an initialization process that is executed when the power is turned on but not when the power failure is restored (steps S702 and S703).

  When backup data exists in the backup RAM area, the payout control CPU 371 performs data check (parity check in this example) of the backup RAM area (step S704). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state at the time of power-off, and therefore an initialization process that is executed at the time of power-on not at the time of power failure recovery is executed (steps S705 and S703).

  If the check result is normal, the payout control CPU 371 performs a payout state recovery process for returning the internal state to the state when the power is turned off (step S706). Then, it returns to the address indicated by the PC (program counter) stored in the backup RAM area (step S707).

  When execution of the normal initialization process (step S703) is finished, the main process executed by the payout control CPU 371 shifts to a loop process in which the monitoring of the timer interrupt flag (step S708) is confirmed.

  In this embodiment, after the presence / absence of backup data is confirmed in step S702, the backup area is checked in step S704 when the backup data exists. After confirming that the data is normal, the presence / absence of backup data may be confirmed. In addition, it may be configured to determine whether or not to execute the power failure recovery process by confirming either one of the presence / absence of backup data or the check of the backup area.

  Also, for example, when performing parity check (step S704) when determining whether or not to execute a power failure recovery process, that is, when determining whether or not to restore the gaming state, payout in the stored RAM data If it is confirmed from the game ball number data or the like that the gaming machine is in a payout waiting state (a state that is not in the middle of payout), the initialization process may be executed without performing the payout state recovery process.

  In the normal initialization process, as shown in FIG. 34, a register and RAM clear process (step S901) is performed, and a predetermined initial value is set (step S902). Since the interruption is prohibited in the initial setting process (step S701a), the interruption is permitted before the initialization process is completed (step S903).

  In this embodiment, the CTC CH3 of the payout control CPU 371 is set to repeatedly generate a timer interrupt. Further, the repetition period is set to 2 ms. Then, as shown in FIG. 35, when a timer interruption occurs, the payout control CPU 371 sets a timer interruption flag (step S721). In FIG. 35, it is also clearly indicated that the interrupt is permitted (step S720). In the 2 ms timer interrupt process, the interrupt permission state is first set. That is, the interrupt is permitted during the 2 ms timer interrupt process.

  When detecting that the timer interrupt flag is set in step S708, the payout control CPU 371 resets the timer interrupt flag (step S709) and executes a payout control process (step S710). With the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the payout control process is executed in the main process, but the payout control process may be executed in the timer interrupt process.

  When the power is turned on, the payout control CPU 371 can determine whether to perform normal initial setting processing or restore the paying-out state only by checking the data in the backup RAM area. That is, the payout process can be resumed for the game balls that have not been paid out by simple determination. Further, in this embodiment, as with the game control in the main board 31, the stored content is ensured by the parity check code.

  FIG. 36 is an explanatory diagram showing a usage example of the RAM built in the payout control CPU 371. In this example, a total number storage (for example, 2 bytes) and a lending ball number storage are formed in the backup RAM area. The total number storage stores the total number of payouts instructed from the main board 31 side. The rented ball number storage stores the number of balls that have not been paid out.

  FIG. 37 is an explanatory diagram showing a configuration example of a reception buffer for storing a payout control command received from the main board 31. In this example, a ring buffer type reception buffer capable of storing six 2-byte payout control commands is used. Therefore, the reception buffer is configured by a 12-byte area of the confirmed command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

  FIG. 38 is a flowchart showing a payout control command reception process by an interrupt process. The payout control INT signal from the main board 31 is input to the CLK / TRG2 terminal of the payout control CPU 371. Therefore, when the INT signal from the main board 31 is turned on, the payout control CPU 371 is interrupted, and the payout control command reception process shown in FIG. 38 is started.

  Although the command reception process of the payout control unit will be described here, the same command reception process is also executed in the display control unit, the lamp control unit, and the voice control unit.

  In the payout control command reception process, the payout control CPU 371 first saves each register in the stack (step S850). Next, data is read from the input port 372a assigned to input of the payout control command data (step S851). Then, it is confirmed whether or not it is the first byte of the 2-byte payout control command (step S852). Whether or not it is the first byte is confirmed by whether or not the first bit of the received command is “1”. The first bit “1” should be the MODE byte (first byte) of the payout control command having a 2-byte configuration (see FIG. 19). Therefore, if the first bit is “1”, the payout control CPU 371 determines that the valid first byte has been received, and stores the received command in the confirmed command buffer indicated by the command reception number counter in the reception buffer area (step S31). S853).

  If it is not the first byte of the payout control command, it is confirmed whether or not the first byte has already been received (step S854). Whether or not it has already been received is confirmed by whether or not valid data is set in the reception buffer (deterministic command buffer).

  If the first byte has already been received, it is confirmed whether or not the first bit of the received 1 byte is “0”. If the first bit is “0”, it is determined that the valid second byte has been received, and the received command is stored in the confirmed command buffer indicated by the command reception number counter + 1 in the reception buffer area (step S855). The leading bit “0” should be the EXT byte (second byte) of the payout control command having a 2-byte configuration (see FIG. 19). If the confirmation result in step S854 indicates that the first byte has already been received, the process ends unless the first bit of the data received as the second byte is “0”.

  When the second byte of command data is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is confirmed whether or not the command reception counter is 12 or more (step S857). If it is 12 or more, the command reception number counter is cleared (step S858). Thereafter, the saved register is restored (step S859), and interrupt permission is set (step S859).

  Interrupts are disabled during command reception interrupt processing. As described above, since the interrupt is enabled during the 2 ms timer interrupt processing, if a command reception interrupt occurs during the 2 ms timer interrupt, the command reception interrupt processing is executed with priority. The Even if a 2 ms timer interrupt occurs during command reception interrupt processing, the interrupt processing is awaited. Thus, in this embodiment, the processing priority of command reception processing from the main board 31 is high. Further, since no other interrupt processing is executed during command reception processing, the maximum time required for command reception processing is determined. If the configuration is such that another interrupt process can be executed during the command reception process, it is difficult to estimate the longest time required for the command reception process. Since the longest time required for the command reception process is determined, it is possible to accurately determine how long the period C (see FIG. 20) in the command transmission process of the game control means should be.

  The payout control command has a 2-byte configuration, and the first byte (MODE) and the second byte (EXT) can be immediately distinguished on the receiving side. In other words, the reception side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received.

  FIG. 39 is a flowchart showing the payout control process in step S710. In the payout control process, the payout control CPU 371 first determines whether or not the prize ball count switch 301A and the ball lending count switch 301B input to the input port 372b via the relay board 72 are turned on (switch process: Step S751).

  Next, the payout control CPU 371 performs processing such as checking the signal input state from a sensor (for example, a motor position sensor that detects the rotation speed of the payout motor 289) and determining the state of the sensor (input determination processing). : Step S752). The payout control CPU 371 further analyzes the received payout control command and executes a process according to the analysis result (command analysis execution process: step S753).

  Next, the payout control CPU 371 sets the payout stop state if the payout stop instruction command is received from the main board 31, and cancels the payout stop state if the payout start instruction command is received (step S754). Further, a prepaid card unit control process is performed (step S755).

  Next, the payout control CPU 371 performs control for paying out the rental balls in response to the ball rental request (step S756). Further, the payout control CPU 371 performs prize ball control processing for paying out the number of prize balls stored in the total number memory (step S757). Then, the payout control CPU 371 outputs a drive signal to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72, and the ball lending control process in step S756 or the step S757. A payout motor control process for rotating the payout motor 289 by the number of rotations set in the prize ball control process is performed (step S758).

  In this embodiment, a stepping motor is used as the payout motor 289, and a 1-2 phase excitation method is used to control the payout motor 289. Therefore, specifically, eight types of excitation pattern data are repeatedly output to the payout motor 289 in the payout motor control process. In this embodiment, each excitation pattern data is output by 4 ms.

  Next, error detection processing is performed, and predetermined display is performed on the error display LED 374 according to the result (error processing: step S759). For example, the following eight types of errors are detected.

  Prize ball path error: When the prize ball payout operation is completed, or when no prize ball count switch 301A detects the passing of a game ball when the payout motor 289 rotates once. “0” is displayed on the error display LED 374.

  Ball lending route error: When ball lending payout operation is completed, or when the ball lending count switch 301B detects no passing of the game ball when the payout motor 289 makes one rotation. “1” is displayed on the error display LED 374.

  Prize ball count switch ball clogging error: Prize ball count switch 301A detects ON for 0.5 seconds or more. “2” is displayed on the error display LED 374.

  Ball lending count switch ball clogging error: When ball lending count switch 301B detects ON for 0.5 seconds or more. “3” is displayed on the error display LED 374.

  Discharge motor ball biting error: When the discharge motor 289 does not rotate normally. Specifically, when the payout motor position sensor has been turned on for a predetermined period or longer or has been turned off for a predetermined period or longer. “4” is displayed on the error display LED 374. When a payout motor ball biting error occurs, the payout control CPU 371 outputs the reference excitation phase for 50 ms, and then outputs four types of excitation pattern data among the excitation pattern data for 1-2 phase excitation. Is repeated every 8 ms to repeat reverse rotation and forward rotation of the dispensing motor 289.

  Prepaid card unit unconnected error: When VL signal OFF is detected. “5” is displayed on the error display LED 374.

  Prepaid card unit communication error: When it is detected that a signal is output from the prepaid card unit 50 at a timing other than the prescribed timing. “6” is displayed on the error display LED 374.

  Discharge stop state: When a payout control command indicating a payout stop is received from the main board 31. “7” is displayed on the error display LED 374. When a payout control command indicating the payout start is received from the main board 31, the payout stop state is returned to the payable state after 2002 ms.

  Further, a process for controlling an information signal output from an external connection terminal (not shown) is performed (output process: step S760). The information signal is a signal that is turned on for a predetermined time for each lending ball payout unit (for example, 25) and subsequently outputs OFF for a predetermined time.

  FIG. 40 is a flowchart illustrating an example of the switch processing in step S751. In the switch process, the payout control CPU 371 checks whether or not the prize ball count switch 301A indicates the on state (step S751a). If the on state is indicated, the payout control CPU 371 increments the prize ball count switch on counter by 1 (step S751b). The prize ball count switch on counter is a counter for counting the number of times the on state of the prize ball count switch 301A is detected.

  Then, the value of the prize ball count switch-on counter is checked (step S751c). If the value is 2, it is determined that one prize ball has been paid out. When it is determined that one prize ball has been paid out, the payout control CPU 371 decrements the prize ball non-payout counter (the number of prize balls stored in the total number memory) by −1 (step S751d).

  When it is confirmed in step S751a that the prize ball count switch 301A is not in the on state, the payout control CPU 371 clears the prize ball count switch on counter (step S751e). In this embodiment, it is checked whether or not the ball lending count switch 301B indicates the on state (step S751f). If the on state is indicated, the payout control CPU 371 increments the ball lending count switch on counter by 1 (step S751g). The ball lending count switch on counter is a counter for counting the number of times that the ball lending count switch 301B is turned on.

  Then, the value of the ball lending count switch-on counter is checked (step S751h). If the value is 2, it is determined that one lending ball has been paid out. If it is determined that one lending ball has been paid out, the payout control CPU 371 decrements the lending ball unpaid-out number counter (the number of lending balls stored in the lending ball number storage) (step S751i). ).

  When it is confirmed in step S751f that the ball lending count switch 301B is not in the on state, the payout control CPU 371 clears the ball lending count switch on counter (step S751j).

  FIG. 41 is a flowchart illustrating an example of the command analysis execution process in step S753. In the command analysis execution process, the payout control CPU 371 checks whether or not there is a received command in the confirmed command buffer area (step S753a). If there is a received command, it is checked whether or not the received payout control command is a payout number instruction command (step S753b). If there are a plurality of received commands in the fixed command buffer area, whether or not the received payout control command is a payout number instruction command is checked for the received command received the earliest. Is called.

  If the received payout control command is a payout number instruction command, the number specified by the payout number instruction command is added to the total number memory (step S753c). That is, the payout control CPU 371 stores the number of prize balls included in the payout number instruction command sent from the CPU 56 of the main board 31 in the backup RAM area (total number memory).

  The payout control CPU 371 performs subtraction of the command reception number counter and reception command shift processing in the confirmed command buffer area, if necessary.

  FIG. 42 is a flowchart illustrating an example of the payout stop state setting process in step S754. In the payout stop state setting process, the payout control CPU 371 checks whether or not there is a received command in the confirmed command buffer area (step S754a). If there is a received command in the fixed command buffer area, it is checked whether or not the received payout control command is a payout stop instruction command (step S754b). If it is a payout stop instruction command, the payout control CPU 371 sets the payout stop state (step S754c).

  If it is confirmed in step S754b that the received command is not a payout stop instruction command, it is checked whether or not the received payout control command is a payout start instruction command (step S754d). If it is a payout start instruction command, the payout stop state is canceled (step S754e).

  FIG. 43 is a flowchart showing an example of the prepaid card unit control process in step S755. In the prepaid card unit control process, the payout control CPU 371 checks whether or not a VL signal input from the card unit control microcomputer has been detected (step S755a). If the VL signal is not detected, the VL signal non-detection counter is incremented by 1 (step S755b). Also, the payout control CPU 371 checks whether or not the value of the VL signal non-detection counter is 125 in this example (step S755c). If the value of the VL signal non-detection counter is 125, the payout control CPU 371 stops the emission control signal output to the emission control board 91 and stops the drive motor 94 (step S755d).

  If the VL signal is detected to be off 125 times (2 ms × 125 = 250 ms) continuously by the above processing, the ball firing prohibited state is set.

  If the VL signal is detected in step S755a, the payout control CPU 371 clears the VL signal non-detection counter (step S755e). If the discharge control CPU 371 stops outputting the firing control signal (step S755f), the payout control CPU 371 starts outputting the firing control signal to the firing control board 91 to enable the drive motor 94 (step S755g). .

  44 and 45 are flowcharts showing an example of the ball lending control process in step S756. In this embodiment, the maximum value of the continuous payout number is set as one unit (for example, 25) of the lending ball, but the maximum value of the continuous payout number may be another number.

  In the ball lending control process, the payout control CPU 371 checks whether or not the lending ball is being paid out (step S511). If the lending ball is being paid out, the process proceeds to the ball lending process shown in FIG. Whether or not the lending ball is being paid out is determined by the state of a ball lending process flag which will be described later. If the rental ball is not being paid out, it is confirmed whether or not the prize ball is being paid out (step S512). Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout, the payout control CPU 371 checks whether or not a ball lending request has been received from the card unit 50 (step S513). If there is a request, the ball lending process flag is turned on (step S514), and 25 (number of ball lending units: here 100 yen) is set in the lending ball number storage in the backup RAM area (step S515). Then, the payout control CPU 371 turns on the EXS signal (step S516). Further, the distribution solenoid 310 is driven to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side (step S517). Further, the payout motor 289 is turned on (step S518), and the process proceeds to the ball lending process shown in FIG.

  Strictly speaking, the payout motor 289 is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized acceptance. The ball lending process flag is set in the backup RAM area.

  FIG. 45 is a flowchart showing a ball lending process in the payout control process by the payout control CPU 371. In the ball lending process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch processing in step S751, it is confirmed whether or not a game ball has been paid out based on the detection output of the ball lending count switch 301B. Therefore, the ball lending control processing subtracts the lending ball number storage. Is not done. In the ball lending control process, the payout control CPU 371 checks whether or not it is during the lending ball passage waiting time (step S519). If it is not during the lending ball passage waiting time, the lending ball is paid out (step S520), and it is confirmed whether or not the driving of the payout motor 289 should be finished (whether the payout operation of one unit has been finished) (step S521). ). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S522) and sets the lending ball passage waiting time (step S523).

  In the ball lending process in step S520, the on / off state of the payout motor position sensor is monitored by a timer. If the on state or the off state continues for a predetermined time or longer, the payout control CPU 371 issues a payout motor ball bit error. Is determined to have occurred.

  If it is during the lending ball passage waiting time in step S519, the payout control CPU 371 checks whether or not the lending ball passage waiting time has ended (step S524). The rental ball passage waiting time is the time from when the last payout ball is paid out by the payout motor 289 until it passes through the ball lending count switch 301B. When confirming the end of the lending ball passage waiting time, all lending balls of one unit have been paid out, so that the card unit 50 can accept the next lending request. The EXS signal is turned off (step S524). Further, the distribution solenoid is turned off (step S525), and the ball lending process flag is turned off (step S527). If the last payout ball does not pass the ball lending count switch 301B before the lending ball passage waiting time elapses, a ball lending route error is determined. In this embodiment, the winning ball and the lending are performed by the same payout device.

  After turning off the EXS signal indicating acceptance of a ball lending request, if the BRQ signal, which is a ball lending request signal, is turned on again within a predetermined period, the ball lending process is continued without turning off the sorting solenoid and the dispensing motor. You may make it do. That is, instead of performing the ball lending process for each predetermined unit (100 yen unit in this example), the ball lending process may be executed continuously.

  The contents of the rental ball number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the gaming machine is powered off. Accordingly, when the power supply is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

  46 and 47 are flowcharts showing an example of the prize ball control process in step S757. In this example, the maximum value of the continuous payout number is the same as the unit of the lending ball (for example, 25), but the maximum value of the continuous payout number may be another number.

  In the winning ball control process, the payout control CPU 371 checks whether or not the lending ball is being paid out (step S531). Whether or not the ball lending is being paid out is determined by the state of the ball lending process flag. If it is not in the lending ball payout, it is confirmed whether or not the award ball is being paid out (step S532). If the award ball is being paid out, the process proceeds to the award ball processing shown in FIG. Whether or not a prize ball is being paid out is determined based on a state of a prize ball processing flag to be described later.

  If neither the lending ball payout nor the prize ball payout is found, the payout control CPU 371 checks whether or not there is a ball lending preparation request from the card unit 50 (step S533). Whether or not there is a ball lending preparation request is determined by confirming whether the BRDY signal input from the card unit 50 is on (requested) or off (no request).

  If there is no ball lending preparation request from the card unit 50, the payout control CPU 371 checks whether or not the number of prize balls (number of unpaid prize balls) stored in the total number memory is 0 (step S534). . If the number of prize balls stored in the total number memory is not 0, the prize ball control CPU 371 turns on a prize ball processing flag (step S535), and whether or not the value of the total number memory is 25 or more. Confirmation is made (step S536). The prize ball processing flag is set in the backup RAM area.

  If the number of prize balls stored in the total number memory is 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate the payout motor 289 until paying out 25 game balls. In order to output 25, the payout operation of 25 is set (step S537). If the number of prize balls stored in the total number memory is not 25 or more, the payout control CPU 371 drives the payout motor 289 to rotate until all the game balls stored in the total number memory are paid out. In order to output the total number delivery operation (step S538). Next, the payout motor 289 is turned on (step S538). Since the distribution solenoid is in the off state, the ball distribution member below the ball dispensing device 97 is set to the prize ball side. Then, the process proceeds to a process during payout of prize balls in the prize ball control process shown in FIG.

  FIG. 47 is a flowchart showing an example of processing during a prize ball in the payout control processing by the payout control CPU 371. In the winning ball control process, if the payout motor 289 is not turned on, it is turned on. In this embodiment, in the switch process in step S751, it is confirmed whether or not a game ball has been paid out based on the detection output of the prize ball count switch 301A. Therefore, in the prize ball control process, the total number memory is subtracted. Is not done. In the processing during the winning ball, the payout control CPU 371 checks whether or not it is during the waiting time for winning ball passing (step S540). If it is not during the waiting time for passing the prize ball, the prize ball is paid out (step S541), and whether or not the driving of the payout motor 289 should be terminated (whether a predetermined number of payout operations of 25 or less than 25 has been completed). Is confirmed (step S542). Specifically, it is confirmed whether or not the rotation corresponding to the predetermined number of payouts has been completed. The rotation corresponding to the predetermined number of payouts is monitored by the output of the payout motor position sensor. When the rotation corresponding to the predetermined number of payouts is completed, the payout control CPU 371 stops driving the payout motor 289 (step S543), and sets the award ball passage waiting time (step S544). The award ball passing waiting time is a time from when the last payout ball is paid out by the payout motor 289 until it passes through the prize ball count switch 301A.

  If it is during the winning ball passage waiting time in step S540, the payout control CPU 371 checks whether or not the winning ball passage waiting time has ended (step S545). When the prize ball passing waiting time ends, all the prize balls set in step S537 or step S538 have been paid out. Therefore, the payout control CPU 371 turns off the award ball processing flag if the award ball passage waiting time has ended (step S546). If the last payout ball does not pass the prize ball count switch 301A before the prize ball passage waiting time elapses, a prize ball path error is determined.

  In this embodiment, the ball lending is prioritized over the winning ball processing according to the determinations in steps S511 and S531, but the winning ball processing may be prioritized over the ball lending.

  The contents of the total number storage and the rented ball number storage are stored by the backup power source of the power supply board 910 for a predetermined period even when the gaming machine is powered off. Therefore, when the power is restored during the predetermined period, the payout control CPU 371 can continue the payout process based on the contents of the total number storage.

  The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as a total number in the prize ball number storage, but may manage each prize ball number (for example, 15, 10, or 6). Good. For example, a number counter corresponding to the number of winning balls is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When a prize ball payout corresponding to the number counter is performed, the number counter is decremented by 1 (in this case, a subtraction process is performed in the payout control process). Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is cut off, if the power recovers during a predetermined period, the payout control CPU 371 can continue the prize ball payout process based on the contents of each number counter.

  FIG. 48 is a flowchart showing an example of a power failure occurrence NMI process executed in response to the NMI based on the voltage change signal from the power supply monitoring circuit of the power supply board 910. In this embodiment, the NMI interrupt address is 0066H. In the power failure occurrence NMI process, the payout control CPU 371 first stores the contents of the interrupt prohibition flag in the parity flag (step S801). Next, interrupt prohibition is set (step S802). In the power failure occurrence NMI process, in this example, a checksum generation process for ensuring the storage of the RAM contents is performed as in the process executed on the main board 31. If another interrupt process is performed during the process, it may be possible that the checkout generation process is not completed before the payout control CPU 371 drops to a voltage at which it cannot operate. The setting is made so that no other interruption occurs. Note that steps S804 to S810 in the power failure occurrence NMI process are an example of a power supply stop process.

  Note that the processing in step S802 is not necessary when a CPU having a specification that does not cause other interrupts during the interrupt processing is used.

  Next, the payout control CPU 371 checks whether or not the backup flag has already been set (step S803). If the backup flag is already set, no further processing is performed. If the backup flag is not set, the following power supply stop process is executed. That is, the processing from step S804 to step S810 is executed.

  First, the contents of each register are stored in the backup RAM area (step S804). Thereafter, a backup flag is set (step S805). Then, an appropriate initial value is set in the backup check data area of the backup RAM area (step S806), the exclusive value is sequentially obtained for the initial value and the data in the backup RAM area, and then inverted (step S807). The calculated value is set in the backup parity data area (step S808). In addition, the RAM access is prohibited (step S809). When the power supply voltage is lowered, the level of various signal lines may become unstable and the contents of the RAM may be altered, but if the RAM access is prohibited in this manner, the data in the backup RAM will be altered. There is no.

  Further, the payout control CPU 371 outputs a clear signal to all output ports (in this embodiment, output port portions of the output ports 372c, 372g, and 372e and the I / O port 372f). Accordingly, all the output ports are turned off by the clear signal (step S810).

  Next, the payout control CPU 371 enters a loop process. That is, no processing is performed. Therefore, the operation is internally stopped before the operation is disabled from the outside by the system reset signal from the reset IC 976 shown in FIG. Therefore, the payout control CPU 371 reliably stops operation when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the RAM contents from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

  In this embodiment, in the power failure occurrence NMI processing, the program is looped at the final part, but a halt (HALT) instruction may be issued.

  Further, as described above, the backup flag that is set after the register contents are stored in the RAM area determines whether or not there is backup data to be restored when the power is turned on (whether or not it is restored from a power failure). Used when. Further, the processing of steps S801 to S810 is completed before the payout control CPU 371 receives the system reset signal from the system reset circuit 975. In other words, the detection voltage of the voltage monitoring circuit is set so as to be completed before the system reset signal from the system reset circuit 975 is received.

  In this embodiment, the backup flag is confirmed at the start of the power supply stop process. If the backup flag is already set, the power supply stop process is not executed. As described above, the backup flag is a flag indicating that the backup of necessary data has been completed and the power supply stop process has been completed thereafter. Therefore, for example, even if NMI occurs again for some reason in a loop waiting for reset, the power supply stop process is not repeatedly executed.

  However, if a CPU with a specification that does not cause other interrupts during interrupt processing is used, the determination in step S803 is not necessary.

  In this embodiment, the payout control CPU 371 detects the NMI interrupt signal from the power supply board (NMI interrupt signal from the power supply monitoring means) via the non-maskable external interrupt terminal (NMI terminal). The NMI interrupt signal may be introduced to the maskable interrupt terminal (INT terminal). In that case, the power failure occurrence NMI process shown in FIG. 48 is executed by the INT process. Further, an NMI interrupt signal may be detected via the input port. In that case, the input port is monitored in the main process executed by the payout control CPU 371.

  FIG. 49 is an explanatory diagram for explaining an example of a backup parity data creation method. However, in the example shown in FIG. 49, for the sake of simplicity, the size of the data in the backup data RAM area is 3 bytes. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 49, initial data (00H in this example) is set in the backup check data area. Next, an exclusive logical sum of “00H” and “F0H” is taken, and an exclusive logical sum of “16H” is obtained. Further, an exclusive OR of the result and “DFH” is taken. Then, a value (“C6H” in this example) obtained by inverting the result (“39H” in this example) is set in the backup parity data area.

  When power is turned on again, parity diagnosis is performed in the power failure recovery process. If all data in the backup area is stored as it is, data as shown in FIG. 49 is set in the backup area when the power is turned on again.

  In the process of step S704, the payout control CPU 371 performs the same process as the process executed in steps S806 and S807 of FIG. That is, initial data (00H in this example) is set in the backup check data area, an exclusive OR of “00H” and “F0H” is taken, and an exclusive OR of “16H” is taken with the result. . Further, an exclusive OR of the result and “DFH” is taken. Then, a final calculation result obtained by inverting the result (“39H” in this example) is obtained. If all the data in the backup area is stored as it is, the final calculation result matches “C6H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is not “C6H”.

  Therefore, the payout control CPU 371 compares the final calculation result with the data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

  As described above, in this embodiment, the payout control means is provided with a storage means (in this example, a backup RAM) that is backed up for a predetermined period of time even when the gaming machine is turned off. The payout control CPU 371 (specifically, the program executed by the payout control CPU 371) performs a payout state recovery process (step S706) for recovering the payout state based on the backup data if the storage means is in the backup state. Composed.

Hereinafter, the payout state recovery process will be described.
FIG. 50 is a flowchart showing an example of the payout state restoration process shown in step S706 of FIG. In this example, the payout control CPU 371 restores the value stored in the backup RAM to the register (step S861). And the process for recovering the payout state at the time of power failure is performed based on the data stored in the backup RAM. For example, an in-price ball processing flag is set.

  When the payout state is restored, in this embodiment, the payout control CPU 371 checks the value of the parity flag stored in the backup RAM in order to restore the interrupt permission / prohibition state at the previous power-off. (Step S862). If the parity flag is clear, interrupt permission setting is performed (step S863). On the other hand, if the parity flag is on, the payout state recovery process is finished as it is (while keeping the interrupt disabled state set in step S701a).

  Here, the payout state recovery processing program is configured to return to the payout control main process when the payout state recovery process ends, but the stack area (pointed to by the stack pointer stored in the power supply stop process) It is also possible to return to the address stored in the backup RAM area (the address that was executed when the NMI interrupt occurred when the power was turned off).

  As described above, after the initial setting process is started, the interrupt disabled state is set before the payout state restoration process is completed or until the initialization process is completed. Therefore, it is possible to prevent the processing from being interrupted by an interrupt. As a result, it is possible to reliably complete the initial setting, the determination as to whether or not to restore the payout state when the power is turned off, which is performed according to the contents of the backup data storage area, and the restoration process (or initialization process). Note that even if the interrupt is disabled until the recovery process is completed as described above, the interrupt disabled / permitted state at power-off is stored in the parity flag. It is possible to reliably restore the interrupt disabled / permitted state when the power is turned off.

  In each of the embodiments, the payout control means is taken as an example. However, other electrical component control means such as a display control means, a sound control means, a lamp control means, etc. are also processed from the game control means by the above-described processing. The control command can be received reliably. Further, the display control means, the sound control means, the lamp control means, and the like are also configured to perform the power supply monitoring control described above, and a clear signal is output in the power failure occurrence NMI process, and each electric component control means controls. You may make it stop the action | operation of an electrical component. If comprised in that way, before it will be in a stop state, the operation | movement of each electric component can be made into a stop state, and it can wait for a power supply restoration in a suitable stop state.

  In the above embodiment, the power supply monitoring circuit is provided on the power supply board 910. However, the power supply monitoring circuit may be provided on an electrical component control board such as the main board 31 or the payout control board 37. When an electric component control board on which a power supply circuit is mounted is configured, a power supply monitoring circuit is not mounted on the power supply board.

  In the pachinko gaming machine 1 according to each of the above-described embodiments, a predetermined game value can be given to a player when a special symbol stop symbol variably displayed on the variable display unit 9 based on the start winning combination is a combination of a predetermined symbol The second type pachinko gaming machine that becomes a predetermined game value can be given to the player when there is a winning in a predetermined area of the electric game that is released based on the start winning Or a third type pachinko gaming machine in which a predetermined right is generated or continued when a winning is given to a predetermined electric accessory that is released when the symbol of the symbol variably displayed based on the start winning is a combination of the predetermined symbols Even so, the present invention can be applied.

  Furthermore, the present invention is not limited to pachinko gaming machines, and the present invention can be applied to slot machines and the like when electrical components that perform some kind of operation are provided.

It is the front view which looked at the pachinko game machine from the front. It is a whole rear view which shows the internal structure of a pachinko gaming machine. It is the rear view which looked at the mechanism board of the pachinko game machine from the back. It is a front view which shows the structure around the intermediate | middle base unit installed in the mechanism board. It is a disassembled perspective view which shows a ball dispensing apparatus. It is a block diagram which shows the circuit structure of a game control board (main board). It is a block diagram which shows the circuit structure in a display control board. It is a block diagram which shows the circuit structure in a lamp control board. It is a block diagram which shows the circuit structure in an audio | voice control board. It is a block diagram which shows the component relevant to prize balls, such as a component of a payout control board and a ball payout apparatus. It is a block diagram which shows one structural example of CPU periphery for a power supply monitoring and a power supply backup. It is a block diagram which shows one structural example of a power supply board. It is a flowchart which shows the example of the main process which CPU in a main board | substrate performs. It is explanatory drawing which shows the example of the determination method of whether to perform a game state restoration process. It is a flowchart which shows the example of an initialization process. It is a flowchart which shows the example of an initialization process. It is a flowchart which shows the example of a 2ms timer interruption process. It is a flowchart which shows the example of a game control process. It is explanatory drawing which shows one structural example of the payout control command. It is a timing diagram which shows the relationship between a control signal and an INT signal. It is explanatory drawing which shows an example of the content of the payout control command. It is explanatory drawing which shows an example of the content of a display control command. It is explanatory drawing which shows an example of the content of a lamp control command. It is explanatory drawing which shows an example of the content of a voice control command. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a switch process. It is a flowchart which shows a winning ball signal process. It is explanatory drawing which shows the structure of a command transmission table. It is a flowchart which shows a command control process. It is a flowchart which shows a command transmission process. It is a block diagram which shows the example of 1 structure around the payout control CPU for power supply monitoring and power supply backup. It is a flowchart which shows the example of the main process which CPU for payout control performs. It is a flowchart which shows an example of the initial setting process of payout control CPU. It is a flowchart which shows an example of the initialization process of CPU for payout control. It is a flowchart which shows the example of the timer interruption process of payout control CPU. It is explanatory drawing which shows one structural example of RAM in the payout control means. It is explanatory drawing which shows the example of 1 structure of a reception buffer. It is a flowchart which shows the example of the command reception processing of CPU for payout control. It is a flowchart which shows the example of the payout control process which CPU for payout control performs. It is a flowchart which shows the example of a switch process. It is a flowchart which shows the example of a command analysis execution process. It is a flowchart which shows the example of a payout stop state setting process. It is a flowchart which shows the example of a prepaid card unit control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a ball lending control process. It is a flowchart which shows the example of a prize ball control process. It is a flowchart which shows the example of a prize ball control process. It is a flowchart which shows the example of the power failure generation | occurrence | production NMI process which CPU for payout control performs. It is explanatory drawing for demonstrating the example of the backup parity data creation method. It is a flowchart which shows the example of the payout state recovery process which CPU for payout control performs.

Explanation of symbols

1 Pachinko machine 31 Main board 37 Payout control board 53 Basic circuit 56 CPU
371 CPU for payout control
570 output port (output port 0)
571 Output port (Output port 1)
572 Output port (Output port 2)
573 Output port (Output port 3)
574 Output port (Output port 4)
902 Power supply monitoring IC
910 Power supply board

Claims (4)

A game is performed using a game ball, and a variable display unit capable of variably displaying identification information is provided, and a predetermined game value is played when a display result of the variable display unit is in a predetermined specific display mode. A gaming machine to give
A game control microcomputer that controls the progress of the game and outputs a command as command information;
A plurality of electrical component control microcomputers that receive commands from the gaming control microcomputer and perform electrical component control processing for controlling electrical components provided in the gaming machine according to the received commands;
The plurality of electric component control microcomputers include a payout control microcomputer that controls a ball payout device as the electric component for paying out a game ball, and a display control microcomputer that controls the variable display unit as the electric component. Including a computer,
The game control microcomputer outputs information that can specify a variable display mode to the display control microcomputer as the command when variable display of the identification information in the variable display unit is started. Command output means for outputting information that can specify the stop of identification information when the display is ended as the command,
The command is composed of 2-byte command data,
The game control microcomputer executes command output processing for outputting command data and a capture signal designating capture of command data to the payout control microcomputer and the display control microcomputer, In the command output process, the command data for the payout control microcomputer and the display control microcomputer and the capture signal are output by calling the same subroutine.
The gaming control microcomputer outputs command data of the first byte in the command and outputs a capture signal, and then outputs command data of the second byte after a predetermined period of time elapses,
The game control microcomputer uses the predetermined period as a value equal to or greater than a maximum period of periods required for the payout control microcomputer and the display control microcomputer to receive command data. A gaming machine characterized by outputting data. When a game is played using a game ball, a variable display unit capable of variably displaying identification information is provided, and a predetermined game value is obtained when a display result of the variable display unit becomes a predetermined display mode. A gaming machine to be given to a player,
A game control microcomputer that controls the progress of the game and outputs a command as command information;
A plurality of electrical component control microcomputers that receive commands from the gaming control microcomputer and perform electrical component control processing for controlling electrical components provided in the gaming machine according to the received commands;
The plurality of electric component control microcomputers control a payout control microcomputer for controlling a ball payout device as the electric component for paying out a game ball, and a light emitter as the electric component provided in the gaming machine. And a microcomputer for controlling the illuminant to perform,
The game control microcomputer is:
Information that can specify the display mode of the light emitter corresponding to the variable display mode of the identification information in the variable display unit when the variable display of the identification information in the variable display unit is started to the microcomputer for controlling the light emitter. And a command output means for outputting information capable of specifying the stop of the identification information as the command when the variable display of the identification information is ended,
The command is composed of 2-byte command data,
The game control microcomputer executes command output processing for outputting command data and a capture signal designating capture of command data to the payout control microcomputer and the light emitter control microcomputer, In the command output process, the command data and the capture signal for the payout control microcomputer and the light emitter control microcomputer are output by calling the same subroutine,
The game control microcomputer outputs command data of the first byte in the command and outputs a capture signal, and then outputs command data of the second byte after a predetermined period of time elapses,
The game control microcomputer uses the predetermined period as a value equal to or greater than a maximum period of periods required for each of the payout control microcomputer and the light emitter control microcomputer to receive command data. A gaming machine characterized by outputting data. The predetermined period is longer claim 1 or claim 2 gaming machine according than the period from when the output command data to the output of the accepting signal. The electrical component control microcomputer executes predetermined periodic interrupt processing for performing electrical component control processing in accordance with an interrupt generated at a predetermined cycle, and is based on an input of a capture signal from the game control microcomputer. The command reception process for receiving a command output from the gaming control microcomputer according to an interrupt is executed, and the command reception process is executed with priority over the periodic interrupt process. The gaming machine according to any one of the three .

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