JP2000126426A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a player to play on a game machine always fair without generating inconstitency between a game control means and various control means and a game parlor to especially prevent a morning set, or the like. SOLUTION: CPU 56 acts according to a game control program in which a routine to periodically output one pulse at a low level from a bit in an output port 579 is included. When a pulse from the output port 579 is interrupted, a timer circuit 691 comes to time-up and a low level pulse is generated from a one shot pulse generating circuit 692 to reset CPU 56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in response to a player's operation. The present invention relates to a gaming machine capable of shifting to a gaming state.

[0002]

2. Description of the Related Art As a gaming machine, a variable display device having a variable display portion whose display state can be changed is provided, and when a display result of the variable display portion becomes a predetermined specific display mode, the player is provided with a variable display device. Some are configured to shift to an advantageous specific game state. The variable display device includes a plurality of variable display units, and is generally configured to display the display results of the plurality of variable display units at different times.

On the variable display section, for example, a plurality of identification information such as symbols are variably displayed. The fact that the display result of the variable display unit is a combination of predetermined specific display modes is usually referred to as “big hit”. In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] In addition, among the combinations of the display modes of "outside" other than the combination of "big hit", at the stage where a part of the display results of the plurality of variable display portions has not been derived and displayed yet, the display results are already displayed. The state in which the display mode of the variable display unit that is derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. A player plays a game while enjoying how to generate a big hit.

[0005] When a big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state as a specific game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 15 rounds). The opening time (for example, 29.5) for each opening
Seconds) is determined, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning port is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

In such a gaming machine, the progress of the game is controlled by game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means. The identification information, the character image, and the background image displayed on the variable display device generally include a display control microcomputer and a video display processor (FIG. 1) that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side. VDP), and the display control microcomputer has a large program capacity.

Therefore, the microcomputer of the game control means having a limited program capacity cannot be used also as the microprocessor for controlling the identification information and the like displayed on the variable display device. Another display control microcomputer (display control means) is mounted on a display control board different from the main board on which the game control means is mounted. Therefore, the game control means for controlling the progress of the game needs to transmit a command for display control to the display control board. The generation of image data such as identification information is performed by the display control means.

Further, in order to facilitate the inspection and the like, the game control means may be configured to transmit a control command to the display control board only when the display is switched, for example.
In such a configuration, the number of control commands transferred between the main board on which the game control means is mounted and the display control board is reduced, so that the inspection can be completed in a short time and the display control means can control the game. Since the display position of the identification information is controlled based on the command, the load on the game control means is reduced.

In a gaming machine, a luminous body such as a lamp and an LED is provided on a game board, and these luminous bodies are turned on and off as the game progresses in order to enhance the gaming effect. Regarding the control of the luminous body, the luminous body control means is mounted only at the time of switching the display for the purpose of reducing the load on the game control means and making the luminous body control part common to each model. May be configured to send control commands to the illuminant control board. Then, such a luminous body control means stores each luminous pattern according to the progress of the game, selects a corresponding pattern according to the control command, and controls the display of the lamp and the LED.

[0010]

As described above, when the display control board other than the main board, the illuminant control board, and the control means mounted on other boards have relatively high functions, the game control means is provided. There is a possibility that a control state mismatch occurs between the control state and the other control means. Since each control means is configured to be reset when the power is turned on, if the power of the gaming machine is cut off for a relatively long time, the game control means and other control means are reset when the power is restored and the control state is reset. Although no inconsistency occurs, a problem arises when an instantaneous power failure occurs such that the game control means is not reset but other control means are reset. For example, if such a momentary power failure occurs when the gaming state is a probability fluctuation state that is advantageous to the player, the display control means and the illuminant control means are reset and the display state of the gaming machine is initialized. In spite of this, the game state managed by the game control means is inconsistent with the state such as the probability fluctuation state. Then, in a game store, such a situation is intentionally caused,
A so-called morning set may be performed.

The present invention has been made to solve such a problem, and has a display control board other than the main board.
In a gaming machine having a configuration in which various control means are mounted on a luminous body control board or another board, a fair game can always be performed without causing a control state mismatch between the game control means and the various control means. In particular, it is an object of the present invention to provide a gaming machine capable of preventing a morning set or the like in a game arcade.

[0012]

A gaming machine according to the present invention comprises:
When a predetermined condition is satisfied, a special game is performed, and based on the result of the special game being in a predetermined mode, a game machine capable of shifting to a specific game state which is advantageous to a player, which is generated periodically. A game control microcomputer that controls the game by interruption executes the game control routine and returns to the main routine after the execution of the game control routine, and has control means for controlling the game machine components. The game control microcomputer sends a control command to another board at the state change point of the game machine component, monitors a signal periodically output from the game control microcomputer, and when the signal is no longer input, the game control microcomputer. Monitoring means for providing a reset signal to the computer is provided.

When a predetermined condition is satisfied, the gaming machine extracts a specific game random value, and when the extracted specific game random value matches the specific game determination value, the game machine can shift to a specific game state which is advantageous to the player. The game control routine started by the interruption may include a process of updating at least a numerical value for generating a specific game random number.

The gaming machine may be configured so that the main routine includes a process of repeatedly updating at least a numerical value for determining a mode of a special game.

Signal communication between the main board on which the game control microcomputer is mounted and another board may be configured to be one-way communication from the main board to another board.

The main board may include an output buffer for outputting the control command, and the other board for receiving the control command may include an input buffer circuit for receiving the control command.

The other board that receives the control command is, for example, a display control board on which means for controlling the display of the variable display unit whose display state can be changed is mounted.

Another board that receives the control command is, for example, a luminous body control board provided with a means for controlling lighting / extinguishing of the luminous body provided in the game machine.

[0019]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine.

As shown in FIG. 1, the pachinko gaming machine 1 comprises:
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, there is provided a variable display device 8 including a variable display section 9 using a CRT for variably displaying a plurality of types of symbols and a variable display 10 using 7-segment LEDs. I have. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. Passage gate 11
Is passed through the ball exit 13 to the starting winning opening 14. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. The winning ball that has entered the starting winning port 14 is guided to the back of the game board 6, and the starting port switch 1
7. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A game effect LED 28a and a game effect lamp 2
8b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is ready for use. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a link stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passing gate 11, if the change of the symbol can be started, the display number of the variable display 10 that normally displays the symbol variably changes. . If it is not in a state where the fluctuation of the symbol can be normally started, the gate passage memory is increased by one. When the hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the special symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start the change of the special symbol, the starting winning memory is increased by one. The start winning memory will be described later in detail.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, the mechanism plate 36 includes a hitting ball firing device 34 for shooting a hitting ball into the game area 7 using the rotational force of a motor, a game effect lamp / LED 28
a, 28b, and 28c, a prize ball lamp 51, and a lamp control board 35 for sending signals to the ball out lamp 52.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. On the back of the game board 6, FIG.
As shown in the figure, the winning ball set cover 4 for guiding the winning ball winning each winning port and the winning ball device along a predetermined winning path.
0 is provided. Of the prize balls guided to the prize ball collection cover 40, those that have won through the open / close plate 20 pay out a relatively large number of prize balls (for example, 15) with a ball payout device (not shown in FIG. 3). Is controlled as follows. The winnings through the start winning opening 14 are controlled so that the ball payout device pays out a relatively small number of prize balls (for example, 6). Then, the winnings through the other winning ports 24 and the winning ball device are controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10). Note that FIG. 3 illustrates the relay board 33 as an example.

Signals from the winning ball detection switch 99, the starting port switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the winning ball payout control. The winning is detected by the winning ball detection switch 99,
When an ON signal of the winning ball detection switch 99 is sent to the main board 31, a winning ball control command is sent from the main board 31 to the winning ball control board 37. For example, when the winning ball detection switch 99 is turned on in response to the turning on of the starting port switch 17, a winning ball control command indicating the number of winning balls “6” is output, and the count switch 23 or the V count switch 22 is turned on. When the winning ball detection switch 99 is turned on, a winning ball control command indicating the number of winning balls “15” is output. When the winning ball detection switch 99 is turned on when these switches are not turned on, a winning ball control command indicating the number of winning balls "10" is output.

FIG. 4 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 4 also shows the prize ball control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12,
A switch circuit 58 that supplies signals from the starting port switch 17, the V count switch 22, the count switch 23, and the winning ball detection switch 99 to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball device 15, and the opening and closing plate 2.
A solenoid circuit 59 for driving the solenoid 21 for opening and closing the 0 according to a command from the basic circuit 53;
It includes a lamp / LED circuit 60 for driving the variable display 10 by ED and the decorative lamp 25.

According to the data supplied from the basic circuit 53, jackpot information indicating occurrence of a jackpot, effective start information indicating the number of start winning balls used to start displaying an image on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. The ROM 54 and the RAM 55 may be built in the CPU 56 in some cases.

Further, when the power is turned on, the main board 31
Initial reset circuit 65 for resetting PU 56
And a watchdog circuit 69 that supplies a reset signal to the CPU 56 when a predetermined condition is satisfied, decodes an address signal supplied from the basic circuit 53, and selects one of the I / O ports in the I / O port unit 57. And an address decode circuit 67 for outputting a signal for performing the operation. In addition, there is also switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 is a block diagram showing an example of the configuration of the watchdog circuit 69 together with its peripheral elements. When the voltage of the power supply terminal (Vcc terminal) falls below a predetermined value, the initial reset circuit 65 used in this embodiment sets the reset signal (initial reset signal) to a low level which is a reset level for a predetermined period. Note that the predetermined value is determined by the level of the VS terminal. In this example, a resistor R1 is connected between the VS terminal and the + 5V power supply, a capacitor C1 is connected between the VS terminal and the ground, and a predetermined value for outputting a reset signal is set.

The CPU 56 operates according to the game control program, and includes a routine for periodically outputting one low-level pulse from a certain bit in the output port 579 during the game control program. Hereinafter, that bit of the output port 579 is referred to as a pulse output port. In this embodiment, the watchdog circuit 69 sets the output to a high level when the counter counts up and reaches a predetermined value, that is, when the time is up, the timer circuit 69.
1 and the output of the timer circuit 691 goes high,
A one-shot pulse generation circuit 692 for generating a low-level pulse of a predetermined length.

The pulse from the pulse output port is input to the timer circuit 691 as a reset signal. When the reset signal is input, the count value of the timer circuit 691 is returned to the initial value. Therefore, if a pulse is periodically output from the pulse output port at a period shorter than the time until the timer circuit 691 times out, the one-shot pulse generation circuit 692 does not generate a low-level pulse. However, when the pulse from the pulse output port is interrupted, the timer circuit 691 times out, and as a result, a one-shot pulse generation circuit 692 generates a low-level pulse. The timer circuit 691 is initialized by an initialization process executed by the CPU 56.

The output of one shot pulse generating circuit 692 is input to AND circuit 693. The AND circuit 693 also receives an initial reset signal from the initial reset circuit 65. The AND circuit 693 changes its output to a low level if any one of the inputs is at a low level. And AN
The output of the D circuit 693 is connected to the reset terminal of the CPU 56. Therefore, when the initial reset signal is generated and when the one-shot pulse generation circuit 692 generates a low-level pulse, the CPU 56 is reset.

FIG. 6 shows the circuit configuration in the display control board 80 by changing the CRT 82 for realizing the variable display section 9 and the main board 3.
1 is a block diagram shown together with a part of FIG. Display control C
The PU 101 operates according to the program stored in the control data ROM 102, and receives a display control command data via the input buffer 105 when a strobe signal is input from the main board 31 via the input buffer circuit 105. In the main board 31, the strobe signal is output from the output port 572 (output port B) and the output buffer circuit 6
3 and the display control command data is output to the output port 571 (output port A) and the output buffer circuit 6.
3 is output.

The display control CPU 101 controls display of a screen displayed on the CRT 82 in accordance with the received display control command data. Specifically, a command corresponding to the display control command data is given to the VDP 103.
The VDP 103 reads necessary data from the character ROM 86. Then, the VDP 103 generates image data to be displayed on the CRT 82 according to the input data, and stores the image data in the VRAM 87. Then, the image data in the VRAM 87 is converted into R, G, B signals, converted into analog signals by the DA converter 104, and output to the CRT 82.

FIG. 6 also shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, and a character ROM 86 for storing frequently used image data. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82.

As the input buffer circuit 105, for example,
74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the display control board 80 side to the main board 31 side.
That is, even if a modification is made in the display control board 80 to give an illegal signal to cause a big hit to the basic circuit 53 of the main board 31, the signal output by the illegal modification is transmitted to the main board 31 side. There is no. Further, in the main board 31, an output buffer circuit 63 for passing a signal only in a direction from the main board 31 to the display control board 80.
Is provided. As the output buffer circuit 63, for example, 74HC244 which is a general-purpose CMOS-IC is used. The enable terminal is always given a low level (GND level). Therefore, even if an illegal signal is to be added from the cable between the main board 31 and the display control board 80, the illegal signal will not be transmitted to the CPU 56 side.

FIG. 7 is a block diagram showing a signal transmitting / receiving portion of the main board 31 and the lamp control board 35.
In this embodiment, a game effect LED 28a and a game effect lamp 28b provided outside the game area 7 are provided.
A lamp control command indicating ON / OFF of 28c and ON / OFF of the award ball lamp 51 and the ball out lamp 52 is output.

As shown in FIG. 7, a lamp control command relating to lamp control is output from an output port (output port C) 573 of the I / O port unit 57 in the basic circuit 53. In the lamp control board 35, a control command from the main board 31 is input to the lamp control CPU 351 via the input buffer circuit 355. If the lamp control CPU 351 does not include an I / O port, the input buffer circuit 355 and the lamp control CPU 35
1, an I / O port is provided. Output port 5
Bit 7 of the data output from 73 is an INT signal. Lamp control CPU 351 takes in lamp control command data (bit 0 to bit 6) when the bit is turned on.

On the lamp control board 35, the CPU 351 for lamp control includes a game effect LED 28a and a game effect lamp 28 defined according to each control command.
b, 28c, the game effect L
A light-on / light-off signal is output to the ED 28a and the game effect lamps 28b and 28c. The light-on / light-off signal is output from the game effect LED 28a and the game effect lamps 28b and 28c.
Is output to The light-on / light-off pattern is stored in a built-in ROM or an external ROM of the lamp control CPU 351.

On the main board 31, the basic circuit 53 outputs a control command for instructing lighting of a prize ball lamp at the time of a prize ball, and when a ball-out detection sensor installed on a game ball supply path on the back of the game board is turned on, the ball is output. A control command for instructing to turn off the lamp is output. On the lamp control board 35,
Each control command is input to the lamp control CPU 351 via the input buffer circuit 355. Lamp control CP
U351 turns on / off the prize ball lamp 51 and the ball out lamp 52 in response to the control commands.

As the input buffer circuit 355, for example,
74HC244 which is a general-purpose CMOS-IC is used. A low level (GND level) is always applied to the enable terminal of the 74HC244. Therefore, the output level of each buffer is the input level, that is, the main board 31.
Signal level has been determined. Therefore, there is no room for a signal to be transmitted from the lamp control board 35 side to the main board 31 side. For example, even if a circuit in the lamp control board 35 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

Therefore, the main board 3 is moved from the lamp control board 35 to the main board 3.
It is possible to eliminate a signal line to which a signal may be given to the first signal line. That is, the unidirectionality of the signal from the main board 31 to the lamp control board 35 is ensured, and the possibility that the lamp control board 35 influences the game control on the main board 31 is eliminated. As a result, even if, for example, the lamp control board 35 is modified so as to give an illegal signal for causing a big hit to the basic circuit 53 of the main board 31, the illegal signal cannot be transmitted to the main board 31.

Further, on the main board 31, an output buffer circuit 62 is provided outside the output port 573. As the output buffer circuit 62, for example, a general-purpose CM
The OS-IC 74HC244 is used. The enable terminal is always given a low level (GND level). According to such a configuration, the main board 3 is externally provided.
Since a signal input to the inside of the first substrate 1 is blocked, a signal line to which a signal may be given from the lamp control board 35 to the main board 31 can be more reliably eliminated.

In FIG. 7, the lamp control CPU 35 is used.
Signals for instructing the game effect LED 28a, the game effect lamps 28b and 28c, the prize ball lamp 51 and the ball out lamp 52 to be turned on or off are output from the internal output port 1 in practice. -A driver circuit is inserted between the LED and the LED.

Next, the operation of the gaming machine will be described. FIG.
FIG. 9 is a flowchart showing the operation of the basic circuit 53 on the main board 31. FIG. 8 shows C of the basic circuit 53.
FIG. 9 shows a main process executed by the PU 56, and FIG. 9 shows an interrupt process. When the reset at the time of power-on of the CPU 56 is released, the CPU 56 first sets a clock monitor register incorporated in the CPU 56 to a clock monitor enable state in order to make the clock monitor control operable (step S1). Note that the clock monitor control is a control in which a reset is automatically generated inside the CPU 56 when a decrease or stop of an input clock signal is detected.

Next, the CPU 56 performs a stack setting process for setting the designated address of the stack pointer (step S2). In this example, 00FFH is set in the stack pointer. Then, a system check process is performed (step S3). In the system check process, the CPU 56 determines whether or not the RAM 55 contains an error.
Processing such as initializing 5 is performed. When power is turned on, RA
Since the content of M55 is undefined, the process of clearing the RAM 55 is eventually performed. Further, the CPU built-in timer is initialized so that the timer is interrupted periodically (for example, every 2 ms).
Of the timer circuit 691 is initialized.

Then, the display random number updating process is repeatedly executed (step S4). FIG. 10 is an explanatory diagram showing each random number used in the gaming machine. Each random number is used as follows. (1) Random 1: Determines whether or not to generate a big hit (for big hit determination) (2) Random 2-1 to 2-3: For left and right middle out-of-design symbol determination (3) Random 3: Design of big hit Determining a combination (for determining a big hit symbol = for determining a specific symbol) (4) Random 4: determining whether or not to reach at the time of a loss (for determining a reach) (5) Random 5: determining a reach type (determining a reach operation) for)

Incidentally, random numbers other than the above-mentioned random numbers (1) to (5) are also used to enhance the game effect. For example, a random number for determining whether or not to win based on the display result of the variable display 10 that normally displays symbols,
There is a random number or the like for determining the stop symbol of the variable display 10.

In the process of step S4, the random number for determining a lost symbol in (2), the random number for reach determination in (4),
The counter (5) for generating a random number for the reach operation and the big hit determination value is counted up (addition of 1). Therefore, in this embodiment, they are counters for generating display random numbers. However, random 2-2 is “0” when the carry of random 2-1 occurs, that is, the value of random 2-1 becomes “15”.
Counted up when returned to. Random 2-3 is obtained when a carry of random 2-2 occurs.
That is, the count is incremented when the value of the random 2-2 becomes “15” and is returned to “0”.

The process shown in FIG. 9 is started by a timer interrupt in the CPU 56. In the interrupt processing, C
The PU 56 first performs a watchdog process (Step S10). FIG. 11 is a flowchart illustrating an example of the watchdog process. In the watchdog process, the corresponding bit of the output port 579 is set to “0” so that the pulse output port of the output port 579 becomes low level (step S31). After a delay time of 30 μs (step S32), the output port 5
The corresponding bit of the output port 579 is set to “1” so that the 79 pulse output port becomes high level (step S
33).

Since the interrupt processing shown in FIG. 9 is periodically started by the internal timer interrupt of the CPU 56, the interrupt processing shown in FIG.
The watchdog process shown in FIG.
Therefore, as long as the CPU 56 operates normally, a low-level pulse of 30 μs is periodically output from the pulse output port of the output port 579. Note that the pulse width of 30 μs is merely an example.

Following the watchdog process, the CPU 56 performs a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S11). A process of outputting a control command is performed (display control data transmission process: step S12).

Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S13). In addition, a process for updating a timer for determining the timing of changing the lighting / extinguishing pattern of the lamp / LED provided around the game area 7 is performed (step S14). Further, an output data setting process of setting output data of a storage area for various output data and setting output data such as jackpot information, start information, and probability variation information output to the hall management computer in the storage area is performed ( Step S15). In addition, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S16).

Next, a process of updating each counter for generating each random number for determination, such as a random number for big hit determination used in game control, is performed (step S17). In this embodiment, among the counters for generating the random numbers shown in FIG. 10, the random number for jackpot determination of (1) and (3)
The counter for generating the big hit symbol determination random number is incremented (addition of 1).

Next, the CPU 56 performs a special symbol process (step S18). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S19). In normal symbol processing, 7 segments L
A corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 by the ED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 further includes a switch circuit 58
The state of the gate switch 12, the starting port switch 17 and the state of the count switch 23 are input through the CPU, and it is determined whether or not there is a winning in each winning opening or the winning device (switch processing: step S20). Further, control is performed to send a signal to the audio control board 70 so that a predetermined sound is emitted from the speaker 27 in accordance with the progress of the game (step S2).
1).

The CPU 56 performs a process of updating each counter for generating a display random number in the same manner as the process of step S4 (step S22). In particular,
Count up (1 addition) of a counter that generates a random number for determining a lost symbol in (2), a random number for reach determination in (4), a random number for reach operation in (5), and a random number for determining a jackpot determination value in (6) )I do.

The CPU 56 performs a winning ball signal process with the winning ball control board 37 (step S23). That is, when a predetermined condition is satisfied, a winning ball number signal is output to the winning ball control board 37. The prize ball control CPU mounted on the prize ball control board 37 drives the ball payout device 97 according to the prize ball number signal.

When the processing in steps S10 to S23 is completed, the interrupt processing ends, and the processing returns to the processing performed at the time of occurrence of the interrupt in the main processing. The process executed at the time of occurrence of the interrupt is the display random number updating process in step S4.

Next, a method of determining a symbol variably displayed on the variable display section 9 based on a winning in the starting winning opening 14 (starting winning) will be described with reference to flowcharts of FIGS. FIG. 12 shows a process for determining that the hit ball has won the starting winning opening 14, and FIG. 13 shows a process for determining a big hit. FIG. 14 is a flowchart showing a process for determining a symbol for stopping variable display on the variable display unit 9.

When the hit ball wins the starting winning port 14 provided in the game board 6, the starting port switch 17 is turned on.
In the switch processing of step S20 in the interrupt processing, the basic circuit 53 determines that the starting port switch 17 has been turned on via the switch circuit 58 (step S4).
1). When it is detected that the power is turned on, the CPU 56
Confirms whether or not the number of start winning memories has reached the start memory upper limit value of 4 (step S42). If the start winning storage number has not reached the start storage upper limit value, the starting winning storage number is increased by 1 (step S43), and the value of the random number for jackpot determination is extracted. Then, each start winning number n (n =
The extracted random numbers are stored in random number value storage areas provided corresponding to (1, 2, 3, 4) (step S44).
If the number of start winning memories has reached the start memory upper limit value, the processes of steps S43 and S44 are not performed.

When the CPU 56 is ready to start variable display on the variable display section 9, it performs the processing shown in the flowchart of FIG. First, the value of the number of memorized start winnings is confirmed (step S50). If the start winning prize memory number is not 0, the value stored in the random number storage area corresponding to the start prize storing number = 1 is read out (step S51), the value of the starting prize storing number is reduced by 1, and The value of the random number value storage area is shifted (step S52). In other words, the value stored in the random number value storage area corresponding to the number of start winning memory = n (n = 2, 3, 4) is calculated as follows:
1 is stored in the random number value storage area corresponding to 1.

Then, the CPU 56 determines a hit / miss based on the value read in step S51, that is, the extracted random number for big hit determination (step S53). In this embodiment, the random number for jackpot determination is 0.
A value in the range of ２４249 is assumed. And FIG.
As shown in (1), the value of the random number (random 1) for jackpot determination extracted at the time of starting winning is compared with the jackpot determination value.
If the value of random 1 matches the jackpot determination value,
It is determined to be a big hit, and if it is any other value, it is determined to be out.

When the combination of stopped symbols in the variable display section 9 is a combination of specific symbols, a big hit occurs and the state becomes high probability. In the state of high probability, the probability of the next big hit will increase,
The time required for the symbol to be determined after the variable display 10 starts variable display is shortened, and when the variable display 10 hits, the open state of the variable winning ball device 15 is set longer. That is, at the time of a high probability, the state becomes extremely advantageous for the player. At the time of low probability (normal time), the jackpot determination value is, for example, one, but at the time of high probability, there are a plurality of jackpot determination values, and the extracted random 1 value is one of the jackpot determination values. If they match, it is determined to be a big hit.

When it is determined that a big hit has occurred, the CPU 56
Determines the stop symbol based on the value of the big hit symbol determination random number (random 3). Here, when the limiter is operating, a stop symbol is determined from a table that does not include a probable variable symbol that causes a high probability state (step S5).
4, S56). The limiter is for restricting the occurrence of the jackpot due to the probable symbol continuously, that is, the continuation of the continuous high probability state. For example, if the high probability state continues four times in a row, the limiter is activated. Therefore, in the limiter operating state, the stop symbol is determined from the table that does not include the specific symbol in which the probability change is performed. If the limiter is not operating, a stop symbol is determined from a table including all symbols (steps S54 and S5).
5).

Further, the CPU 56 determines the reach type according to the value of the random number 5 (step S74), and sets whether or not to make a big hit, the symbol in the case of the big hit, and the reach type in a predetermined storage area (step S75). ). The storage area is provided in the RAM 55 of the basic circuit 53.

If it is determined in step S53 that there is a deviation, the CPU 56 determines whether or not to reach (step S59). For example, when the value of the reach determination random number shown in FIG. 10 is any one of 0 to 104, it is determined to reach. When it is decided to reach, the basic circuit decides a stop symbol. In this embodiment, the left and right symbols are determined according to the value of the random 2-1 (step S60). Also, random 2-2
The middle symbol is determined according to the value of (step S61). Here, if the determined middle symbol matches the left and right symbols, the symbol corresponding to the value obtained by adding 1 to the value of the random number corresponding to the middle symbol is determined as the middle symbol, so that it does not match the big hit symbol. I do.

Further, the CPU 56 determines a reach type according to the value of the random number 5 (step S62). Then, “reach”, reach symbol, and reach type are set in a predetermined storage area (step S63). If the lottery result in step S59 is out of place, it is set that it is out of place in the predetermined storage area (step S64).

FIG. 15 is a flowchart showing an example of a special symbol process processing program. The special symbol process process shown in FIG. 15 is a specific process of step S18 in the flowchart of FIG. When performing the special symbol process, the CPU 56 of the basic circuit 53 performs steps S300 to S300 shown in FIG.
309 is performed. In each process, the following processes are performed.

The special symbol change waiting process (step S30)
0): The starting winning switch 14 (in this embodiment, the winning opening of the variable winning ball device 15) is hit and the starting switch 17
Wait for to turn on. When it is detected that the start port switch 17 is turned on, the processing shown in FIG. 12 is performed. Special symbol determination processing (step S301): When a state in which the variable display of the special symbol can be started, the number of start winning prizes is confirmed. If the number of the memorized start winnings is not 0, it is determined whether to make a jackpot or a miss depending on the value of the random 1 already extracted. Stop symbol setting process (step S302): A stop symbol of the left and right middle symbols is determined according to the value of random 2 or random 3.

Reaching operation setting processing (step S30)
3): Whether or not to perform the reach operation is determined according to the value of the reach determination random number (random 4), and the variation mode of the reach operation is determined according to the value of the reach operation random number (random 5).

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. When a background or a character is also displayed on the variable display unit 9, control is performed so that display control command data corresponding to the background or character is transmitted to the display control board 80. All symbols stop waiting process (step S305): After a predetermined time has elapsed, control is performed so that all symbols displayed on the variable display section 9 are stopped. Further, the control is performed so that the left and right symbols are stopped at a predetermined timing until the timing of stopping all the symbols, and the display control command data corresponding to the background or the character displayed on the variable display unit 9 is appropriately displayed. Control to be sent to

Big hit display processing (step S306):
If the stop symbol is a combination of jackpot symbols,
The display control command data of the jackpot display is controlled to be sent to the display control board 80, and the internal state (process flag) is updated so as to shift to step S307. Otherwise, the internal state is changed to step S3.
Update to shift to 09. The combination of the big hit symbols is a combination in which the right and left middle symbols are aligned.
Further, the circuit of the game control board 80 displays a big hit on the variable display unit 9 according to the display control command data. The jackpot display is made to notify the player of the occurrence of the jackpot. Big winning opening opening process (step S307): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening.

Processing during opening of the special winning opening (step S30)
8): Control for transmitting display control command data of the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S307 unless the end condition of the big hit gaming state is satisfied. If the jackpot gaming state end condition is satisfied, the internal state is updated to shift to step S309.

Big hit end processing (step S309):
A display for notifying the player that the jackpot gaming state has ended is performed. When the display is completed, the internal flags and the like are returned to the initial state, and the internal state is updated so as to shift to step S300.

A module (display control data transmission processing: step S12) for performing processing of transmitting display control command data in the game control program in accordance with the processing of each of the above steps outputs the corresponding display control command data to the output port. And a strobe signal to an output port.

FIG. 16 shows the main board 31 to the display control board 8.
FIG. 9 is an explanatory diagram showing display control command data transmitted to 0. As shown in FIG. 16, in this embodiment, the display control command data is transmitted from the main board 31 to the display control board 80 through eight signal lines of display control signals CD0 to CD7. A display control signal IN for transmitting a strobe signal is provided between the main board 31 and the display control board 80.
T signal line, +5 V, +
A 12 V supply line and a signal line for supplying a ground level are also provided.

FIG. 17 shows the main board 31 to the game control board 8
FIG. 9 is a timing chart showing an example of transmission timing of display control command data given to 0. In this example, the 2-byte display control data constituting the display control command data is transmitted every 2 ms as shown in FIG. Then, a strobe signal (display control signal INT) is output in synchronization with each display control data. Display control CPU 10
1 is interrupted by IRQ2 at the rise of the strobe signal, so that the display control CPU 101 can fetch each display control data by the interrupt processing program.

In this embodiment, the display mode after the change is instructed from the main board 31 to the display control board 80 at the change point of the change speed of the pattern change and the display change point of the background and the character. Display control command data is 1
Sent only once. Therefore, the display control can be promptly started in the display control board 80, and the load related to the display control of the basic circuit 53 of the main board 31 is greatly reduced.

FIGS. 18 to 20 are explanatory diagrams showing examples of the structure of the display control command data. However, FIGS. 18 to 20 show a part of all the display control command data.

FIGS. 18 and 19 are explanatory diagrams showing display control command data for instructing the display of each of the right and left symbols, and display control command data for instructing the display position of the left and right symbols on the screen. is there. In this embodiment,
There are 15 left and right middle designs each. FIG. 18 shows display control command data for instructing display of a left symbol and a right symbol. Display control CPU 101
Receives the display control command data, and controls to display the designated left and right symbols regardless of the immediately preceding display symbol. FIG. 19 shows display control command data for instructing display of a medium symbol.
When receiving the display control command data, the display control CPU 101 controls to display the designated middle symbol regardless of the immediately preceding display symbol. The value of the display control data CMD1 in the first byte for the left symbol is
“84 (H)”, the value of the display control data CMD1 in the first byte for the right symbol is “85 (H)”,
The value of the display control data CMD1 in the first byte for the middle symbol is “86 (H)”.

FIG. 19 also shows display control command data indicating the display position of the left and right middle symbol on the screen.
When the display control CPU 101 receives the display control command data, the display control CPU 101 sets the display area of the middle left and right symbols on the display screen to a normal position (approximately the center in this embodiment) or a lower part of the screen. The value of the display control data CMD1 of the display control command data indicating the display position of the middle left and right symbols is “87 (H)”.

FIG. 20 is an explanatory diagram showing display control command data for instructing a character, background, and error display. When the value of the display control data CMD1 is “88”
(H) "indicates data relating to a character, and the value of the display control data CMD1 is" 89 ".
(H) "indicates data related to the background, and the value of the display control data CMD1 is" F8 ".
The display control command data of “(H)” indicates data related to error display.

FIG. 21 is a flowchart showing the operation of the display control CPU 101. Display control CPU 101
When the power is turned on, first, an initialization process including an initialization process of the VDP 103 and the RAM is performed (step D71). Then, a display update process is performed based on the display control command data received last (step S7).
2). That is, a process of updating the display state in order to change the design or the character is performed. When the data reception completion flag is turned on (step S73), the data reception completion flag is reset (step S74), and a display switching process is performed (step S75). The data reception completion flag is turned on when new display control command data is received. Therefore, when the data reception completion flag is turned on, the use data is switched to perform a display update process based on the new display control command data.

FIG. 22 is a flowchart showing the display control command data receiving process of the display control CPU 101. As described above, since the strobe signal from the main control board 31 is input to the IRQ2 interrupt terminal of the display control CPU 101, the display control command data is received by the IRQ2 interrupt processing. Each display control data from the main board 31 is input to an input port in the display control CPU 101.

In the IRQ2 interrupt processing, the display control C
The PU 101 first checks whether or not the data receiving flag is set (step S701). If not set, this interrupt is an interrupt caused by the transmission of the first byte of display control data in the display control command data. Therefore, the pointer is cleared (step S702), and the data receiving flag is set (step S703). The pointer indicates which byte in the display control command data storage area in the RAM built in the display control CPU 101 stores the received data.

When the data receiving flag is set, the display control CPU 101 inputs data from the input port and stores the input data at the address indicated by the pointer in the display control command data storage area. (Step S705).

Then, the display control CPU 101 increments the value of the pointer by one (step S706). Then, when the value of the pointer becomes 2, it means that the reception of the display control command data composed of 2 bytes has been completed, so that the data reception completion flag is set and the data reception flag is reset. (Step S708,
S709). With the above processing, the display control data CMD1 and CMD2 are received by the display control board 80.

FIG. 23 is an explanatory diagram showing an example of a lamp control command sent from the main board 31 to the lamp control board 35. Each lamp control command data is composed of 7 bits, and a lamp / LED according to the progress of the game, respectively.
Specify the lighting pattern and turn off. However, FIG.
Is an example of a pattern corresponding to a specific gaming machine. In other gaming machines, lamp control command data having different definitions can be used. For example, in the example shown in FIG.
To 08H), but in a gaming machine having more special fluctuation patterns, the special fluctuation patterns may be assigned to more types of lamp control command data. Alternatively, the lamp control data that may be used in all the gaming machines may be defined, and the lamp control data to be used in each model may be selected as needed.

It should be noted that the command configuration shown in FIG. 23 is characterized by a normal lamp designation, a changing lamp designation,
That is, the command of the lamp designation at the time of the special fluctuation, the announcement at the time of the big hit, and the designation of the ramp at the time of the decision are different from each other by “1” between the time of the high probability and the case of the other times. With such a command configuration, the load when the CPU 56 of the main board 31 creates the lamp control command data is reduced. For example, when creating the lamp control command data of the normal lamp designation, the fluctuation lamp designation, the special fluctuation lamp designation, the big hit announcement lamp designation, or the fixed lamp designation, first, "01H", "03H", "05H" , "07
H ”,“ 09H ”or“ 0BH ”, and then
It is determined whether or not a high probability is in progress. If the probability is high, the set value may be incremented by +1. Otherwise, the set value is used as it is as the lamp control command data. That is, creation of the high-probability lamp control command data for the normal lamp designation, the fluctuation lamp designation, the special fluctuation lamp designation, the big hit notice, and the fixed lamp designation is shared as a step of incrementing the set value by +1.

In this embodiment, the difference is "1", but the difference may be a predetermined value other than "1".
Even if the difference is a predetermined value other than “1”, if the probability is high, the lamp control command data is generated only by increasing the set value by + (the predetermined value). Further, in this embodiment, the high probability state is exemplified as the special game state, but the special game state may be a time saving state. In other words, the ramp control command data during the working hours may be different from the ramp control command data normally sent from the main board 31 by the predetermined value in the same game situation.

"00H" to "10H" are ramp control commands related to game control, and are "70H" to "7H".
"2H" is a ramp control command that is less important than control commands related to game control. Therefore, when the timing of issuing the ramp control command relating to the game control and the timing of issuing the lamp control command having a low importance are combined, the basic circuit 53 of the main board 31 issues the ramp control command relating to the game control. When the command issuance is completed, the lamp control commands of “70H” to “72H” are issued.

FIG. 24 is an explanatory diagram showing the bit configuration of the lamp control command. As shown in FIG. 24, six bytes of bit 0 to bit 6 in one byte are used as the ramp control command data portion shown in FIG. 23, and bit 7 is used for the INT signal.

FIG. 25 is a flowchart showing a lamp control command output portion of the data output process (step S13) in the main process in the basic circuit 53 of the main board 31 shown in FIG. In the data output process relating to the lamp control command output, the CPU 56 determines whether or not a port C output request has been set (step S621). The port C output request is set when the lamp data has been changed in the output data setting process (step S15).

If the port C output request has been set, the port C output request is reset (step S62).
2) Output the contents of the port C storage area to the output port (output port C) 573 (step S623). Lamp control command data is set in bits 0 to 6 of the port C storage area. As shown in FIG. 7, the output of the port C is connected to the lamp control board 35 via the output buffer circuit 62. Therefore, a new lamp control command is sent to the lamp control board 35.

FIG. 26 is a flowchart showing the processing of the lamp control CPU 351 in the lamp control board 35. The lamp control CPU 351 includes all lamps / L
After initializing an output port and a work area for turning off the ED and performing an initial process such as a timer setting (step S141), a loop state is entered. In the initial processing, a timer is set such that a timer interrupt occurs every 500 μs. Therefore, in the loop state, when a timer interrupt of 500 μs is applied, the lamp control is executed (step S142).

FIG. 27 is a flowchart showing the timer interrupt processing of 500 μs. When a timer interrupt occurs, the lamp control CPU 351 performs initial processing such as starting a timer so as to perform the next 500 μs interrupt (step S151), and then performs lamp data reception processing (step S152). Then, following the lamp data receiving process, a lamp / LED turning on / off process (step S153) based on the received lamp control command is executed.

When no new lamp control command is received, the lamp control CPU 351 repeatedly executes the lamp control according to the content of the last received lamp control command.

As described above, the CPU 56 of the main board 31 sends out the display control command at the display change point of the variable display section 9, and sends out the lamp control command at the lamp / LED display change point. Then, the display control board 80
The display control CPU 101 and the lamp control CPU 351 in the lamp control board 35 perform display control based on the control command received immediately before until a new control command is received.

As shown in the flow charts shown in FIGS. 21 and 26, when the power of the game machine is turned on and the reset is released, the display control CPU 101 and the lamp control CPU 351 execute the initialization processing. In the initialization processing, the display is initialized.
Then, not only at the time of normal power-on, but also at the moment of a momentary power failure, and then when the power is restored, the reset is performed and the initialization processing is executed. That is, the display states of the variable display section 9 and the lamp / LED are initialized.

At this time, it is sufficient that the CPU 56 of the main board 1 is similarly reset. However, there is a possibility that the CPU 56 is not reset due to a difference in electric load or the like. In this case, if no consideration is given, the contents of the RAM 55 in the basic circuit 53 of the main board 31 are not initialized, and the state of the internal flag continues.

In particular, in a state where the game state is advantageous to the player (for example, a probability fluctuation state), the display control CPU 101 and the lamp control CPU 351 are reset, and the CPU 56 in the basic circuit 53 of the main board 31 is reset.
This is a problem when the initialization process is not executed. This is because the gaming machine appears to be in the initial state at first glance when viewed from the outside, but internally it is in an advantageous state for the player. In addition, there is a possibility that an instantaneous power failure may occur artificially to cause such a state. Then, at the game store,
At the time of opening the store, there is a possibility that a morning set for attracting a player may be performed.

However, in this embodiment, the main substrate 3
Such a situation can be avoided by the watchdog circuit 69 provided in the device 1. FIG. 28 is a timing chart for explaining the operation of watchdog circuit 69. As shown in FIG. 28, when the CPU 56 is operating normally, a low-level pulse of 30 μs is periodically input to the reset terminal of the timer circuit 691 of the watchdog circuit 69. Therefore, the timer circuit 691
Is reset before the time-up, and repeats the process of restarting the count-up from the initial value.

When the power supply of the gaming machine momentarily stops and the +5 V power supply voltage drops, the potential of the low-level pulse of 30 μs becomes 0 V
Can not fall to Then, a low level sufficient to reset the timer circuit 691 is not input to the reset terminal of the timer circuit 691. Then, the timer circuit 69
The count-up of 1 progresses, and finally the time is up, and the output goes high. As a result, a low-level signal is output from the one-shot pulse output circuit 692,
The signal is supplied to the reset terminal of the CPU 56 via the AND circuit 693.

Therefore, the CPU 56 is reset,
After the reset is released, the CPU 56 can execute the processing of steps S1 to S3 shown in FIG. Since the RAM 55 is initialized by the processing in step S3, the gaming state in the basic circuit 53 of the main board 31 is initialized.

Here, in order to reliably detect a drop in the + 5V voltage due to a momentary power failure that resets the display control CPU 101 and the lamp control CPU 351,
Any circuit element may be connected to the reset terminal of the timer circuit 691. For example, the output (voltage) of the output port 579 may be divided and supplied to the reset terminal so that a momentary power failure can be detected earlier.

As described above, in this embodiment, the watchdog circuit 69 controls the display control CP.
Since it is configured to detect a momentary power failure such that the U101 or the lamp control CPU 351 is reset and to supply a reset signal to the CPU 56, the display control board 80 other than the main board 31, the lamp control board 35, or another In a gaming machine having a control means mounted on a board, the main board 3
A fair game can always be played without causing a control state mismatch between the first game control means and each control means.

In each of the above embodiments, the game control routine for controlling the game is executed by an internal timer interrupt of the CPU 56 which is periodically generated. However, a periodic reset circuit is provided outside the CPU 56. The present invention can be applied to any of the embodiments. In that case, the periodic reset circuit periodically (for example, every 2 ms) gives the CPU 56 a periodic reset signal different from the initial reset,
The CPU 56 executes a game control routine (for example, step S1 shown in FIGS. 8 and 9) by a periodic reset signal.
To S3, S10 to S23, and S4). In that case, steps S1 to S3
After the processes of S10 and S23 are performed, step S
Step 4 is repeated until the next periodic reset signal is generated. Then, when the next periodic reset signal is generated, the processing related to the initialization in steps S1 to S3 is performed, but the contents of the RAM are not initialized. In addition, CPU
Since the period 56 is periodically restarted by the periodical reset, the periodical reset signal is substantially an interrupt signal.

In each of the above embodiments, the variable display section 9 using a CRT for variably displaying a plurality of types of symbols is provided.
Has been described, but a variable display device using an LCD may be used, or the present invention can be applied to a video-type pachinko game machine in which the entire board surface is composed of video.

[0119]

As described above, according to the present invention, a game control microcomputer which controls a game machine with a periodically generated interrupt executes a game control routine, and executes a game control routine. And the game control microcomputer sends a control command to another board on which control means for controlling the gaming machine components are mounted at a state change point of the gaming machine components. And a monitoring means for monitoring a signal periodically output from the game control microcomputer and providing a reset signal to the game control microcomputer when the signal is no longer input. In a gaming machine in which various control means are mounted on a board, a luminous body control board or another board,
There is an effect that a fair game can always be played without causing a control state mismatch between the game control means and the various control means.

When a predetermined condition is satisfied, a specific game random value is extracted, and when the extracted specific game random value matches the specific game determination value, it is possible to shift to a specific game state that is advantageous to the player. If the game control routine that is started by including a process for updating at least a numerical value for generating a specific game random number value,
Since the numerical value for generating the specific game random number value is periodically updated, there is an effect that the probability of the specific game state does not deviate from a predetermined value.

If the main routine is configured to include at least a process of repeatedly updating a numerical value for determining a special game mode, the numerical value is appropriately varied, and the special game mode is randomly changed. There are effects that are determined.

When signal communication between the main board on which the game control microcomputer is mounted and another board is configured to be one-way communication from the main board to another board, the main board is There is an effect that it is possible to prevent a fraudulent act of sending a fraudulent signal to gain fraudulent profit.

If the main board includes an output buffer for outputting a control command and the other board for receiving the control command includes an input buffer circuit for receiving the control command, the illegal operation is prevented. This has the effect that it can be prevented more reliably.

When the other board receiving the control command is a display control board, the game control microcomputer only needs to send the control command at the display change point for the display control of the variable display section. This has the effect of reducing the load on the device.

When the other substrate for receiving the control command is a luminous body control board on which a means for controlling lighting / extinguishing of the luminous body is mounted, a lamp, an LED or the like provided in the gaming machine is provided. As for the control, the game control microcomputer only needs to send the control command at the display change point, so that the load on the game control microcomputer is reduced.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing an example of a circuit configuration in the game control board.

FIG. 5 is a block diagram showing a configuration example of a watchdog circuit together with peripheral elements.

FIG. 6 is a block diagram showing a circuit configuration in a display control board.

FIG. 7 is a block diagram showing a circuit configuration in the lamp control board.

FIG. 8 is a flowchart showing main processing of the basic circuit.

FIG. 9 is a flowchart showing an interrupt process of a basic circuit.

FIG. 10 is an explanatory diagram showing each random number.

FIG. 11 is a flowchart showing a watchdog process.

FIG. 12 is a flowchart illustrating a process of determining that a hit ball has won a start winning opening.

FIG. 13 is a flowchart showing a jackpot determination process.

FIG. 14 is a flowchart showing a process of determining a stop symbol for variable display.

FIG. 15 is a flowchart showing a special symbol process process.

FIG. 16 is an explanatory diagram showing display control command data.

FIG. 17 is a timing chart showing an example of transmission timing of display control command data.

FIG. 18 is an explanatory diagram illustrating a configuration example of display control command data.

FIG. 19 is an explanatory diagram showing a configuration example of display control command data.

FIG. 20 is an explanatory diagram illustrating a configuration example of display control command data.

FIG. 21 is a flowchart showing the operation of the display control CPU.

FIG. 22 is a flowchart showing an IRQ2 interrupt process of the display control CPU.

FIG. 23 is an explanatory diagram showing an example of a lamp control command.

FIG. 24 is an explanatory diagram showing a bit configuration of a lamp control command.

FIG. 25 is a flowchart showing a ramp control command output processing portion of the data output processing in the main processing.

FIG. 26 is a flowchart showing the operation of the lamp control CPU.

FIG. 27 is a flowchart showing a timer interrupt process of a lamp control CPU.

FIG. 28 is a timing chart for explaining the operation of the watchdog circuit.

[Explanation of symbols]

 9 Variable display unit 31 Game control board (main board) 35 Lamp control board 53 Basic circuit 56 CPU 62 Output buffer circuit 63 Output buffer circuit 69 Watchdog circuit 80 Display control board 101 Display control CPU 105 Input buffer circuit 351 For lamp control CPU 355 input buffer circuit

Claims (7)

[Claims] 1. A gaming machine capable of performing a special game when a predetermined condition is satisfied, and shifting to a specific game state which is advantageous to a player based on a result of the special game being in a predetermined mode, A game control microcomputer which controls a game with a periodically generated interrupt executes a game control routine, and controls a game machine component in a game machine configured to return to a main routine after executing the game control routine. The game control microcomputer sends a control command to the other board on which the control means is mounted at a state change point of the game machine component, monitors a signal periodically output from the game control microcomputer, and A gaming machine comprising monitoring means for giving a reset signal to the game control microcomputer when a signal is no longer input. . 2. A game machine capable of extracting a specific game random number value when a predetermined condition is satisfied, and shifting to a specific game state that is advantageous to a player when the extracted specific game random value matches a specific game determination value. The gaming machine according to claim 1, wherein the game control routine started by interruption includes a process of updating at least a numerical value for generating the specific game random number value. 3. The gaming machine according to claim 1, wherein the main routine includes a process of repeatedly updating at least a numerical value for determining a mode of a special game. 4. A signal communication between a main board on which a game control microcomputer is mounted and another board is one-way communication from the main board to another board.
The gaming machine described. 5. The gaming machine according to claim 4, wherein the main board includes an output buffer for outputting a control command, and the other board receiving the control command includes an input buffer circuit for receiving the control command. 6. The display control board according to claim 1, wherein the other board receiving the control command is a display control board on which means for controlling display of a variable display unit whose display state can be changed is mounted.
The gaming machine described. 7. The illuminant control board on which the means for receiving the control command is provided with means for controlling the lighting / extinguishing of the illuminant provided in the gaming machine. Gaming machine.