JP2000140350A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a control command to be more securely transmitted from a main board to another board mounted with a control means to enable a fair game to be played by constituting the Pachinko machine to be equipped with a noise filter circuit on a control command receiving part and a circuit element with hysteresis properties on the output side of the noise filter circuit. SOLUTION: A noise filter circuit 106 by EMI filter is equipped on a display control command inputting part in a display control board 80. A circuit with hysteresis in input threshold voltage, for instance, an input buffer circuit 108 by 74HC14 is equipped on the output side of the noise filter circuit 106. Accordingly noise between boards is effectively eliminated by the noise filter circuit 106 and wave rounding by the filter is formed by an input buffer circuit 105. Consequently display control command data with a fine waveform without noise and INT signals are inputted into the display control CPU 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine or a coin game machine in which a game is played in response to a player's operation. The present invention relates to a gaming machine capable of shifting to a gaming state.

[0002]

2. Description of the Related Art As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a winning area such as a winning opening provided in the game area, a predetermined number of prize balls are obtained. Are paid out to players.
Furthermore, a variable display unit capable of changing the display state is provided,
There is a configuration in which a predetermined game value is provided to a player when a display result of the variable display unit has a predetermined specific display mode.

[0003] When the display result of the variable display section for displaying a special symbol is a combination of a predetermined specific display mode, it is usually called a "big hit". In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0004] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state where a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. If the predetermined condition (for example, winning in the V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit gaming state ends.

[0005] In addition, among the combinations of display modes other than the "big hit" combination, at a stage where some of the display results of the plurality of variable display portions have not been derived and displayed yet, the display results have already been derived and displayed. A state in which the display mode of the variable display unit that satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. If the display result of the identification information variably displayed on the variable display unit does not satisfy the condition of “reach”, the result is “out” and the variable display state ends. A player plays a game while enjoying how to generate a big hit.

The progress of the game in the gaming machine is controlled by game control means such as a microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means.
The identification information, the character image, and the background image displayed on the variable display device generally include a display control microcomputer and a video display processor (FIG. 1) that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side. VDP), and the display control microcomputer has a large program capacity.

Therefore, the microcomputer of the game control means having a limited program capacity cannot be used also as the microprocessor for controlling the identification information and the like displayed on the variable display device. Another display control microcomputer (display control means) is used. Therefore, the game control means for controlling the progress of the game needs to transmit a command for display control to the display control means. The generation of image data such as identification information is performed by the display control means.

When it is detected that a prize has been won in the prize area, a predetermined number of game media for each prize area are paid out to the player as prize balls. Since the payout of the game media is performed by the payout mechanism, the number of prize balls according to the winning is instructed from the main means of the gaming machine to the payout mechanism. The payout mechanism pays out the number of game media according to the instruction. The payout mechanism is generally controlled by prize ball control means mounted on a prize ball control board. Since the progress of the game is controlled by the game control means mounted on the main board, the number of prize balls based on the winning is determined by the game control means and transmitted to the prize ball control board.

Further, in order to enhance the game effect, a speaker is provided on the game board of the gaming machine, and various sound effects are emitted from the speaker as the game progresses. Further, a light emitting body such as a lamp or an LED is provided on the game board, and these light emitting bodies are turned on or off as the game progresses in order to enhance the game effect. In this case, in order to perform voice control and lighting / extinguishing control of lamps / LEDs, a voice control board equipped with voice control means is provided separately from the game control means, or a light emitter control board equipped with light emitter control means. May be provided separately from the game control means, and a control command may be sent from the game control means to the voice control means and the illuminant control means in accordance with the progress of the game.

[0010]

When the display control means, the prize ball control means and the other control means are mounted on a board different from the board on which the game control means is mounted, the control command is transmitted to the board. There is a possibility that noise and the like may change between them. If a control command changes between boards due to noise or the like, identification information different from the identification information that should be displayed, or something different from the background or character that should be displayed, is displayed. Or Since the identification information and the like are originally displayed in accordance with the progress of the game, if the display is not performed as specified, it will not be consistent with the progress of the game, giving a player distrust or playing the game. It may be disadvantageous to people.
Further, when the prize ball control command indicating the number of prize balls changes between the substrates due to noise or the like, a different number of prize balls are paid out than the number of prize balls that should be paid out to the player. As a result, it is conceivable that a disadvantage is given to the game store or the player. Furthermore, if other control commands such as voice commands change between boards due to noise or the like, an effect different from the original game effect is performed, and the game effect is reduced.

An object of the present invention is to provide a gaming machine capable of transmitting a control command from a game control means to a board on which each control means is mounted more reliably.

[0012]

A gaming machine according to the present invention comprises:
Perform special games by winning game media in the special prize section,
A main board having a game control means for controlling the progress of the game, the main board being a game machine capable of shifting to a specific game state which is advantageous to the player based on the result of the special game being in a predetermined mode; Another board having control means for controlling the gaming machine components in response to a control command from the control means, the other board having a noise filter circuit in a control command receiving section, and further comprising a noise filter circuit Is characterized by having a circuit element having a hysteresis characteristic on the output side of.

[0013] The game control means may be configured to transmit a control command to another board only once at a control change point.

Preferably, the gaming machine is configured so that control commands can be transmitted only in a direction from the main board to another board.

[0015] The game control means may be configured to output a control command via an irreversible transmission means capable of transmitting a signal in only one direction.

The gaming machine has a display device, and the other substrate is, for example, a substrate on which display control means for controlling a display state of the display device is mounted.

The gaming machine has prize ball payout means for paying out a prize ball to a player, and the other substrate is, for example, a board on which a prize ball control means for controlling the prize ball payout means is mounted.

The control means mounted on another board fetches the control command in a cycle shorter than the validity period of the control command from the game control means. It may be configured to perform control based on the control command upon receiving the control command.

On the other hand, when the control means mounted on another board detects an error in the control command, the control means takes in the control command in a cycle shorter than the validity period of the control command from the game control means from that time. It may be configured to start.

[0020]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing prize balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section 9 for variably displaying a plurality of types of symbols and a 7-segment L
A variable display device 8 including a variable display 10 using an ED is provided. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

An opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state) is provided below the variable winning ball apparatus 15. In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The game board 6 is provided with a plurality of winning ports 19 and 24. Decorative lamps 25 are provided around the left and right sides of the game area 7 so as to blink during the game.
There is an out port 26 for absorbing a hit ball that does not win. In addition, two speakers 27 that emit sound effects are provided at upper left and right sides outside the game area 7. A game effect LED 28a and a game effect lamp 2
8b and 28c are provided.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a prize ball is paid out, and a ball out lamp 52 which is lit when a supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card can be used. If there is a fraction (less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a link stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided for releasing the card unit 50 when checking the mechanism of the writer.

The hit ball fired from the hitting ball launching device enters the game area 7 through the hitting rail, and thereafter, the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passage gate 11, the display number of the variable display 10 is changed continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, the symbol in the variable display section 9 starts rotating if the symbol can be changed. If it is not possible to start changing the symbol, the start winning memory is increased by one. The start winning memory will be described later in detail. The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening and closing plate 20
Is released until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit becomes high. That is, a high probability state, which is more advantageous for the player, is obtained. Also, when the stop symbol on the variable display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the variable display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back of the variable display device 8, as shown in FIG. 2, a prize ball tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, a prize ball is provided from above. Premium ball tank 3
8 is supplied. The prize ball in the prize ball tank 38 reaches the ball payout device through the guide gutter 39.

On the mechanism board 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball control board on which a prize ball control microcomputer for controlling the payout of prize balls is mounted. 37 are installed. Further, the mechanism plate 36 includes a hitting ball firing device 34 for shooting a hitting ball into the game area 7 using the rotational force of a motor, a game effect lamp / LED 28
a, 28b, and 28c, a prize ball lamp 51, and a lamp control board 35 for sending signals to the ball out lamp 52.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. On the back of the game board 6, FIG.
As shown in the figure, the winning ball set cover 4 for guiding the winning ball winning each winning port and the winning ball device along a predetermined winning path.
0 is provided. Of the prize balls guided to the prize ball collection cover 40, those that have won through the open / close plate 20 pay out a relatively large number of prize balls (for example, 15) with a ball payout device (not shown in FIG. 3). Is controlled as follows. The winnings through the start winning opening 14 are controlled so that the ball payout device pays out a relatively small number of prize balls (for example, 6). Then, the winnings through the other winning ports 24 and the winning ball device are controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10). Note that FIG. 3 illustrates the relay board 33 as an example.

Signals from the winning ball detection switch 99, the starting port switch 17 and the V count switch 22 are sent to the main board 31 in order to perform the winning ball payout control. The winning is detected by the winning ball detection switch 99,
When an ON signal of the winning ball detection switch 99 is sent to the main board 31, a winning ball control command is sent from the main board 31 to the winning ball control board 37. For example, when the winning ball detection switch 99 is turned on in response to the turning on of the starting port switch 17, a winning ball control command indicating the number of winning balls “6” is output, and the count switch 23 or the V count switch 22 is turned on. When the winning ball detection switch 99 is turned on, a winning ball control command indicating the number of winning balls “15” is output. When the winning ball detection switch 99 is turned on when these switches are not turned on, a winning ball control command indicating the number of winning balls "10" is output.

FIG. 4 is a block diagram showing an example of the circuit configuration of the main board 31. FIG. 4 also shows the prize ball board 37, the lamp control board 35, the audio control board 70, the launch control board 91, and the display control board 80. On the main board 31, a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, and signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, and the winning ball detection switch 99 are transmitted to the basic circuit 53. , A solenoid circuit 59 for driving a solenoid 16 for opening and closing the variable winning ball device 15 and a solenoid 21 for opening and closing the open / close plate 20 in accordance with a command from the basic circuit 53, and a start storage display 18
And a lamp / LED circuit 60 for driving the variable indicator 10 and the decorative lamp 25 by a 7-segment LED.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start variable display of the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 used as a work memory, a CPU 56 for performing a control operation in accordance with the control program, and an I / O port unit 57. The ROM 54 and the RAM 55 may be built in the CPU 56 in some cases.

Further, the main board 31 has an initial reset circuit 65 for resetting the basic circuit 53 when the power is turned on.
A periodic reset circuit 66 for periodically (eg, every 2 ms) giving a reset pulse to the basic circuit 53 to re-execute the game control program from the beginning, and decode an address signal given from the basic circuit 53. I
Address decode circuit 67 for outputting a signal for selecting any I / O port in I / O port unit 57
Are provided. In addition, there is also switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

FIG. 5 shows a circuit configuration in the display control board 80 by using a CRT 82 for realizing the variable display section 9 and the main board 3.
FIG. 5 is a block diagram showing the output ports 571 and 572 of FIG. The display control CPU 101 includes a control data ROM
It operates according to the program stored in 102 and receives display control command data when an INT signal is input from the main board 31. Then, display control of a screen displayed on the CRT 82 is performed according to the received display control command data. Specifically, a command corresponding to the display control command data is given to the VDP 103. The VDP 103 reads necessary data from the character ROM 86. And
The VDP 103 generates image data to be displayed on the CRT 82 according to the input data, and stores the image data in the VRAM 87. Then, the image data in the VRAM 87 is converted into R, G, B signals, converted into analog signals by the DA converter 104, and output to the CRT 82.

FIG. 5 shows a reset circuit 83 for resetting the VDP 103, an oscillation circuit 85 for supplying an operation clock to the VDP 103, a character ROM 86 for storing frequently used image data, and display control command data. An input buffer circuit 105 for input is also shown. The frequently used image data stored in the character ROM 86 is, for example, a person, an animal, or an image composed of characters, graphics, or symbols displayed on the CRT 82.

In this embodiment, a noise filter circuit 106 using an EMI filter is provided at the input section of the display control command on the display control board 80. The noise filter circuit 106 includes an EMI filter corresponding to each bit of the display control command data and each line of the INT signal. Therefore, noise on the display control command data between the main board 31 and the display control board 80 is canceled by the noise filter circuit 106. As a result, inconveniences such as display of identification information different from the identification information to be displayed or display of a different background or character from the originally appearing character can be prevented. Therefore, even if the display control command includes noise between the boards, the display is performed as determined, and the game effect does not become strange or the player does not feel suspicious.

However, since the EMI filter includes a capacitance component, the waveform of the display control command data that has passed through the noise filter circuit 106 may be rounded. The display control CPU 101 receives display control command data in synchronization with the INT signal. However, if the waveform of the display control command data becomes blunt, erroneous data may be taken. As will be described later, in this embodiment, the possibility of receiving incorrect display control command data that has been subjected to noise suppression even by software processing is further reduced, but it is assumed that the software has received regular display control command data. The determined timing may be delayed.

Therefore, on the output side of the noise filter circuit 106, an input buffer circuit 105 of, for example, 74HC14 having hysteresis in the input threshold voltage is provided. Input buffer circuit 1 with hysteresis
Reference numeral 05 indicates that even if the input waveform gradually rises and falls, the rising and falling of the output waveform can be sharpened. That is, the waveform of the display control command input to the display control CPU 101 does not become dull.

As described above, in this embodiment, the noise between the substrates is effectively removed by the noise filter circuit 106, and the waveform rounding due to the filter is shaped by the input buffer circuit 105. Therefore, the display control command data and the INT signal having a clear waveform including no noise are input to the display control CPU 101.

Each element in the input buffer circuit 105 can pass a signal only in the direction from the main substrate 31 to the display control substrate 80. Therefore, there is no room for a signal to be transmitted from the display control board 80 side to the main board 31 side. Therefore, even if the circuit in the display control board 80 is tampered with, the signal output by the tampering is not transmitted to the main board 31 side.

Further, the main board 31, which is the signal output side, has an output port 57 for outputting display control command data.
Output buffer circuits 611 and 612 that allow signals to pass in only one direction are provided on the output side of an output port 572 that outputs 1 and INT signals. Therefore, the main substrate 3
1, there is no room for a signal to enter from outside, and there is no room for an illegal start winning signal to be sent by an illegal board or the like, and illegal acts can be more reliably prevented.

Next, the operation of the gaming machine will be described. FIG.
5 is a flowchart showing the operation of the basic circuit 53 on the main board 31. As described above, this process is started, for example, every 2 ms by the reset pulse generated by the periodic reset circuit 66. When the basic circuit 53 is started, the basic circuit 53 first sets a clock monitor register incorporated in the CPU 56 to a clock monitor enable state in order to make the clock monitor control operable (step S1). Note that the clock monitor control is a control in which a reset is automatically generated inside the CPU 56 when a decrease or stop of an input clock signal is detected.

Next, the CPU 56 performs a stack setting process for setting the designated address of the stack pointer (step S2). In this example, 00FFH is set in the stack pointer. Then, a system check process is performed (step S3). In the system check process, the CPU 56 determines whether or not the RAM 55 contains an error.
Processing such as initializing 5 is performed.

Next, after processing for setting the command data sent to the display control board 80 in a predetermined area of the RAM 55 is performed (display control data setting processing: step S
4), a process of outputting command data as display control command data is performed (display control data output process: step S5).

Next, processing for outputting the contents of the storage area for various output data to each output port is performed (data output processing: step S6). Further, the lamp timer is decremented by one, and when the lamp timer times out (when it becomes 0), the lamp data pointer is updated and a new value is set in the lamp timer (lamp timer processing: step S7).

Further, output data setting processing for setting output data such as data of the address indicated by the lamp data pointer, jackpot information, start information, and probability variation information output to the hall management computer in the storage area is performed (step S8). ). Further, various abnormality diagnosis processes are performed by a self-diagnosis function provided inside the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S9).

Next, a process of updating each counter indicating a random number for determination, such as a random number for big hit determination used in game control, is performed (step S10).

Next, the CPU 56 performs a special symbol process (step S11). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Further, a normal symbol process is performed (step S12). In normal symbol processing, 7 segments L
A corresponding process is selected and executed according to a normal symbol process flag for controlling the variable display 10 by the ED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 further includes a switch circuit 58
, The state of the gate sensor 12, the starting port sensor 17, and the count sensor 23 are input, and it is determined whether or not there is a prize for each prize port or prize device (switch processing: step S13). Further, the audio timer is decremented by one, and when the audio timer times out (when it becomes 0), the audio data pointer is updated and a new value is set in the audio timer. The data at the address indicated by the audio data pointer is sent to the audio control board 70 (audio processing: step S14).

The basic circuit 53 further performs a process of updating the display random number (step S15). That is, the counter for generating the symbol determining random number and the counter for generating the reach determining random number are counted up (addition is performed by 1).

The basic circuit 53 performs signal processing with the award ball substrate 37 (step S16). That is, when a predetermined condition is satisfied, a prize ball number signal is output to the prize ball substrate 37. CP for controlling the prize ball mounted on the prize ball substrate 37
U drives the ball payout device 97 according to the prize ball number signal. After that, the basic circuit 53 next executes the periodic reset circuit 6.
Step S1 until the reset pulse is given from Step S1
7 is updated.

FIG. 7 is a flowchart showing an example of a program for the special symbol process in the basic circuit 53. The special symbol process process shown in FIG. 7 is a specific process of step S12 in the flowchart of FIG. The CPU 56 of the basic circuit 53 performs a special symbol process according to the value of the special symbol process flag when performing the special symbol process.
Any one of steps S300 to S309 shown in FIG. 7 is performed. In each process, the following processes are performed.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a big hit determination random number is extracted. Special symbol determination processing (step S301): When a state in which the variable display of the special symbol can be started, the number of start winning prizes is confirmed. If the number of start winning prizes is not 0, it is determined whether to make a jackpot or not according to the value of the extracted jackpot determination random number. Stop symbol setting process (step S302): A stop symbol for the left and right middle symbols is determined.

Reach operation setting processing (step S30)
3): Whether or not the reach operation is performed is determined according to the value of the reach determination random number, and the variation mode of the reach operation is determined according to the value of the reach random number.

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the display control board 80,
The left and right middle final stop symbols and information instructing the variation mode are transmitted. When a background or a character is also displayed on the variable display unit 9, control is performed so that display control command data corresponding to the background or character is transmitted to the display control board 80.

All symbols stop waiting processing (step S30)
5): Control is performed so that all symbols displayed on the variable display section 9 are stopped after a predetermined time has elapsed. Also, control is performed so that the left and right symbols are stopped at a predetermined timing until the timing of stopping all symbols.

Big hit display processing (step S306):
If the stop symbol is a combination of jackpot symbols,
The display control command data of the jackpot display is controlled to be sent to the display control board 80, and the internal state (process flag) is updated so as to shift to step S307. Otherwise, the internal state is changed to step S3.
Update to shift to 09. The combination of the big hit symbols is a combination in which the right and left middle symbols are aligned.
Further, the display control CPU 101 of the game control board 80 performs a big hit display on the variable display unit 9 according to the display control command data. The jackpot display is made to notify the player of the occurrence of the jackpot. Big winning opening opening process (step S307): Control for opening the big winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening.

Processing during opening of the special winning opening (step S30)
8): Control for transmitting display control command data of the special winning opening round display to the display control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. If the closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S307 unless the end condition of the big hit gaming state is satisfied. If the jackpot gaming state end condition is satisfied, the internal state is updated to shift to step S309.

Big hit end processing (step S309):
A display for notifying the player that the jackpot gaming state has ended is performed. When the display is completed, the internal flags and the like are returned to the initial state, and the internal state is updated so as to shift to step S300.

The module (step S5 in FIG. 6) which performs the processing of transmitting the display control command in the game control program according to the processing of each of the above steps outputs the corresponding display control command data to the output port and , INT signal to an output port. The module that performs the output data setting process (step S8 in FIG. 6) responds to the timeout of the process timer.
The setting for transmitting the lamp control command to the lamp control board 35 is performed, and the setting for transmitting the display control command data to the voice control board 70 is performed.

FIG. 8 shows the display control board 80 from the main board 31.
FIG. 9 is an explanatory diagram showing display control command data transmitted to the user. As shown in FIG. 8, in this embodiment, display control command data is transmitted from the main board 31 to the display control board 80 through eight signal lines of display control signals CD0 to CD7. Further, between the main board 31 and the display control board 80,
A signal line of a display control signal INT for transmitting an INT signal, a supply line of +5 V and +12 V serving as a power supply of the display control board 80, and a signal line for supplying a ground level are also provided.

FIG. 9 shows a game control board 80 from the main board 31.
FIG. 5 is a timing chart showing transmission timing of the display control command data given to the first embodiment. As shown in FIG. 9, in this embodiment, the INT signal is turned on (low level) for 2 ms after new display control command data is output.
become. When detecting that the INT signal has been turned on, the display control CPU 101 performs processing for importing display control command data. As described later, in this embodiment, the display control command has a 2-byte configuration, so that when one display control command is output, the INT signal is output twice. Note that the port output counter shown in FIG. 9 is a counter used in the display control data output process (step S5) in the main process.

FIG. 10 is an explanatory diagram showing an example of the display control command data. As shown in FIG. 10, the display control command data composed of the 2-byte display control data CMD1 and CMD2 specifies each variation pattern, the fact that the left symbol should be stopped and the left stop symbol at that time. . In these designations, the value of the display control data CMD1 in the first byte is “60 (H)”. Note that FIG. 10 shows only the display control command data related to the stop of the left symbol, but also the display control command data related to the stop of the right symbol, the display control command data related to the stop of the middle symbol, and the display of the left and right middle symbols. Display control command data, display control command data indicating the reach type, display control command data indicating the appearance of the character, display control command data indicating the round display during the big hit game, and the number of times of opening the special winning opening, etc. are prepared. I have. This command data is used when changing the display.
I only once for each of the first and second bytes
When the NT signal goes low, it is transmitted receivably.

In this embodiment, the display control command data has a 2-byte structure. However, even if the display control command data has a structure exceeding 2 bytes, the processing described below can be applied.

FIG. 11 is a flowchart showing an operation example of the display control data setting process (step S4 in the main process). In the display control data setting process, the CP
U56 first checks whether or not the data sending flag is set (step S411). If not set, it is confirmed whether or not the transmission request flag of the display control command data is set (step S41).
2). If the transmission request flag has been set, the transmission request flag is reset (step S413). The display control command data to be transmitted is set in the output data storage area (step S414), and a port output request is set (step S416). The transmission request flag of the display control command data is set in the special symbol process. The data sending flag is set in a display control data output process described later.

FIG. 12 is a flowchart showing the display control data output process (step S5) in the main process shown in FIG. In the display control data output process, the CPU 56 determines whether a port output request has been set (step S421). If the port output request has been set, the port output request is reset (step S422), and the contents of the port storage area (the first byte of the display control command) are output to the output port 571 (step S423). Then, the port output counter is incremented by one (step S424). In addition, INT
The signal (output port 572) is set to low level (step S425), and the data sending flag is turned on (step S426).

If the port output request has not been set, it is determined whether or not the value of the port output counter is 0 (step S431). Port output counter value is 0
If not, it is checked whether the value of the port output counter is 1 (step S432). If the value of the port output counter is 1, the INT signal is turned off (= 1) because it is the INT signal off timing for the first byte of the display control command (step S43).
3). Further, the value of the port output counter is increased by 1 (step S434).

If the value of the port output counter is 2 (step S435), the output timing of the second byte of the display control command has come, so the contents of the port storage area (the second byte of the display control command) Is output to the output port 571 (step S436). Then, the port output counter is incremented by 1 (step S437). Further, the INT signal (output port 572) is set to low level (step S438).

If the value of the port output counter is not 2, that is, if it is 3, the INT signal off timing for the second byte of the display control command has come, and the value of the port output counter is cleared. At the same time (step S441), the INT signal is turned off (high level) (step S442). Further, the data sending flag is turned off (step S443).

In this embodiment, the display control data output process shown in FIG. 12 is executed once every 2 ms. Therefore, as shown in FIG. 9, when the display control command data is output by the data output processing shown in FIG. 12, the situation where the INT signal is at the low level for 2 ms occurs twice.

FIG. 13 is a timing chart showing an example of the timing at which the display control CPU 101 in the display control board 80 takes in the display control command data transmitted from the main board 31. As shown in FIG. 13A, when the same display control command data is received three times in a row, the display control CPU 101 executes a display control process based on the received display control command data. That is, FIG.
The display control process is started at the timing shown in FIG.

As described above, the display control CPU 101
If the same command is received continuously for a predetermined number of times (three times in this example), it is determined that a correct command has been received. Therefore, even if noise is present on the cable between the main board 31 and the display control board 80, etc. , The effects of which can be avoided. In particular, even if there is INT signal noise that cannot be removed even by the noise filter circuit 106 shown in FIG. 5, the influence of the noise can be prevented.

For example, FIG. 13B shows an example in which noise occurs near the timing shown by the symbol and the display control command data at the timing is destroyed. In that case, step S123 shown in FIG.
The display communication counter is cleared by the processing of S126. When the same display control command data can be fetched three consecutive times again, the display control CP
U101 determines that a correct command has been received.
Therefore, display control is not performed based on display control command data in which an error has occurred on a cable or the like.

The basic circuit 53 on the main board 31
Performs control to change the display control command data output from the main board 31 only at the display change point. Further, when the display control command data to be output is changed, a signal (INT signal) indicating that the display control command data has changed is output only for a short predetermined period (in this example, 2 ms). The display control CP on the display control board 80
U101 samples the display control command data in a cycle shorter than the INT signal period.

The display control CPU 101 fetches display control command data only during a short INT period, and
When the T signal is turned off, the capture of the display control command data is stopped.
The effect of noise can be reduced. For example, FIG.
As shown in (C), even if the INT signal has noise on it and the INT signal which is originally off is turned on (timing of '), after the noise disappears, I
The NT signal returns to the OFF state, and in the INT signal OFF state, the display control CPU 101 clears the display communication counter and does not take in display control command data. Therefore, there is no possibility of receiving incorrect display control command data.

As described above, in this embodiment, when the same command can be received a plurality of times in succession, it is determined that the correct command has been received, thereby preventing the influence of noise by software and displaying the command reception period. By limiting the period to a short period after the control command data is changed, the influence of noise is more effectively prevented.

In the above embodiment, the INT signal is prepared separately from the 8-bit display control command data. However, the display control command data is 7 bits,
The INT signal may be assigned to the remaining one bit in one byte. That is, bit 6 to bit 0 (D6
.. D0) are assigned display control command data, and the bit 7 (D7) is assigned an INT signal. When the display control command is configured in such a manner, only one output port (8-bit configuration) is allocated to the display control in the basic circuit 53 of the main board 31.

FIG. 14 is a flowchart showing a display control command receiving process executed by the display control CPU 101. This process is started by, for example, a timer interrupt. In the display control command receiving process, the display control CPU 101 reads 1-byte data from the input port assigned to input of the display control command data (step S121). Next, the state of the INT signal is read from the input port assigned to the input of the INT signal (step S122). As described above, IN
The T signal is set to low level when the basic circuit 53 of the main board 31 outputs new display control command data.

If the INT signal is off, the display communication counter is cleared (step S126). The display communication counter is used to count the number of times display control command data is received when the INT signal is on.

When the INT signal is on, the received display control command data is transmitted immediately before (200 μs before).
It is determined whether the received command data is the same as the received command data (step S123). If they are not the same, the display communication counter is cleared (step S126). If they are the same, it is checked whether the display communication counter has reached a predetermined maximum value (MAX) (step S124).

If the maximum value has not been reached, the value of the display communication counter is incremented by 1 (step S125). Here, the maximum value is a value larger than the value (3 in this example) for determining that the display control command data has been reliably received, and is used for the purpose of counting the number of receptions in 2 ms, for example. Can be

Next, the display control CPU 101 checks whether or not the value after the display communication counter has become "3" (step S127). If it is "3", the communication end flag is set (step S128),
The received display control command data is stored in the received command storage area (step S129). Further, the received display control command data is stored in the work area (step S130). If it is not "3", the read display control command data is stored in the work area without setting the communication end flag (step S13).
0). The data stored in the work area is used in the next interrupt processing in step S123.

When the communication end flag is set, processing such as display switching is performed based on the display control command data stored in the received command storage area.
As described above, the reception of the display control command shown in FIG. 13 is realized.

Although the INT signal is turned on for 2 ms here, the ON period of the INT signal is not limited to 2 ms and may be, for example, 4 ms. When the same display control command data has been captured three consecutive times, the display control CPU 101 determines that the display control command data has been received. However, another value may be used as the number of continuous times.

FIG. 15 is a block diagram showing the award ball control board 37 and its related parts. As shown in FIG. 15, the winning ball detection switch 99 and the full tank switch 40
2 from the main board 31 via the relay board 71.
Is input to the I / O port 57. The prize ball discharge solenoid 127 drives a ball stop member provided in the middle of the prize ball flow path on the back of the game board. The prize ball detection switch is provided when the prize ball is stopped on the ball stop member. 9
The winning ball is detected by 9. The full tank switch 402 is a switch that detects whether the excess ball tray 4 is full.

The detection signals from the out-of-ball detection switch 167 and the out-of-ball switch 187 are input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The ball out detection switch 167 is a prize ball tank 3
8 is a switch for detecting a shortage of replenishment balls, and a ball out switch 187 is a switch for detecting the presence or absence of a prize ball in the prize ball passage.

The CPU 56 of the main board 31 indicates that the detection signal from the out-of-ball detection switch 167 or the out-of-ball switch 187 indicates the out-of-ball state, or the detection signal from the full-state switch 402 indicates the full state. You have
A prize ball control command for instructing ball lending is transmitted. When receiving the award ball control command instructing the ball lending prohibition, the award ball control CPU 371 of the award ball control board 37 stops the ball lending process.

Further, the detection signal from the prize ball count switch 301A for detecting the actually paid prize ball is also transmitted to the main board 31 via the relay board 72 and the relay board 71.
It is input to the / O port 57. In addition, I /
The drive signal from the O port 57 to the winning ball discharge solenoid 127 is transmitted to the winning ball discharging solenoid 1 via the relay board 71.
27. The prize ball count switch 301
A is provided in the prize ball mechanism portion of the ball payout device 97, and detects the prize balls actually paid out.

When there is a prize, a prize ball control command indicating the number of prize balls is input to the prize ball control board 37 from the main board 31. The prize ball control command indicating the number of prize balls is first input to the noise filter circuit 376 using the EMI filter in the prize ball control board 37. Noise filter circuit 3
Reference numeral 76 denotes each bit of the award ball control command data and IN
An EMI filter corresponding to each of the lines of the T signal is included. Therefore, noise on the prize ball control command data between the main board 31 and the prize ball control board 37 is canceled by the noise filter circuit 376. Therefore, it is surely prevented that a prize ball is paid out in a number different from the number of prize balls to be paid out to the player and the player is disadvantaged.

On the output side of the noise filter circuit 3706, an input buffer circuit 373 made of, for example, 74HC14 having hysteresis in the input threshold voltage is provided. Input buffer circuit 3 with hysteresis
Numeral 73 can make the rising and falling of the output waveform sharp even if the input waveform is a waveform that rises and falls gently. That is, the waveform of the prize-ball indication control command input to the prize-ball control CPU 371 does not become dull.

As described above, in this embodiment, noise between the substrates is effectively removed by the noise filter circuit 376, and the waveform rounding due to the filter is shaped by the input buffer circuit 373. Therefore, the prize-ball control command data and the INT signal having a clean waveform containing no noise are input to the prize-ball control CPU 371.

Each element in the input buffer circuit 373 can pass a signal only in a direction from the main board 31 to the prize ball control board 37. Therefore, there is no room for a signal to be transmitted from the award ball control board 37 side to the main board 31 side. Therefore, even if a circuit in the award ball control board 37 is tampered with, a signal output by the tampering is not transmitted to the main board 31 side.

Further, on the signal output side of the main board 31, on the output side of the output port 574 for outputting the prize ball control command data and the INT signal, there is provided an output buffer circuit 613 which allows signals to pass only in one direction. I have.
According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line which may give a signal from the prize ball control board 37 to the main board 31 is more reliably formed. Can be eliminated.

The CPU 371 for controlling the prize ball controls the I / O
Via the port 372, a ball lending number signal indicating the number of lending balls is output to a terminal board (not shown), and a buzzer driving signal is output to a buzzer board (not shown). In addition, I /
An error signal is output to the error display LED 374 via the O port 372. In addition, signals are exchanged with a card unit (not shown in FIG. 15) via the I / O port 372.

Further, the detection signal of the prize ball count switch 301A and the detection signal of the ball lending count switch 301C are input to the prize ball control board 37 via the relay board 72. Prize ball motor 289 from the prize ball control board 37
Is transmitted to the prize ball motor 289 of the ball payout device via the relay board 72. The ball lending count switch 301C detects a game ball actually lent from the ball payout device.

FIG. 16 is an explanatory diagram showing the bit configuration of the award ball control command. As shown in FIG. 16, bit 7 in one byte is used as an INT signal. Also, 7 bits from bit 0 to bit 6 are used as a winning ball control command data portion. The upper three bits of bits 0 to 6 are used as control designation. That is, if bits 6, 5, and 4 are “0, 0, 0”, it indicates normal payout designation (prize ball number output), and if “0, 0, 1”, indicates corrected payout designation, and “0, 0, 1”. "1,0" indicates ball lending prohibition designation, and "1,1,1" indicates ball lending prohibition designation cancellation. The ball lending prohibition is specified when the surplus ball tray 4 is full and the full switch 402 is turned on, and when the out-of-ball detection switch 167 or the out-of-ball switch 187 is turned on. 5
3 is transmitted. Then, when those switches are turned off, ball lending prohibition designation cancellation is transmitted.

The award ball control command is transmitted from the main board 31 to the award ball control board 37 via the output port (port D) 574 as shown in FIG. Then, in this embodiment, as shown in FIG. 17, when the prize ball control command data is output from the main board 31, the INT signal becomes low level for 4 ms. That is, its 4ms
During this time, it is transmitted so that it can be received only once.

Next, the winning ball signal processing on the main board 31 will be described with reference to the flowcharts of FIGS. The winning ball signal processing is performed in step S16 shown in FIG.
Is executed once every 2 ms. First, each timer used will be described. (1) Timer T1: Set when the prize ball count switch 301A is turned off, and when a timeout occurs, the number of payouts is checked. (2) Timer T4: Set when the prize ball control command is sent, and the prize ball count switch is set to 1 before the timeout occurs.
An error will be signaled if it is not turned on again. (3) Timer T5: Set when an error is detected, and an error is displayed until a timeout occurs. (4) Timer T6: The timer T6 is restarted repeatedly each time a timeout occurs. If the cumulative error count exceeds a predetermined count at the time of the timeout, an irrecoverable error occurs. (5) Timer T7: The timer T7 is started when the driving of the winning ball discharge solenoid 127 is started. If the discharging of the winning ball is not confirmed before the time-out, an error is determined.

In the winning ball signal processing, the CPU 56 of the main board 31 first checks whether or not the timer T4 is operating (step S201). If in operation,
It is determined whether or not the timer T4 has timed out (step S202). If the timer T4 times out, an error state is entered (step S203).

If the timer T4 is not operating or has not timed out, it is checked whether the timer T6 has timed out (step S20).
4). If the time-out has occurred, the value of the winning ball error counter is checked (step S205). If the value of the winning ball error counter exceeds a predetermined value, an error state is entered (step S208). In the error state,
The basic circuit 53 enters a halt state (HALT state).
For example, an operation stop flag is set.

If the value of the winning ball error counter does not exceed a predetermined number when the timer T6 times out, the winning ball error counter is initialized (step S206).
The timer T6 is started again (step S20).
7).

As will be described later, the value of the winning ball error counter is counted up when an excessive number of winning balls is detected. Therefore, if a prize ball excess error exceeding a predetermined number occurs within a predetermined time (within the count-up time of the timer T6), the state is not canceled even by the periodic reset signal. In this way, if the system is configured not to be in the halt state immediately when the prize-ball excess error occurs, but to be in the halt state when the prize-ball excess error occurs frequently, it is possible to temporarily recover from the error and recover naturally. The gaming machine is not disabled. In addition, when the prize ball excess error frequently occurs, an inspection or the like is often required. In such a case, the gaming machine can be made inoperable.

Next, the CPU 56 checks whether or not the timer T7 is operating (step S210). If the timer is operating, it is checked whether the timer T7 has timed out (step S211). If the timer T7 has timed out, it means that the winning ball has not been discharged within a predetermined time after the driving of the winning ball discharging solenoid 127 has been started, so that an error occurs (step S211). If the timer T7 has not timed out, it is checked whether or not the winning ball detection switch 99 has been turned off (step S213). If it is turned off, the driving of the winning ball discharge solenoid 127 is stopped (step S214), and the timer T7 is stopped (step S215).

Next, it is checked whether or not the award ball paying flag is on (step S216). If it is on, the process moves to step S230. If the prize ball paying flag is not on, it is checked whether or not the prize ball detection switch 99 is on (step S216). If not, the process ends. If it is turned on, the state of the count switch 23 and the starting port switch 17 is checked (steps S218, S220).

In this embodiment, 15 prize balls are paid out for a prize passing through the special winning opening, 6 prize balls are paid out for a prize passed through the starting winning opening 14, and the other prize opening 24 and the prize winning ball are paid out. It is assumed that ten prize balls are paid out for a winning through the device. Therefore, the count switch 2
When 3 is on, 15 is set as the expected prize ball number (step S219), and when the starter switch 17 is on, 6 is set as the expected prize ball number (step S2).
21). In other cases, 10 is set as the expected prize ball count (step S222). To set the expected number of prize balls,
Specifically, it is to set data of "normal payout designation" and "number designation" in the port D storage area (see FIG. 16). The turning on of the count switch 23 and the starter switch 17 is detected in the switch process (step S13) shown in FIG. 6, and the fact is stored in a predetermined RAM area.

Then, the CPU 56 sets a port D output request (step S223). Further, a T4 timer is set (step S224). Here, the CPU 5
No. 6 confirms whether or not the winning ball detection switch 99 is turned off (step S225). If it has been turned off, it means that the winning ball has been missed even though the winning ball discharging process has not been started, so an error occurs (step S22).
6). If there is no error, the driving of the prize ball discharge solenoid 127 is started to discharge the prize ball parked at the stopping portion in the prize ball processing device (step S22).
7).

Then, the CPU 56 turns on the award ball paying-out flag (step S228). Further, a timer T7 for monitoring the winning ball discharge is started (step S7).
229), and the process ends. Next, when the winning ball signal processing is executed, the turning-off of the winning ball detection switch 99 is confirmed in step S213, and the winning ball paying-out flag is on, so that the process proceeds from step S216 to step S230. I do.

At the step S230, the CPU 56
Confirms whether the error display flag is on.
If it is on, the process moves to step S245. In addition,
The error display flag will be described later. If the error display flag is not turned on, the prize ball count switch 3
Wait for 01A to turn on (step S231). When the turning-on of the winning ball count switch 301A is detected, the T4 timer is stopped (step S232). And
It waits for the award ball count switch 301A to be turned off (step S233), and when it is turned off, increments the award ball count number by one (step S234).

Then, the timer T1 is started (step S235). Timer T1 is a prize ball count switch 30
Each time the 1A output is turned on after being turned on, it is started or restarted. If the award ball count switch 301A is not turned on in step S231, it is checked whether or not the timer T1 is operating (step S236). Timer T1
Is operating, the CPU 56 checks whether or not the timer T1 has timed out (step S240). If the timeout has not occurred, the process ends. Next,
When the prize ball signal processing is executed, the prize ball paying-out flag is on, so that the process also proceeds from step S216 to step S230.

The value of the timer T1 (the time from the start to the time-out) is a payout cycle (a period from when the prize ball count switch 301A is turned on to when it is turned on next time) when payout is normally performed. ) Is set longer. Therefore, when the payout is normally performed, the next award ball count switch 301A is turned on (step S231) before the timer T1 times out, except for the last payout. That is, when the payout is normally performed, the timer T1 times out only after the last payout is performed.

When the timer T1 times out in step S240, the CPU 56 compares the winning ball count number with the expected winning ball number or the corrected number (step S2).
41). If the payout is completed successfully, they match. Therefore, the award ball payout flag is turned off, and the process ends (step S243).

If the counted number of winning balls does not match the expected number of winning balls or the corrected number when the timer T1 times out, the CPU 56 checks which one is more (step S244). If the prize ball count is less than the expected prize ball count or the correction number, that is, if it is determined that the payout is insufficient, a correction number output request is set (step S246), and the timer T4 is started (step S247). . When setting the corrected number output request, the data of “correction payout designation” is set in the port D storage area and “number designation” is set (see FIG. 16).

In step S244, if the prize ball count is larger than the expected prize ball count or the corrected number, that is, if it is determined that the payout is excessive, an error display process is performed (step S245).

FIG. 20 is a flowchart showing an example of the error display process. In the error display process, the CPU
56 first checks whether the timer T5 is operating (step S251). If not in operation, the error display flag is turned on (step S252), and an error display request is set (step S253). Then, it is determined whether or not the generated error is an error to be automatically recovered (step S254). In this embodiment, the error to be automatically recovered is an error of excessive payment. If the error is to be automatically restored, the timer T5 (for example, 3 seconds) is started (step S256). Further, the value of the winning ball error counter is incremented by 1 (step S257). The value of the prize ball error counter is checked in step S205, and if the value exceeds a predetermined value within a predetermined time, a complete error state where automatic recovery is not performed is set.

If the timer T5 is operating in step S251, the CPU 56 checks whether the timer T5 has timed out (step S26).
0). If the timeout has occurred, the error display request is reset (step S261), and the error display flag is turned off (step S262). Further, the award ball paying flag is turned off (step S263). Therefore, the gaming machine returns to a state where the winning ball detection and the winning ball payout control can be performed again. When the error display flag is on, the game progress is interrupted.

If it is determined in step S254 that the error does not automatically recover (hardware error), the process waits for hardware recovery (step S25).
5). That is, the error state of step S211 (the winning ball detection switch 99 was not turned off even though the winning ball discharging solenoid 127 was driven = the winning ball was not removed), and the error state of step S226 (the winning ball discharging solenoid). (The winning ball detection switch 99 is turned on despite the fact that the player has not driven the player 127 = the winning ball has been removed). For example, an error display or an error notification is performed, and the halt state is set until the hardware failure is recovered. Is controlled so that

In this embodiment, the above-described hardware error has been exemplified. However, if the on-state of the prize ball count switch 301A continues for a predetermined time or more, an error occurs or the prize ball operation is stopped. An error may occur when the award ball count switch 301A is turned on even though it has not started.

FIG. 21 is a flowchart showing a winning ball control command output portion of the data output process (step S6) in the main process shown in FIG. In a data output process related to award ball control command output, the CPU
56 determines whether the port D output request is set (step S671). The port D output request is set when the expected number of winning balls is determined in the winning ball signal processing shown in FIG. 18 (step S22).
3).

If the port D output request has been set, the port D output request is reset (step S67).
2) Output the contents of the port D storage area to the output port (output port D) 574 (step S673). Prize ball control command data is set in bits 0 to 6 of the port D storage area, and 0 is set in bit 7. Then, the port D output counter is incremented by 1 (step S67).
4).

If the port D output request has not been set, the CPU 56 determines whether or not the corrected number output request has been set (step S675). The corrected number output request is set when it is detected in the prize ball signal processing shown in FIGS. 18 and 19 that the prize balls have not been performed up to the expected prize ball number (steps S244 and S2).
46).

If the corrected number output request is set, the corrected number output request is reset (step S67).
6) Output the contents of the port D storage area to the output port (output port D) 574 (step S677). Then, the port D output counter is incremented by 1 (step S67).
8).

If neither the port D output request nor the corrected number output request is set, it is determined whether the value of the port D output counter is 0 (step S681). If the value of the port D output counter is not 0, it is checked whether the value of the port D output counter is 2 (step S).
682). If the value of the port D output counter is not 2, that is, it is 1, the value of the port D output counter is increased by 1 (step S683).

If the value of the port D output counter is 2, the value of the port D output counter is cleared (step S684), and the output port (output port D) 5 is cleared.
The bit 7 of 74 is set to 1 (step S685).

Bit 7 of the output port D is a port for outputting an INT signal applied to the award ball control board 37.
Bits 0 to 6 of the output port D are ports for outputting award ball control command data. Then, in this embodiment, the data output process shown in FIG. 21 is executed once every 2 ms. Therefore, when the award ball control command data is output as shown in FIG. 17 by the data output processing shown in FIG. 21, the INT signal goes low for 4 ms.

[0129] Here, the case where a prize ball control command including the number of prize balls and the number of corrections are output as the processing of the prize ball control command output processing portion has been described. When a transmission request of "prohibition specification release specification" is received, a prize ball control command including them is output.

FIG. 22 is a flowchart showing a prize ball data receiving process executed by the prize ball control CPU 371.
The prize ball data receiving process is started by, for example, a timer interrupt. In the award ball data receiving process, the award ball control CP
The U371 reads 1-byte data from the input port assigned to the input of the prize ball control command (Step S321). As described above, bit 7 of the prize ball control command is an INT signal, and is set to a low level when the basic circuit 53 of the main board 31 outputs new prize ball control command data using bits 0 to 6. You. Therefore, the CPU 371 for controlling the prize ball checks whether or not the INT signal is ON (= 0) (step S322).

If the INT signal is off, the winning ball communication counter is cleared (step S326). The winning ball communication counter is used to count the number of receiving the winning ball control command data when the INT signal is on.

When the INT signal is on, the received command (bits 0 to 6) is immediately before (for example, 500 bits).
It checks whether it is the same as the received command (before μs) (step S323). If they are not the same, the award ball communication counter is cleared (step S326). If they are the same, it is checked whether or not the award ball communication counter has reached a predetermined maximum value (MAX) (step S324). If the maximum value has not been reached, the value of the prize ball communication counter is set to +
1 (step S325). Here, the maximum value is a value larger than a value (3 in this example) for determining that the award ball control command data has been reliably received, for example, 4 m.
It is used for purposes such as counting the number of receptions during s.

Next, the award ball control CPU 371 checks whether or not the value after the award ball communication counter has reached "3" (step S327). If it is "3", the communication end flag is set (step S328), and
The received prize ball control command data is stored in the received command storage area (step S329). The received prize ball control command data is stored in the work area (step S330). If it is not "3", the received prize ball control command data is stored in the work area without setting the communication end flag (step S33).
0). The data stored in the work area is used in the next interrupt processing in step S323.

FIG. 23 is a timing chart showing an example of the timing at which the prize ball control CPU 371 of the prize ball control board 37 captures the prize ball control command transmitted from the main board 31. As shown in FIG. 23A, when the same winning ball control command data is received three times in succession, the winning ball control CPU 371 executes the winning ball control based on the received winning ball control command data. That is, the prize ball control is started at the timing shown in FIG.

As described above, the CPU 371 for controlling the prize ball
When the same command is received a predetermined number of times (three times in this example) continuously, it is determined that a correct command has been received. Therefore, it is assumed that noise is present on the cable between the main board 31 and the prize ball control board 37 or the like. Can also avoid that effect. For example, FIG. 23B shows an example in which noise occurs near the timing indicated by, and the winning ball control command data at the timing is destroyed. In that case, step S323 shown in FIG.
And the award ball communication counter is cleared by the processing of S326. When the same award ball control command data is received three consecutive times again, the award ball control CPU
371 determines that the correct command has been received. Therefore, the award ball control is not performed based on the award ball control command in which an error has occurred on a cable or the like.

Further, as in the process of step S223 in the flowchart shown in FIG. 18, the basic circuit 53 on the main board 31 performs control of transmitting the prize ball control command only once. Further, when outputting the output prize ball control command, only a short predetermined period (in this example, 4 m
s), a signal (I
NT signal). Then, the prize ball control CPU 371 in the prize ball control board 37 samples the prize ball control command data in a cycle shorter than the INT signal period.

The prize ball control CPU 371 fetches prize ball control command data only during a short INT period,
When the T signal is turned off, the capture of the prize ball control command data is stopped.
The effect of noise can be reduced. For example, FIG.
As shown in (C), even if the INT signal has noise on it and the INT signal which is originally off is turned on (timing of '), after the noise disappears, I
The NT signal returns to the off state, and in the INT signal off state, the prize ball control CPU 371 clears the prize ball communication counter and does not take in the prize ball control command data. Therefore, it does not happen that wrong prize ball control command data is received.

As described above, in this embodiment, if the same command can be received a plurality of times in succession, it is determined that the correct command has been received, so that the influence of noise is prevented by software and the command reception period is displayed. By limiting the period to a short period after the control command data is changed, the influence of noise is more effectively prevented.

In the above embodiments, the main substrate 3
The inter-substrate communication between 1 and the display control board 80 and the award ball control board 37 has been described as an example, but the present invention is not limited to these inter-substrate communications. The present invention may be applied to inter-board communication between the voice control board 70, the lamp control board 35, and other boards and the main board 31.

The gaming machine of each of the above-described embodiments, that is, the pachinko gaming machine shown in the front view of FIG. 1, has a special symbol that is variably displayed on the variable display section 9 based on a winning start. Although it was a first-class pachinko gaming machine in which a predetermined game value could be given to a player when a predetermined combination of symbols was reached, a predetermined area was determined when an electric accessory that was opened based on a start winning prize entered a predetermined area. Winning a second-class pachinko gaming machine that allows a player to give a game value to a player, and a predetermined electric role that is opened when a stop symbol of a symbol variably displayed based on a winning start becomes a predetermined symbol combination. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a certain right.

[0141]

As described above, according to the present invention, a game machine is controlled by a main board having game control means for controlling the progress of the game and the components of the game machine in response to control commands from the game control means. And another board having control means for performing the control command, the other board has a noise filter circuit in a control command receiving unit, and further has a circuit element having a hysteresis characteristic on an output side of the noise filter circuit. With this configuration, the control command can be transmitted more reliably from the main board to the other board on which the control means is mounted, so that an appropriate game can always be played.

When the game control means is configured to transmit a control command to another board only once at the control change point, the control for sending the control command in the game control means is simplified. effective.

In the case where the control command can be transmitted only in the direction from the main board to another board, the input of an illegal signal to the main board is prevented, and the illegal action is hardly received. Can be.

When the game control means is configured to output a control command through an irreversible transmission means capable of transmitting a signal in only one direction, it is possible to more reliably prevent an illegal act. Can be.

When the other substrate is a substrate on which display control means for controlling the display state of the display device is mounted, it is prevented that information other than the information to be displayed is displayed. , It is possible to prevent the player from feeling suspicious.

If the other substrate is a substrate on which a prize ball control means for controlling the prize ball payout means is mounted, the correct number of prize balls is reliably paid out, and the player's shortage due to lack of prize balls. It is possible to reliably prevent profits and disadvantages of the game store due to excessive prize balls.

If the control means mounted on another board fetches the control command in a cycle shorter than the validity period of the control command from the game control means, and fetches the same control command continuously for a predetermined number of times within the validity period, it is correct. If the control command is received and the control is performed based on the control command, noise control is also performed by software control, and the control command is transmitted to other boards more reliably. Can be.

If the control means mounted on another board detects an error in the control command, the control means starts the process of retrieving the control command from that point in time. Transmission and reception of strong control commands can be realized.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is a front view of the gaming board of the pachinko gaming machine as viewed from the front.

FIG. 3 is a rear view of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram showing a circuit configuration of a game control board (main board).

FIG. 5 is a block diagram illustrating a circuit configuration example of a display control board.

FIG. 6 is a flowchart showing main processing of a basic circuit on a main board.

FIG. 7 is a flowchart showing an example of a special symbol process processing program.

FIG. 8 is an explanatory diagram showing display control command data transmitted from the main board to the display control board.

FIG. 9 is a timing chart showing transmission timing of display control command data.

FIG. 10 is an explanatory diagram illustrating an example of display control command data.

FIG. 11 is a flowchart showing a display control data setting process in a main process.

FIG. 12 is a flowchart showing a display control data output process in a main process.

FIG. 13 is a timing chart showing an example of a timing at which the display control CPU captures a display control command transmitted from the main board.

FIG. 14 is a flowchart illustrating a display control command receiving process.

FIG. 15 is a block diagram showing a prize ball control board and components related thereto.

FIG. 16 is an explanatory diagram showing a bit configuration of a winning ball control command.

FIG. 17 is a timing chart showing how the award ball control command data is output.

FIG. 18 is a flowchart showing winning ball signal processing.

FIG. 19 is a flowchart showing winning ball signal processing.

FIG. 20 is a flowchart showing error processing in winning ball signal processing.

FIG. 21 is a flowchart showing a prize ball control command output processing portion of the data output processing.

FIG. 22 is a flowchart showing a prize ball control command receiving process.

FIG. 23 is a timing chart showing an example of the timing at which the CPU for controlling a winning ball receives a winning ball control command transmitted from the main board.

[Explanation of symbols]

 1 Pachinko gaming machine 31 Main board 37 Prize ball control board 53 Basic circuit 56 CPU 80 Display control board 101 Display control CPU 105 Input buffer circuit 106 Noise filter circuit 371 Prize ball control CPU 373 Input buffer circuit 376 Noise filter circuit 611, 612,613 output buffer circuit

Claims (8)

[Claims] 1. A gaming machine capable of performing a special game by winning a game medium to a specific winning section, and shifting to a specific gaming state that is advantageous to a player based on a result of the special game being in a predetermined mode. A main board having game control means for controlling the progress of the game,
Another board having control means for controlling a gaming machine component in response to a control command from the game control means, the other board having a noise filter circuit in a control command receiving unit, A gaming machine comprising a circuit element having a hysteresis characteristic on an output side of a noise filter circuit. 2. The game machine according to claim 1, wherein the game control means transmits the control command to another board only once at the control change point. 3. The gaming machine according to claim 1, wherein the control command can be transmitted only in a direction from the main board to another board. 4. The gaming machine according to claim 3, wherein the game control means outputs the control command via an irreversible transmission means capable of transmitting a signal in only one direction. 5. The gaming machine according to claim 1, wherein the other substrate is a substrate on which display control means for controlling a display state of the display device is mounted. 6. A gaming machine having a prize ball payout means for paying out a prize ball to a player, wherein the other board is a board on which a prize ball control means for controlling the prize ball payout means is mounted. The gaming machine according to claim 1. 7. A control means mounted on another board captures a control command in a cycle shorter than a validity period of the control command from the game control means, and captures the same control command continuously for a predetermined number of times within the validity period. The gaming machine according to claim 1, wherein the control based on the control command is performed when a correct control command is received. 8. The control means mounted on another substrate,
8. The gaming machine according to claim 7, wherein when an error in the control command is detected, processing for retrieving the control command in a cycle shorter than the validity period of the control command from the game control means is started from that point.