JPH04245343A - Memory clearing circuit - Google Patents

Abstract

PURPOSE:To clear or check a memory for a system which has a CPU mounted and is controlled by firmware by memory clearing circuit even when a software is not completed. CONSTITUTION:The memory for the system which has the CPU mounted and is controlled by the firmware is equipped with a memory clearing address counter part 11, an address selecting part 12 which selects and outputs one of a memory clearing address from the address counter part 11 and a normal address to an address bus 5 extending to the memory, a memory clearing data generation part 13, and a data selecting circuit 14 which selects and outputs either of the memory clearing data from the data generating part 13 and normal data to a data bus 6 extending to the memory.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory clear circuit for clearing a memory for a system mounted with a CPU and controlled by firmware.

[0002] A system in which a CPU is mounted and whose operation is controlled by firmware has a large amount of memory (RAM).
However, it is necessary to check whether there are any defects in the data and address bus lines connected to such memory, or whether there are any defects in the memory IC. Furthermore, when resetting the system or resetting the memory, it is necessary to write initial data (clear data). Because of this necessity, it is necessary to perform the above checking and clearing operations accurately and quickly.

0003

DESCRIPTION OF THE PRIOR ART FIG. 7 is a block diagram showing a conventional configuration for memory clearing and memory checking.
, 1 is a CPU, 2 is a ROM, 3 is a RAM, and 4 is an external unit such as a data processing circuit. connected.

By the way, various programs are stored in the ROM 2, including a memory clear program (the program area A is shown in FIG. 8(a)) and a memory check program ( A program area B (shown in FIG. 8(b)) is also provided. Note that the memory clear program and memory check program are created to suit each system.

Further, while memory clearing or memory checking is being performed, a busy signal is sent from the CPU 1 to the unit 4.

[0006] Therefore, memory clearing or memory checking is executed using the memory clearing program and memory checking program in the ROM 2 described above. During memory clearing or memory checking, a busy signal is sent to unit 4, so unit 4
Processing has been suspended.

An example of a flowchart for clearing the memory is shown in FIG. That is, in step a1, the required address is accessed, initial data (clear data) is written (step a2), it is determined whether it is the maximum address, and the address is incremented until it reaches the maximum address (steps a2 to a4). ), when the maximum address is reached, access the maximum address and exit (step a5
).

[0008]

However, in such conventional devices, memory clearing or memory checking cannot be performed only by hardware, and a software part is required. Therefore, even if the hardware is completed, there is a problem in that the memory cannot be cleared or checked unless the software is completed.

Furthermore, even if an error is detected by the memory check, it is difficult to determine whether the cause is due to hardware or software.

[0010] Furthermore, when the memory becomes large-scale, there is a problem that it takes time to clear the memory or check the memory.

The present invention was devised in view of the above-mentioned problems, and it is an object of the present invention to provide a memory clear circuit that can perform memory clear or memory check even if the software is not completed. purpose.

0012

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, 11 is an address counter section, and this address counter section 11 is a system in which a CPU is mounted and controlled by firmware. This function generates an address for clearing the memory.

Reference numeral 12 denotes an address selector section, and this address selector section 12 selects either the memory clear address or the normal address from the address counter section 11 and outputs the address to the address bus 5 to the memory. It is something to do.

13 is a data generation unit for memory clearing;
14 is a data selector section, and this data selector section 14
selects either the memory clear data or the normal data from the data generation section 13 and outputs the data to the data bus 6 to the memory.

Reference numeral 15 denotes a memory check comparator, and this comparator 15 compares the memory clear data from the data generation section 13 with the data from the data selector section 14.

[0016]

[Operation] In the memory clear circuit of the present invention described above, when clearing the memory, the address selector section 12 is placed on the address counter section 11 side, and the data selector section 1
4 on the data generation section 13 side. As a result, the address selector section 12 selects the address for memory clearing from the address counter section 11 and outputs it to the address bus 5 to the memory, and the data selector section 14 selects the address for clearing the memory from the address counter section 11 and outputs it to the address bus 5 to the memory. The data for memory clearing is selected and output to the data bus 6 to the memory.

Furthermore, when checking the memory, the comparator 15 compares the data for memory clearing from the data generating section 13 with the data from the data selector section 14,
If they do not match, an error signal is generated.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing an example of a system having the circuit of the present invention. In FIG. 2, 1 is a CPU;
3 is a ROM, 3 is a RAM, and 4 is an external unit. These CPU 1, ROM 2, RAM 3, and unit 4 are connected to each other via an address bus 5 and a data bus 6. Note that the ROM2 and RAM3 are configured as peripheral circuits of the CPU1. That is, this example also has
This can be said to be about a system in which the CPU 1 is mounted and controlled by firmware.

By the way, the unit 4 has a built-in RAM clear/check circuit 10 for clearing and checking the RAM 3.

As shown in FIG. 3, this RAM clear/check circuit 10 includes an address counter section 11,
It includes an address selector section 12, a data generation section 13 for memory clearing, a data selector section 14, and a comparator 15 for memory checking.

[0022] Here, the address counter section 11
It generates an address for clearing M3, and the address selector section 12 is connected to the address counter section 11.
Select either the memory clear address or the normal address from address bus 5 to RAM 3.
This outputs the address to.

The data generation unit 13 for memory clearing generates initial data for clearing the memory, and the data selector unit 14 selects either the data for memory clearing or the normal data from the data generation unit 13. do,
It outputs data to the data bus 6 to the RAM 3.

The memory check comparator 15 compares the memory clear data from the data generator 13 with the data from the data selector 14.

With the above-described configuration, when clearing the memory, upon receiving a select signal, the address selector section 12 is placed on the address counter section 11 side, and the data selector section 14 is placed on the data generation section 13 side. This results in
From the address selector section 12, the address counter section 1
An address for memory clearing from 1 is selected, and this is output to the address bus 5 to the RAM 3.
The data selector 14 selects the data for memory clearing from the data generator 13 and stores it in the RAM 3.
is output to the data bus 6.

Furthermore, when checking the memory, the comparator 15 compares the memory clear data from the data generator 13 with the data from the data selector 14.
If they do not match, an error signal is generated. If both match, a normal signal is output.

Note that during memory clearing and memory checking, a busy signal is output from the data generation section 13 to the CPU 1, so the CPU 1 does not access the RAM 3.

When the memory clear and memory check are completed, the select signal level changes, so the address selector section 12 selects the normal address and outputs it to the address bus 5 to the RAM 3.
The data selector unit 14 selects normal data and outputs it to the data bus 6 to the RAM 3.

A time chart for memory clearing is shown in FIG. 4, and a time chart for memory checking is shown in FIG. 5.

In this way, in this embodiment, it is possible to clear the memory and check the memory using only the hardware without having to complete the software, so that defects in bus lines, etc. can be discovered early and easily. Can be done. In addition, since the processing speed is significantly faster than that of software, the time it takes to stop the system can be shortened.
This also saves the effort of creating programs for memory clearing and memory checking.

Furthermore, as shown in FIG. 6, a plurality (n) of CPUs 1 are provided, and a ROM is provided as a peripheral circuit of each CPU
The present invention can also be applied to a device having a RAM 2 and a dual port RAM 3'. In this case, the unit 4 includes each CPU1,
Common to the peripheral circuits, this unit 4 includes a RAM clear/check circuit 10 for clearing and checking each dual port RAM 3'. As shown in FIG. 3, this RAM clear/check circuit 10 also includes an address counter section 11, an address selector section 12, a data generation section 13 for memory clearing, a data selector section 14, and a comparator 15 for memory checking. It is assumed that this is provided.

[0032] Even in this way, it is possible to clear the memory and check the memory using only the hardware without having to complete the software, and thereby defects in bus lines, etc. can be discovered early and easily, and furthermore, compared to software, it is possible to clear the memory and check the memory using only the hardware. Because the processing speed is extremely fast, the time it takes to stop the system can be shortened, and the time required to create programs for memory clearing and memory checking can also be eliminated.

In addition, especially when dealing with large-capacity RAM or dual-port RAM, memory clearing and memory checking can be performed at a much faster speed than when using software, so the effectiveness of the present invention is improved. is large. Furthermore, it is also highly effective when the unit is implemented as an LSI.

[0034]

[Effects of the Invention] As detailed above, according to the memory clear circuit of the present invention, it is possible to clear the memory and check the memory using only the hardware without completing the software. Defects can be discovered early and easily, and since the processing speed is significantly faster than that of software, the time it takes to stop the system can be shortened, and it has the advantage of eliminating the need to create programs for memory clearing and memory checking. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 is a block diagram illustrating an example system having a circuit of the present invention.

FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 4 is a time chart for explaining one embodiment of the present invention.

FIG. 5 is a time chart for explaining one embodiment of the present invention.

FIG. 6 is a block diagram illustrating another example system having a circuit of the present invention.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8(a) is a diagram illustrating a conventional program area for memory clearing, and FIG. 8(b) is a diagram illustrating a conventional program area for memory checking.

FIG. 9 is a flowchart for explaining conventional memory clearing.

[Explanation of symbols]

1 CPU 2 ROM 3 RAM 3' Dual port RAM 4 Unit 5 Address bus 6 Data bus 10 RAM clear/check circuit 11 Address counter section 12 Address selector section 13 Data generation section for memory clear 14 Data selector section 15 Comparison for memory check vessel

Claims (2)

[Claims] [Claim 1] Regarding a system memory (3) in which a CPU (1) is mounted and controlled by firmware, an address counter section (11) for memory clearing and a memory clearing from the address counter section (11) are provided. an address selector section (12) that selects one of the normal address and the normal address and outputs the address to the address bus (5) to the memory (3); and a data generation section (13) for memory clearing. and a data selector section (14) that selects either the memory clear data or normal data from the data generation section (13) and outputs the data to the data bus (6) to the memory (3). ) A memory clear circuit characterized by comprising: 2. A comparator (15) for memory checking that compares the data for memory clearing from the data generation section (13) and the data from the data selector section (14).
2. The memory clear circuit according to claim 1, further comprising a memory clear circuit.