JP2001244331A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2001244331A5 JP2001244331A5 JP2000050903A JP2000050903A JP2001244331A5 JP 2001244331 A5 JP2001244331 A5 JP 2001244331A5 JP 2000050903 A JP2000050903 A JP 2000050903A JP 2000050903 A JP2000050903 A JP 2000050903A JP 2001244331 A5 JP2001244331 A5 JP 2001244331A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- concave pattern
- interlayer insulating
- wiring
- embedded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims 26
- 239000011229 interlayer Substances 0.000 claims 11
- 230000004888 barrier function Effects 0.000 claims 9
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 24
- 238000005530 etching Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 3
- 238000000576 coating method Methods 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000050903A JP2001244331A (ja) | 2000-02-28 | 2000-02-28 | 半導体集積回路装置およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000050903A JP2001244331A (ja) | 2000-02-28 | 2000-02-28 | 半導体集積回路装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001244331A JP2001244331A (ja) | 2001-09-07 |
JP2001244331A5 true JP2001244331A5 (enrdf_load_stackoverflow) | 2005-04-07 |
Family
ID=18572635
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000050903A Pending JP2001244331A (ja) | 2000-02-28 | 2000-02-28 | 半導体集積回路装置およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2001244331A (enrdf_load_stackoverflow) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005167081A (ja) | 2003-12-04 | 2005-06-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7176571B2 (en) * | 2004-01-08 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure |
JP2005236141A (ja) * | 2004-02-20 | 2005-09-02 | Oki Electric Ind Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP4540504B2 (ja) * | 2005-03-03 | 2010-09-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2007027347A (ja) * | 2005-07-15 | 2007-02-01 | Sony Corp | 半導体装置およびその製造方法 |
JP2008010630A (ja) * | 2006-06-29 | 2008-01-17 | Sharp Corp | 半導体装置およびその製造方法 |
-
2000
- 2000-02-28 JP JP2000050903A patent/JP2001244331A/ja active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8298954B1 (en) | Sidewall image transfer process employing a cap material layer for a metal nitride layer | |
US9373580B2 (en) | Dual hard mask lithography process | |
US7947907B2 (en) | Electronics structures using a sacrificial multi-layer hardmask scheme | |
JP5306196B2 (ja) | 誘電体空隙を有する相互接続構造体 | |
JPH1187502A (ja) | 半導体装置の製造方法 | |
JP2002050684A (ja) | デュアルダマシン配線構造の半導体素子及びその製造方法 | |
JP3700460B2 (ja) | 半導体装置およびその製造方法 | |
JPH11176814A (ja) | 半導体装置の製造方法 | |
CN100390929C (zh) | 形成半导体器件的方法和半导体器件 | |
JP2000188330A (ja) | デュアルダマシン配線の形成方法 | |
US6686643B2 (en) | Substrate with at least two metal structures deposited thereon, and method for fabricating the same | |
KR100342639B1 (ko) | 반도체 구조물의 제조 방법 | |
JP2001244331A5 (enrdf_load_stackoverflow) | ||
TWI767964B (zh) | 後段介電質蝕刻用之選擇性沉積方法 | |
US20090085210A1 (en) | Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits | |
JP2001244331A (ja) | 半導体集積回路装置およびその製造方法 | |
JP3282607B2 (ja) | 半導体装置の製造方法 | |
JP4207113B2 (ja) | 配線構造の形成方法 | |
JP2007511087A (ja) | コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 | |
JP2001189383A (ja) | 半導体素子の金属配線並びにその製造方法 | |
KR100548570B1 (ko) | 반도체소자의 금속배선 형성방법 | |
JP2005012050A (ja) | 半導体装置の製造方法及び半導体装置 | |
JP4436606B2 (ja) | 半導体装置の製造方法 | |
CN100431133C (zh) | 半导体器件的制造方法和利用这种方法获得的半导体器件 | |
JP4211235B2 (ja) | コンタクトホール形成方法 |