JP2001044421A5 - - Google Patents

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Publication number
JP2001044421A5
JP2001044421A5 JP1999211800A JP21180099A JP2001044421A5 JP 2001044421 A5 JP2001044421 A5 JP 2001044421A5 JP 1999211800 A JP1999211800 A JP 1999211800A JP 21180099 A JP21180099 A JP 21180099A JP 2001044421 A5 JP2001044421 A5 JP 2001044421A5
Authority
JP
Japan
Prior art keywords
insulating film
gate
dummy gate
interlayer insulating
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999211800A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001044421A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP11211800A priority Critical patent/JP2001044421A/ja
Priority claimed from JP11211800A external-priority patent/JP2001044421A/ja
Priority to US09/487,620 priority patent/US6235564B1/en
Publication of JP2001044421A publication Critical patent/JP2001044421A/ja
Publication of JP2001044421A5 publication Critical patent/JP2001044421A5/ja
Pending legal-status Critical Current

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JP11211800A 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法 Pending JP2001044421A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11211800A JP2001044421A (ja) 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法
US09/487,620 US6235564B1 (en) 1999-07-27 2000-01-20 Method of manufacturing MISFET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11211800A JP2001044421A (ja) 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法

Publications (2)

Publication Number Publication Date
JP2001044421A JP2001044421A (ja) 2001-02-16
JP2001044421A5 true JP2001044421A5 (enExample) 2006-08-24

Family

ID=16611825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11211800A Pending JP2001044421A (ja) 1999-07-27 1999-07-27 Ｍｉｓｆｅｔの製造方法

Country Status (2)

Country Link
US (1) US6235564B1 (enExample)
JP (1) JP2001044421A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
WO2005057663A2 (en) * 2003-12-10 2005-06-23 Koninklijke Philips Electronics N.V. Method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices
US7138323B2 (en) * 2004-07-28 2006-11-21 Intel Corporation Planarizing a semiconductor structure to form replacement metal gates
JP5380827B2 (ja) 2006-12-11 2014-01-08 ソニー株式会社 半導体装置の製造方法
WO2008072573A1 (ja) * 2006-12-11 2008-06-19 Sony Corporation 半導体装置の製造方法および半導体装置
DE102007015505B4 (de) * 2007-03-30 2009-01-02 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Halbleiterstruktur
KR100935773B1 (ko) * 2007-11-26 2010-01-06 주식회사 동부하이텍 반도체 소자의 제조 방법
CN102117750B (zh) * 2009-12-30 2012-08-29 中国科学院微电子研究所 Mosfet结构及其制作方法
JP5598145B2 (ja) * 2010-08-04 2014-10-01 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
KR20160127891A (ko) * 2015-04-27 2016-11-07 삼성전자주식회사 싸이클 공정을 이용한 수직 패턴의 형성방법
KR102456077B1 (ko) * 2015-06-22 2022-10-19 삼성디스플레이 주식회사 박막 트랜지스터 기판의 제조방법
JP7071841B2 (ja) * 2018-02-28 2022-05-19 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03250741A (ja) 1990-02-28 1991-11-08 Fujitsu Ltd 半導体装置の製造方法
US5227326A (en) * 1991-12-23 1993-07-13 Texas Instruments Incorporated Method for fabricating non-volatile memory cells, arrays of non-volatile memory cells
JPH06342810A (ja) 1993-02-22 1994-12-13 Sumitomo Electric Ind Ltd ショットキ接合型電界効果トランジスタおよびその製造方法
JP3298601B2 (ja) * 1994-09-14 2002-07-02 住友電気工業株式会社 電界効果トランジスタおよびその製造方法
JPH09246543A (ja) 1996-03-07 1997-09-19 Hitachi Ltd 半導体集積回路装置の製造方法
JP4540142B2 (ja) * 1999-01-19 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

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