JP2001015403A5 - - Google Patents

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Publication number
JP2001015403A5
JP2001015403A5 JP1999181878A JP18187899A JP2001015403A5 JP 2001015403 A5 JP2001015403 A5 JP 2001015403A5 JP 1999181878 A JP1999181878 A JP 1999181878A JP 18187899 A JP18187899 A JP 18187899A JP 2001015403 A5 JP2001015403 A5 JP 2001015403A5
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JP
Japan
Prior art keywords
alignment mark
insulating layer
semiconductor substrate
semiconductor device
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP1999181878A
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English (en)
Japanese (ja)
Other versions
JP4037561B2 (ja
JP2001015403A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP18187899A priority Critical patent/JP4037561B2/ja
Priority claimed from JP18187899A external-priority patent/JP4037561B2/ja
Priority to CN00122585.5A priority patent/CN1199265C/zh
Priority to US09/604,791 priority patent/US6392300B1/en
Publication of JP2001015403A publication Critical patent/JP2001015403A/ja
Publication of JP2001015403A5 publication Critical patent/JP2001015403A5/ja
Application granted granted Critical
Publication of JP4037561B2 publication Critical patent/JP4037561B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP18187899A 1999-06-28 1999-06-28 半導体装置の製造方法 Expired - Fee Related JP4037561B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP18187899A JP4037561B2 (ja) 1999-06-28 1999-06-28 半導体装置の製造方法
CN00122585.5A CN1199265C (zh) 1999-06-28 2000-06-28 半导体器件
US09/604,791 US6392300B1 (en) 1999-06-28 2000-06-28 Semiconductor device having an alignment mark formed on the uppermost layer of a multilayer wire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18187899A JP4037561B2 (ja) 1999-06-28 1999-06-28 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2001015403A JP2001015403A (ja) 2001-01-19
JP2001015403A5 true JP2001015403A5 (enExample) 2005-04-28
JP4037561B2 JP4037561B2 (ja) 2008-01-23

Family

ID=16108456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18187899A Expired - Fee Related JP4037561B2 (ja) 1999-06-28 1999-06-28 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US6392300B1 (enExample)
JP (1) JP4037561B2 (enExample)
CN (1) CN1199265C (enExample)

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US6784516B1 (en) * 2000-10-06 2004-08-31 International Business Machines Corporation Insulative cap for laser fusing
US6559042B2 (en) * 2001-06-28 2003-05-06 International Business Machines Corporation Process for forming fusible links
US7053495B2 (en) * 2001-09-17 2006-05-30 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit device and method for fabricating the same
US20030071323A1 (en) * 2001-10-15 2003-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic fabrication with upper lying aluminum fuse layer in copper interconnect semiconductor technology and method for fabrication thereof
KR100429881B1 (ko) * 2001-11-02 2004-05-03 삼성전자주식회사 셀 영역 위에 퓨즈 회로부가 있는 반도체 소자 및 그제조방법
KR100451506B1 (ko) * 2001-12-24 2004-10-06 주식회사 하이닉스반도체 오버레이 마크의 구조 및 형성 방법
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
TW531776B (en) * 2002-03-21 2003-05-11 Nanya Technology Corp Metal pad structure suitable for connection pad and inspection pad
TWI272641B (en) * 2002-07-16 2007-02-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells
JP4357862B2 (ja) * 2003-04-09 2009-11-04 シャープ株式会社 半導体装置
US6787443B1 (en) * 2003-05-20 2004-09-07 Intel Corporation PCB design and method for providing vented blind vias
JP2005109145A (ja) 2003-09-30 2005-04-21 Toshiba Corp 半導体装置
US6975040B2 (en) * 2003-10-28 2005-12-13 Agere Systems Inc Fabricating semiconductor chips
CN100382263C (zh) * 2004-03-05 2008-04-16 沈育浓 具有多层布线结构的半导体晶片装置及其封装方法
JP4689244B2 (ja) * 2004-11-16 2011-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US8405216B2 (en) * 2005-06-29 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for integrated circuits
JP4501806B2 (ja) * 2005-07-27 2010-07-14 株式会社デンソー 半導体装置の製造方法
JP2007123509A (ja) * 2005-10-27 2007-05-17 Seiko Epson Corp 半導体装置およびその製造方法
KR100660893B1 (ko) * 2005-11-22 2006-12-26 삼성전자주식회사 정렬 마크막을 구비하는 반도체 소자 및 그 제조 방법
KR100735757B1 (ko) * 2006-01-12 2007-07-06 삼성전자주식회사 퓨즈 영역 및 그의 제조방법
US7692230B2 (en) * 2006-12-06 2010-04-06 Taiwan Semiconductor Manufacturing Co. Ltd. MRAM cell structure
US8030733B1 (en) 2007-05-22 2011-10-04 National Semiconductor Corporation Copper-compatible fuse target
US7964934B1 (en) * 2007-05-22 2011-06-21 National Semiconductor Corporation Fuse target and method of forming the fuse target in a copper process flow
JP5064157B2 (ja) * 2007-09-18 2012-10-31 新光電気工業株式会社 半導体装置の製造方法
TWI394260B (zh) * 2007-10-31 2013-04-21 群成科技股份有限公司 具有多晶粒之半導體元件封裝結構及其方法
JP5268618B2 (ja) 2008-12-18 2013-08-21 株式会社東芝 半導体装置
US8278733B2 (en) * 2009-08-25 2012-10-02 Mediatek Inc. Bonding pad structure and integrated circuit chip using such bonding pad structure
US8896136B2 (en) 2010-06-30 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark and method of formation
CN102157497B (zh) * 2011-01-26 2016-03-09 上海华虹宏力半导体制造有限公司 多层堆栈的半导体器件的结构及形成方法
JP5953974B2 (ja) * 2011-09-15 2016-07-20 富士通セミコンダクター株式会社 半導体装置及び半導体装置の製造方法
JP2014216377A (ja) * 2013-04-23 2014-11-17 イビデン株式会社 電子部品とその製造方法及び多層プリント配線板の製造方法
CN105845659B (zh) * 2015-01-15 2019-04-26 中芯国际集成电路制造(上海)有限公司 引线焊垫结构及其形成方法
CN113394193B (zh) * 2020-03-13 2022-03-22 长鑫存储技术有限公司 半导体结构及其形成方法、激光熔丝的熔断方法
US20220254718A1 (en) * 2021-02-07 2022-08-11 Changxin Memory Technologies, Inc. Method for fusing and filling semiconductor structure, and semiconductor structure
JP7719608B2 (ja) * 2021-02-08 2025-08-06 ローム株式会社 半導体素子、当該半導体素子を備えた半導体装置、および、半導体素子の製造方法
CN115831865A (zh) * 2023-02-24 2023-03-21 广州粤芯半导体技术有限公司 一种减小晶圆标记区域电弧放电的结构及方法

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JP3512225B2 (ja) * 1994-02-28 2004-03-29 株式会社日立製作所 多層配線基板の製造方法
US5976971A (en) * 1995-07-19 1999-11-02 Ricoh Company, Ltd. Fabrication process of a semiconductor device having an interconnection structure
JP2956571B2 (ja) * 1996-03-07 1999-10-04 日本電気株式会社 半導体装置
US5783490A (en) 1997-04-21 1998-07-21 Vanguard International Semiconductor Corporation Photolithography alignment mark and manufacturing method
US5933744A (en) * 1998-04-02 1999-08-03 Taiwan Semiconductor Manufacturing Co., Ltd. Alignment method for used in chemical mechanical polishing process

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