JP2000509948A - 集積回路装置 - Google Patents
集積回路装置Info
- Publication number
- JP2000509948A JP2000509948A JP10537661A JP53766198A JP2000509948A JP 2000509948 A JP2000509948 A JP 2000509948A JP 10537661 A JP10537661 A JP 10537661A JP 53766198 A JP53766198 A JP 53766198A JP 2000509948 A JP2000509948 A JP 2000509948A
- Authority
- JP
- Japan
- Prior art keywords
- gate array
- programmable
- integrated circuit
- mask
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17768—Structural details of configuration resources for security
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17732—Macroblocks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
- H03K19/17744—Structural details of routing resources for input/output signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computer Security & Cryptography (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. 集積回路装置であって、 少なくとも1つのユーザによりプログラム可能なゲートアレイ領域と、少なく とも1つのマスクによりプログラム可能なゲートアレイ領域と、 I/Oパッドと関連する駆動回路とを有するI/Oシステムと、 少なくとも1つのユーザによりプログラム可能なゲートアレイ領域と、少なく とも1つのマスクによりプログラム可能なゲートアレイ領域と、I/Oシステム と、を選択的に接続するための、ユーザによりプログラム可能な接続構造とから 構成されることを特徴とする集積回路装置。 2. さらに、少なくとも1つのユーザによりプログラム可能なゲートアレイ領 域と、少なくとも1つのマスクによりプログラム可能なゲートアレイ領域と、の 間を接続する少なくとも1つのインターフェイス回路領域を備えることを特徴と する請求項1の集積回路装置。 3. 少なくとも1つのインターフェイス回路領域が、ユーザによりプログラム 可能であることを特徴とする請求項2の集積回路装置。 4. 複数の領域を有する集積回路装置であって、 少なくとも1つのユーザによりプログラム可能なゲートアレイ領域と、 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域と、 少なくとも1つのユーザによりプログラム可能なゲートアレイ領域と、少なく とも1つのマスクによりプログラム可能なゲートアレイ領域と、の間を接続する 少なくとも1つのインターフェイス回路領域と、 集積回路装置の入力および出力を可能とする、少なくとも1つの入力・出力領 域と、を備えることを特徴とする集積回路装置。 5. 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域が、入 力部より受信した暗号化された構成データ信号から解読された構成データ信号に 解読する少なくとも1つの解読回路を備え、少なくとも1つのユーザによりプロ グラム可能なゲートアレイ領域が、解読された構成データ信号を用いて、少なく とも1つのユーザによりプログラム可能なゲートアレイ領域にユーザのプログラ ムする機能を実行させる構成制御回路を備えることを特徴とする請求項4の集積 回路装置。 6. 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域が、少 なくとも1つのユーザによりプログラム可能なゲートアレイ領域の任意の部分を 再度プログラムする、少なくとも1つの動的な再プログラム回路を備えることを 特徴とする請求項4の集積回路装置。 7. 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域が、少 なくとも1つのユーザによりプログラム可能なゲートアレイ領域に対する組み込 み式のテストシーケンスを与える少なくとも1つの論理機能を備えることを特徴 とする請求項4の集積回路装置。 8. 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域が、外 部ユーザシステムと、少なくとも1つのユーザによりプログラム可能なゲートア レイ領域と、の間を接続する少なくとも1つのバスインターフェイス回路を備え ることを特徴とする請求項4の集積回路装置。 9. 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域が、外 部ユーザシステムと、少なくとも1つのユーザによりプログラム可能なゲートア レイ領域と、の間を接続する少なくとも1つのローカルネットワークインターフ ェイス回路を備えることを特徴とする請求項4の集積回路装置。 10. 少なくとも1つのマスクによりプログラム可能なゲートアレイ領域が、 少なくとも1つのマイクロプロセッサコントローラを備えることを特徴とする請 求項4の集積回路装置。 11. 少なくとも1つのユーザによりプログラム可能なゲートアレイ領域が、 少なくとも1つの高い論理出力数負荷を備え、少なくとも1つのマスクによりプ ログラム可能なゲートアレイ領域が、少なくとも1つの高い論理出力数負荷に接 続するために少なくとも1つの低ドライブスキュークロック駆動回路を備えるこ とを特徴とする請求項4の集積回路装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/807,455 | 1997-02-28 | ||
US08/807,455 US6150837A (en) | 1997-02-28 | 1997-02-28 | Enhanced field programmable gate array |
PCT/US1998/002280 WO1998038741A1 (en) | 1997-02-28 | 1998-02-03 | Enhanced field programmable gate array |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000509948A true JP2000509948A (ja) | 2000-08-02 |
JP3926398B2 JP3926398B2 (ja) | 2007-06-06 |
Family
ID=25196411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53766198A Expired - Lifetime JP3926398B2 (ja) | 1997-02-28 | 1998-02-03 | 集積回路装置 |
Country Status (6)
Country | Link |
---|---|
US (6) | US6150837A (ja) |
EP (5) | EP1237281A3 (ja) |
JP (1) | JP3926398B2 (ja) |
KR (1) | KR100491662B1 (ja) |
DE (2) | DE69838462T2 (ja) |
WO (1) | WO1998038741A1 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003531509A (ja) * | 1999-08-31 | 2003-10-21 | クイックロジック コーポレイション | 専用及びプログラム可能論理を有する集積回路 |
JP2007195191A (ja) * | 2006-01-19 | 2007-08-02 | Altera Corp | モジュール式i/oバンクアーキテクチャ |
JP2007522576A (ja) * | 2004-02-12 | 2007-08-09 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Io接続部を備えるデジタル信号処理集積回路 |
JP2008016663A (ja) * | 2006-07-06 | 2008-01-24 | Sharp Corp | 再構成可能な集積回路デバイス |
JP2008042936A (ja) * | 2000-10-02 | 2008-02-21 | Altera Corp | 専用プロセッサ装置を含むプログラマブルロジック集積回路装置 |
US7702884B2 (en) | 2005-01-11 | 2010-04-20 | Fujitsu Limited | Semiconductor integrated circuit with selected signal line coupling |
JP2012525706A (ja) * | 2009-05-01 | 2012-10-22 | アルテラ コーポレイション | 埋め込みデジタルストリップチップ |
WO2020144758A1 (ja) * | 2019-01-09 | 2020-07-16 | 三菱電機株式会社 | 秘密計算装置及びクライアント装置 |
Families Citing this family (130)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
DE19651075A1 (de) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen |
DE19654595A1 (de) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen |
DE19654846A1 (de) | 1996-12-27 | 1998-07-09 | Pact Inf Tech Gmbh | Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.) |
DE59710317D1 (de) | 1996-12-27 | 2003-07-24 | Pact Inf Tech Gmbh | VERFAHREN ZUM SELBSTÄNDIGEN DYNAMISCHEN UMLADEN VON DATENFLUSSPROZESSOREN (DFPs) SOWIE BAUSTEINEN MIT ZWEI- ODER MEHRDIMENSIONALEN PROGRAMMIERBAREN ZELLSTRUKTUREN (FPGAs, DPGAs, o.dgl.) |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US5874834A (en) * | 1997-03-04 | 1999-02-23 | Xilinx, Inc. | Field programmable gate array with distributed gate-array functionality |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (de) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Verfahren zur Reparatur von integrierten Schaltkreisen |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US6356637B1 (en) * | 1998-09-18 | 2002-03-12 | Sun Microsystems, Inc. | Field programmable gate arrays |
US6311316B1 (en) * | 1998-12-14 | 2001-10-30 | Clear Logic, Inc. | Designing integrated circuit gate arrays using programmable logic device bitstreams |
US6762621B1 (en) | 1998-12-31 | 2004-07-13 | Actel Corporation | Programmable multi-standard I/O architecture for FPGAs |
US6366120B1 (en) * | 1999-03-04 | 2002-04-02 | Altera Corporation | Interconnection resources for programmable logic integrated circuit devices |
JP2003505753A (ja) | 1999-06-10 | 2003-02-12 | ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング | セル構造におけるシーケンス分割方法 |
US6625787B1 (en) * | 1999-08-13 | 2003-09-23 | Xilinx, Inc. | Method and apparatus for timing management in a converted design |
WO2001037154A1 (en) * | 1999-11-16 | 2001-05-25 | Aladdin Knowledge Systems Ltd. | Preventing unauthorized use of active content generator software |
US6519753B1 (en) | 1999-11-30 | 2003-02-11 | Quicklogic Corporation | Programmable device with an embedded portion for receiving a standard circuit design |
US6769109B2 (en) | 2000-02-25 | 2004-07-27 | Lightspeed Semiconductor Corporation | Programmable logic array embedded in mask-programmed ASIC |
US6694491B1 (en) | 2000-02-25 | 2004-02-17 | Lightspeed Semiconductor Corporation | Programmable logic array embedded in mask-programmed ASIC |
US6803785B1 (en) * | 2000-06-12 | 2004-10-12 | Altera Corporation | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
ATE476700T1 (de) | 2000-06-13 | 2010-08-15 | Richter Thomas | Pipeline ct-protokolle und -kommunikation |
DE60040064D1 (de) * | 2000-07-04 | 2008-10-09 | Sun Microsystems Inc | Anwenderprogrammierbare Gatterfelder (FPGA) und Verfahren zur Bearbeitung von FPGA-Konfigurationsdaten |
US6476636B1 (en) | 2000-09-02 | 2002-11-05 | Actel Corporation | Tileable field-programmable gate array architecture |
US7055125B2 (en) | 2000-09-08 | 2006-05-30 | Lightspeed Semiconductor Corp. | Depopulated programmable logic array |
US6628140B2 (en) | 2000-09-18 | 2003-09-30 | Altera Corporation | Programmable logic devices with function-specific blocks |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US7024653B1 (en) * | 2000-10-30 | 2006-04-04 | Cypress Semiconductor Corporation | Architecture for efficient implementation of serial data communication functions on a programmable logic device (PLD) |
US7380131B1 (en) | 2001-01-19 | 2008-05-27 | Xilinx, Inc. | Copy protection without non-volatile memory |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US6650140B2 (en) * | 2001-03-19 | 2003-11-18 | Altera Corporation | Programmable logic device with high speed serial interface circuitry |
US6605962B2 (en) * | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
JP3485106B2 (ja) * | 2001-05-11 | 2004-01-13 | セイコーエプソン株式会社 | 集積回路装置 |
JP2002368727A (ja) * | 2001-06-04 | 2002-12-20 | Nec Corp | 半導体集積回路 |
GB2376321B (en) * | 2001-06-08 | 2005-04-20 | Hewlett Packard Co | Electronic interface device |
AU2002347560A1 (en) | 2001-06-20 | 2003-01-02 | Pact Xpp Technologies Ag | Data processing method |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US6633182B2 (en) | 2001-09-05 | 2003-10-14 | Carnegie Mellon University | Programmable gate array based on configurable metal interconnect vias |
US7191339B1 (en) * | 2001-09-10 | 2007-03-13 | Xilinx, Inc. | System and method for using a PLD identification code |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US6646466B1 (en) * | 2001-12-05 | 2003-11-11 | Cypress Semiconductor Corp. | Interface scheme for connecting a fixed circuitry block to a programmable logic core |
US6747479B1 (en) * | 2001-12-05 | 2004-06-08 | Cypress Semiconductor Corp. | Interface scheme for connecting a fixed circuitry block to a programmable logic core |
WO2003060747A2 (de) | 2002-01-19 | 2003-07-24 | Pact Xpp Technologies Ag | Reconfigurierbarer prozessor |
ATE538439T1 (de) | 2002-02-18 | 2012-01-15 | Richter Thomas | Bussysteme und rekonfigurationsverfahren |
US7187709B1 (en) * | 2002-03-01 | 2007-03-06 | Xilinx, Inc. | High speed configurable transceiver architecture |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US6886143B1 (en) * | 2002-03-29 | 2005-04-26 | Altera Corporation | Method and apparatus for providing clock/buffer network in mask-programmable logic device |
US6693454B2 (en) * | 2002-05-17 | 2004-02-17 | Viasic, Inc. | Distributed RAM in a logic array |
US6873185B2 (en) * | 2002-06-19 | 2005-03-29 | Viasic, Inc. | Logic array devices having complex macro-cell architecture and methods facilitating use of same |
WO2004021176A2 (de) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Verfahren und vorrichtung zur datenverarbeitung |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
US7202908B2 (en) * | 2002-09-04 | 2007-04-10 | Darien K. Wallace | Deinterlacer using both low angle and high angle spatial interpolation |
US7346876B2 (en) * | 2002-09-04 | 2008-03-18 | Darien K. Wallace | ASIC having dense mask-programmable portion and related system development method |
US7782398B2 (en) * | 2002-09-04 | 2010-08-24 | Chan Thomas M | Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions |
US7480010B2 (en) * | 2002-09-04 | 2009-01-20 | Denace Enterprise Co., L.L.C. | Customizable ASIC with substantially non-customizable portion that supplies pixel data to a mask-programmable portion in multiple color space formats |
JP4388895B2 (ja) | 2002-09-06 | 2009-12-24 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | リコンフィギュアラブルなシーケンサ構造 |
US20040267520A1 (en) * | 2003-06-27 | 2004-12-30 | Roderick Holley | Audio playback/recording integrated circuit with filter co-processor |
US8352724B2 (en) * | 2003-07-23 | 2013-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Microprocessor and grid computing system |
US7521960B2 (en) * | 2003-07-31 | 2009-04-21 | Actel Corporation | Integrated circuit including programmable logic and external-device chip-enable override control |
US7170315B2 (en) * | 2003-07-31 | 2007-01-30 | Actel Corporation | Programmable system on a chip |
US6990010B1 (en) | 2003-08-06 | 2006-01-24 | Actel Corporation | Deglitching circuits for a radiation-hardened static random access memory based programmable architecture |
EP1676208A2 (en) | 2003-08-28 | 2006-07-05 | PACT XPP Technologies AG | Data processing device and method |
US7112991B1 (en) * | 2003-12-24 | 2006-09-26 | Altera Corporation | Extended custom instructions |
US7081771B2 (en) * | 2004-02-20 | 2006-07-25 | Lattice Semiconductor Corporation | Upgradeable and reconfigurable programmable logic device |
CA2462497A1 (en) * | 2004-03-30 | 2005-09-30 | Dspfactory Ltd. | Method and system for data logging in a listening device |
US7138824B1 (en) | 2004-05-10 | 2006-11-21 | Actel Corporation | Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks |
US7478355B2 (en) * | 2004-05-21 | 2009-01-13 | United Microelectronics Corp. | Input/output circuits with programmable option and related method |
US7135888B1 (en) * | 2004-07-22 | 2006-11-14 | Altera Corporation | Programmable routing structures providing shorter timing delays for input/output signals |
US8566616B1 (en) * | 2004-09-10 | 2013-10-22 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like |
US20060080632A1 (en) * | 2004-09-30 | 2006-04-13 | Mathstar, Inc. | Integrated circuit layout having rectilinear structure of objects |
US7334208B1 (en) | 2004-11-09 | 2008-02-19 | Viasic, Inc. | Customization of structured ASIC devices using pre-process extraction of routing information |
US7116181B2 (en) * | 2004-12-21 | 2006-10-03 | Actel Corporation | Voltage- and temperature-compensated RC oscillator circuit |
US7119398B1 (en) | 2004-12-22 | 2006-10-10 | Actel Corporation | Power-up and power-down circuit for system-on-a-chip integrated circuit |
US7446378B2 (en) | 2004-12-29 | 2008-11-04 | Actel Corporation | ESD protection structure for I/O pad subject to both positive and negative voltages |
US7627291B1 (en) * | 2005-01-21 | 2009-12-01 | Xilinx, Inc. | Integrated circuit having a routing element selectively operable to function as an antenna |
US7919979B1 (en) * | 2005-01-21 | 2011-04-05 | Actel Corporation | Field programmable gate array including a non-volatile user memory and method for programming |
US20070247189A1 (en) * | 2005-01-25 | 2007-10-25 | Mathstar | Field programmable semiconductor object array integrated circuit |
JPWO2006115212A1 (ja) * | 2005-04-21 | 2008-12-18 | 松下電器産業株式会社 | アルゴリズム更新システム |
US7716497B1 (en) | 2005-06-14 | 2010-05-11 | Xilinx, Inc. | Bitstream protection without key storage |
US7653448B2 (en) * | 2005-09-30 | 2010-01-26 | Freescale Semiconductor, Inc. | NICAM processing method |
JP5140594B2 (ja) * | 2005-09-30 | 2013-02-06 | フリースケール セミコンダクター インコーポレイテッド | Nicam処理方法 |
US7538574B1 (en) | 2005-12-05 | 2009-05-26 | Lattice Semiconductor Corporation | Transparent field reconfiguration for programmable logic devices |
WO2007082730A1 (de) | 2006-01-18 | 2007-07-26 | Pact Xpp Technologies Ag | Hardwaredefinitionsverfahren |
US7375549B1 (en) | 2006-02-09 | 2008-05-20 | Lattice Semiconductor Corporation | Reconfiguration of programmable logic devices |
US20070203596A1 (en) * | 2006-02-28 | 2007-08-30 | Accel Semiconductor Corporation | Fm transmission |
US7459931B1 (en) | 2006-04-05 | 2008-12-02 | Lattice Semiconductor Corporation | Programmable logic devices with transparent field reconfiguration |
US7554358B1 (en) | 2006-04-05 | 2009-06-30 | Lattice Semiconductor Corporation | Programmable logic devices with user non-volatile memory |
US7570078B1 (en) | 2006-06-02 | 2009-08-04 | Lattice Semiconductor Corporation | Programmable logic device providing serial peripheral interfaces |
US7378873B1 (en) | 2006-06-02 | 2008-05-27 | Lattice Semiconductor Corporation | Programmable logic device providing a serial peripheral interface |
US7495970B1 (en) | 2006-06-02 | 2009-02-24 | Lattice Semiconductor Corporation | Flexible memory architectures for programmable logic devices |
JP4932369B2 (ja) * | 2006-07-27 | 2012-05-16 | ローム株式会社 | 音声信号増幅回路およびそれを用いたオーディオ装置ならびにボリウム切換方法 |
US7378874B2 (en) * | 2006-08-31 | 2008-05-27 | Viasic, Inc. | Creating high-drive logic devices from standard gates with minimal use of custom masks |
US8018248B2 (en) | 2006-09-21 | 2011-09-13 | Quicklogic Corporation | Adjustable interface buffer circuit between a programmable logic device and a dedicated device |
US8386553B1 (en) | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
US7930336B2 (en) | 2006-12-05 | 2011-04-19 | Altera Corporation | Large multiplier for programmable logic device |
US7456653B2 (en) | 2007-03-09 | 2008-11-25 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
US7508231B2 (en) | 2007-03-09 | 2009-03-24 | Altera Corporation | Programmable logic device having redundancy with logic element granularity |
US7692309B2 (en) * | 2007-09-06 | 2010-04-06 | Viasic, Inc. | Configuring structured ASIC fabric using two non-adjacent via layers |
US20090144595A1 (en) * | 2007-11-30 | 2009-06-04 | Mathstar, Inc. | Built-in self-testing (bist) of field programmable object arrays |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8244789B1 (en) | 2008-03-14 | 2012-08-14 | Altera Corporation | Normalization of floating point operations in a programmable integrated circuit device |
US8886696B1 (en) | 2009-03-03 | 2014-11-11 | Altera Corporation | Digital signal processing circuitry with redundancy and ability to support larger multipliers |
US8547135B1 (en) * | 2009-08-28 | 2013-10-01 | Cypress Semiconductor Corporation | Self-modulated voltage reference |
US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
DE102010033780A1 (de) | 2010-08-09 | 2012-02-09 | Volkswagen Ag | Integrierte Schaltungseinheit |
US8418006B1 (en) | 2010-12-07 | 2013-04-09 | Xilinx, Inc. | Protecting a design for an integrated circuit using a unique identifier |
US8386990B1 (en) | 2010-12-07 | 2013-02-26 | Xilinx, Inc. | Unique identifier derived from an intrinsic characteristic of an integrated circuit |
US8427193B1 (en) | 2010-12-07 | 2013-04-23 | Xilinx, Inc. | Intellectual property core protection for integrated circuits |
US8686753B1 (en) * | 2011-04-08 | 2014-04-01 | Altera Corporation | Partial reconfiguration and in-system debugging |
US9600278B1 (en) | 2011-05-09 | 2017-03-21 | Altera Corporation | Programmable device using fixed and configurable logic to implement recursive trees |
US9053045B1 (en) | 2011-09-16 | 2015-06-09 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
US9007243B2 (en) * | 2012-09-05 | 2015-04-14 | IQ-Analog Corporation | System and method for customizing data converters from universal function dice |
US9553590B1 (en) | 2012-10-29 | 2017-01-24 | Altera Corporation | Configuring programmable integrated circuit device resources as processing elements |
US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
US9379687B1 (en) | 2014-01-14 | 2016-06-28 | Altera Corporation | Pipelined systolic finite impulse response filter |
US9634667B2 (en) | 2014-08-29 | 2017-04-25 | Cypress Semiconductor Corporation | Integrated circuit device with programmable analog subsystem |
US9473144B1 (en) | 2014-11-25 | 2016-10-18 | Cypress Semiconductor Corporation | Integrated circuit device with programmable analog subsystem |
US10452392B1 (en) | 2015-01-20 | 2019-10-22 | Altera Corporation | Configuring programmable integrated circuit device resources as processors |
US9684488B2 (en) | 2015-03-26 | 2017-06-20 | Altera Corporation | Combined adder and pre-adder for high-radix multiplier circuit |
US10942706B2 (en) | 2017-05-05 | 2021-03-09 | Intel Corporation | Implementation of floating-point trigonometric functions in an integrated circuit device |
Family Cites Families (209)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4195352A (en) * | 1977-07-08 | 1980-03-25 | Xerox Corporation | Split programmable logic array |
US4415818A (en) | 1979-01-16 | 1983-11-15 | Nippon Telegraph & Telephone Corp. | Programmable sequential logic circuit devices |
WO1982002640A1 (en) | 1981-01-16 | 1982-08-05 | Robert Royce Johnson | Universal interconnection substrate |
US4458163A (en) * | 1981-07-20 | 1984-07-03 | Texas Instruments Incorporated | Programmable architecture logic |
US4527115A (en) * | 1982-12-22 | 1985-07-02 | Raytheon Company | Configurable logic gate array |
JPS6050940A (ja) * | 1983-08-31 | 1985-03-22 | Toshiba Corp | 半導体集積回路 |
US4870302A (en) | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4713792A (en) * | 1985-06-06 | 1987-12-15 | Altera Corporation | Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits |
US4774421A (en) * | 1984-05-03 | 1988-09-27 | Altera Corporation | Programmable logic array device using EPROM technology |
US4803162A (en) | 1984-05-15 | 1989-02-07 | Fluorodiagnostic Limited Partners | Composition, article and process for detecting a microorganism |
US4609986A (en) * | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
US4684830A (en) * | 1985-03-22 | 1987-08-04 | Monolithic Memories, Inc. | Output circuit for a programmable logic array |
US4933577A (en) * | 1985-03-22 | 1990-06-12 | Advanced Micro Devices, Inc. | Output circuit for a programmable logic array |
US4963768A (en) * | 1985-03-29 | 1990-10-16 | Advanced Micro Devices, Inc. | Flexible, programmable cell array interconnected by a programmable switch matrix |
US4742252A (en) * | 1985-03-29 | 1988-05-03 | Advanced Micro Devices, Inc. | Multiple array customizable logic device |
US5225719A (en) * | 1985-03-29 | 1993-07-06 | Advanced Micro Devices, Inc. | Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix |
US5151623A (en) * | 1985-03-29 | 1992-09-29 | Advanced Micro Devices, Inc. | Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix |
US4677318A (en) * | 1985-04-12 | 1987-06-30 | Altera Corporation | Programmable logic storage element for programmable logic devices |
US4691161A (en) * | 1985-06-13 | 1987-09-01 | Raytheon Company | Configurable logic gate array |
US4718057A (en) * | 1985-08-30 | 1988-01-05 | Advanced Micro Devices, Inc. | Streamlined digital signal processor |
US4638187A (en) * | 1985-10-01 | 1987-01-20 | Vtc Incorporated | CMOS output buffer providing high drive current with minimum output signal distortion |
US4771285A (en) * | 1985-11-05 | 1988-09-13 | Advanced Micro Devices, Inc. | Programmable logic cell with flexible clocking and flexible feedback |
US4758747A (en) * | 1986-05-30 | 1988-07-19 | Advanced Micro Devices, Inc. | Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor |
JP2546228B2 (ja) * | 1985-12-20 | 1996-10-23 | 株式会社日立製作所 | 選択回路 |
US4772811A (en) * | 1986-07-04 | 1988-09-20 | Ricoh Company, Ltd. | Programmable logic device |
US4857774A (en) * | 1986-09-19 | 1989-08-15 | Actel Corporation | Testing apparatus and diagnostic method for use with programmable interconnect architecture |
US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US4758745B1 (en) * | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
US5172014A (en) * | 1986-09-19 | 1992-12-15 | Actel Corporation | Programmable interconnect architecture |
US5187393A (en) * | 1986-09-19 | 1993-02-16 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5015885A (en) * | 1986-09-19 | 1991-05-14 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5367208A (en) * | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US4721868A (en) * | 1986-09-23 | 1988-01-26 | Advanced Micro Devices, Inc. | IC input circuitry programmable for realizing multiple functions from a single input |
US4983959A (en) * | 1986-10-01 | 1991-01-08 | Texas Instruments Incorporated | Logic output macrocell |
US4969121A (en) * | 1987-03-02 | 1990-11-06 | Altera Corporation | Programmable integrated circuit logic array device having improved microprocessor connectability |
US4783606A (en) * | 1987-04-14 | 1988-11-08 | Erich Goetting | Programming circuit for programmable logic array I/O cell |
US4928023A (en) * | 1987-08-27 | 1990-05-22 | Texas Instruments Incorporated | Improved output buffer having reduced noise characteristics |
US5165166A (en) * | 1987-09-29 | 1992-11-24 | Microelectronics And Computer Technology Corporation | Method of making a customizable circuitry |
US5068603A (en) * | 1987-10-07 | 1991-11-26 | Xilinx, Inc. | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
US4847612A (en) * | 1988-01-13 | 1989-07-11 | Plug Logic, Inc. | Programmable logic device |
US5023484A (en) * | 1988-09-02 | 1991-06-11 | Cypress Semiconductor Corporation | Architecture of high speed synchronous state machine |
US4987319A (en) | 1988-09-08 | 1991-01-22 | Kawasaki Steel Corporation | Programmable input/output circuit and programmable logic device |
IT1225638B (it) * | 1988-12-28 | 1990-11-22 | Sgs Thomson Microelectronics | Dispositivo logico integrato come una rete di maglie di memorie distribuite |
US4912345A (en) * | 1988-12-29 | 1990-03-27 | Sgs-Thomson Microelectronics, Inc. | Programmable summing functions for programmable logic devices |
US4930097A (en) * | 1988-12-30 | 1990-05-29 | Intel Corporation | Architecture for an improved performance of a programmable logic device |
US5083293A (en) * | 1989-01-12 | 1992-01-21 | General Instrument Corporation | Prevention of alteration of data stored in secure integrated circuit chip memory |
US4933898A (en) * | 1989-01-12 | 1990-06-12 | General Instrument Corporation | Secure integrated circuit chip with conductive shield |
US4952934A (en) * | 1989-01-25 | 1990-08-28 | Sgs-Thomson Microelectronics S.R.L. | Field programmable logic and analogic integrated circuit |
US4940909A (en) * | 1989-05-12 | 1990-07-10 | Plus Logic, Inc. | Configuration control circuit for programmable logic devices |
US5343406A (en) * | 1989-07-28 | 1994-08-30 | Xilinx, Inc. | Distributed memory architecture for a configurable logic array and method for using distributed memory |
US5489857A (en) | 1992-08-03 | 1996-02-06 | Advanced Micro Devices, Inc. | Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
US5212652A (en) | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
US5231588A (en) * | 1989-08-15 | 1993-07-27 | Advanced Micro Devices, Inc. | Programmable gate array with logic cells having symmetrical input/output structures |
US5457409A (en) | 1992-08-03 | 1995-10-10 | Advanced Micro Devices, Inc. | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices |
US5644496A (en) | 1989-08-15 | 1997-07-01 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5377124A (en) | 1989-09-20 | 1994-12-27 | Aptix Corporation | Field programmable printed circuit board |
US5027011A (en) * | 1989-10-31 | 1991-06-25 | Sgs-Thomson Microelectronics, Inc. | Input row drivers for programmable logic devices |
US4978905A (en) * | 1989-10-31 | 1990-12-18 | Cypress Semiconductor Corp. | Noise reduction output buffer |
US5448493A (en) * | 1989-12-20 | 1995-09-05 | Xilinx, Inc. | Structure and method for manually controlling automatic configuration in an integrated circuit logic block array |
US5028821A (en) * | 1990-03-01 | 1991-07-02 | Plus Logic, Inc. | Programmable logic device with programmable inverters at input/output pads |
DE4008791A1 (de) * | 1990-03-19 | 1991-09-26 | Slt Lining Technology Gmbh | Anordnung zur abdeckung geneigter schuettstoffflaechen |
US5140193A (en) * | 1990-03-27 | 1992-08-18 | Xilinx, Inc. | Programmable connector for programmable logic device |
US5198705A (en) * | 1990-05-11 | 1993-03-30 | Actel Corporation | Logic module with configurable combinational and sequential blocks |
US5045726A (en) * | 1990-05-16 | 1991-09-03 | North American Philips Corporation | Low power programming circuit for user programmable digital logic array |
US5085885A (en) * | 1990-09-10 | 1992-02-04 | University Of Delaware | Plasma-induced, in-situ generation, transport and use or collection of reactive precursors |
DE69133311T2 (de) | 1990-10-15 | 2004-06-24 | Aptix Corp., San Jose | Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung |
JPH0714024B2 (ja) * | 1990-11-29 | 1995-02-15 | 川崎製鉄株式会社 | マルチチップモジュール |
US5166557A (en) * | 1991-01-02 | 1992-11-24 | Texas Instruments Incorporated | Gate array with built-in programming circuitry |
US5107146A (en) | 1991-02-13 | 1992-04-21 | Actel Corporation | Mixed mode analog/digital programmable interconnect architecture |
US5416367A (en) | 1991-03-06 | 1995-05-16 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
US5220213A (en) * | 1991-03-06 | 1993-06-15 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
US5313119A (en) * | 1991-03-18 | 1994-05-17 | Crosspoint Solutions, Inc. | Field programmable gate array |
US5384499A (en) | 1991-04-25 | 1995-01-24 | Altera Corporation | High-density erasable programmable logic device architecture using multiplexer interconnections |
US5701027A (en) | 1991-04-26 | 1997-12-23 | Quicklogic Corporation | Programmable interconnect structures and programmable integrated circuits |
US5557136A (en) | 1991-04-26 | 1996-09-17 | Quicklogic Corporation | Programmable interconnect structures and programmable integrated circuits |
US5191242A (en) * | 1991-05-17 | 1993-03-02 | Advanced Micro Devices, Inc. | Programmable logic device incorporating digital-to-analog converter |
US5153462A (en) * | 1991-05-21 | 1992-10-06 | Advanced Micro Devices, Inc. | Programmable logic device incorporating voltage comparator |
EP0518701A3 (en) | 1991-06-14 | 1993-04-21 | Aptix Corporation | Field programmable circuit module |
US5221865A (en) * | 1991-06-21 | 1993-06-22 | Crosspoint Solutions, Inc. | Programmable input/output buffer circuit with test capability |
US5187392A (en) * | 1991-07-31 | 1993-02-16 | Intel Corporation | Programmable logic device with limited signal swing |
US5317209A (en) * | 1991-08-29 | 1994-05-31 | National Semiconductor Corporation | Dynamic three-state bussing capability in a configurable logic array |
US5633830A (en) | 1995-11-08 | 1997-05-27 | Altera Corporation | Random access memory block circuitry for programmable logic array integrated circuit devices |
US5260610A (en) | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic element interconnections for programmable logic array integrated circuits |
US5883850A (en) | 1991-09-03 | 1999-03-16 | Altera Corporation | Programmable logic array integrated circuits |
US5550782A (en) | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
US5576554A (en) | 1991-11-05 | 1996-11-19 | Monolithic System Technology, Inc. | Wafer-scale integrated circuit interconnect structure architecture |
EP0541288B1 (en) * | 1991-11-05 | 1998-07-08 | Fu-Chieh Hsu | Circuit module redundacy architecture |
JPH07502377A (ja) * | 1991-12-18 | 1995-03-09 | クロスポイント・ソルーションズ・インコーポレイテッド | フィールドプログラマブルゲートアレイのための拡張アーキテクチャ |
US5208491A (en) * | 1992-01-07 | 1993-05-04 | Washington Research Foundation | Field programmable gate array |
US5254886A (en) * | 1992-06-19 | 1993-10-19 | Actel Corporation | Clock distribution scheme for user-programmable logic array architecture |
US5646547A (en) | 1994-04-28 | 1997-07-08 | Xilinx, Inc. | Logic cell which can be configured as a latch without static one's problem |
DE69304471T2 (de) | 1992-08-03 | 1997-03-20 | Advanced Micro Devices Inc | Programmierbare logische Vorrichtung |
US5490042A (en) * | 1992-08-10 | 1996-02-06 | Environmental Research Institute Of Michigan | Programmable silicon circuit board |
AU4798793A (en) | 1992-08-10 | 1994-03-03 | Monolithic System Technology, Inc. | Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration |
US5317698A (en) | 1992-08-18 | 1994-05-31 | Actel Corporation | FPGA architecture including direct logic function circuit to I/O interconnections |
US5404033A (en) * | 1992-08-20 | 1995-04-04 | Swift Microelectronics Corporation | Application specific integrated circuit and placement and routing software with non-customizable first metal layer and vias and customizable second metal grid pattern |
US5432388A (en) | 1992-08-27 | 1995-07-11 | At&T Global Information Solutions Company | Repeatedly programmable logic array using dynamic access memory |
US5432708A (en) | 1992-10-08 | 1995-07-11 | Aptix Corporation | Multichip module integrated circuit device having maximum input/output capability |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
US5452229A (en) * | 1992-12-18 | 1995-09-19 | Lattice Semiconductor Corporation | Programmable integrated-circuit switch |
US5414638A (en) * | 1992-12-18 | 1995-05-09 | Aptix Corporation | Programmable interconnect architecture |
US5301143A (en) * | 1992-12-31 | 1994-04-05 | Micron Semiconductor, Inc. | Method for identifying a semiconductor die using an IC with programmable links |
US5357153A (en) | 1993-01-28 | 1994-10-18 | Xilinx, Inc. | Macrocell with product-term cascade and improved flip flop utilization |
US5424589A (en) * | 1993-02-12 | 1995-06-13 | The Board Of Trustees Of The Leland Stanford Junior University | Electrically programmable inter-chip interconnect architecture |
GB9303084D0 (en) | 1993-02-16 | 1993-03-31 | Inmos Ltd | Programmable logic circuit |
JPH06243677A (ja) | 1993-02-19 | 1994-09-02 | Hitachi Ltd | 半導体記憶装置とメモリ装置及びその品種設定方法 |
US5329181A (en) * | 1993-03-05 | 1994-07-12 | Xilinx, Inc. | Complementary macrocell feedback circuit |
US5550839A (en) | 1993-03-12 | 1996-08-27 | Xilinx, Inc. | Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays |
US5317212A (en) * | 1993-03-19 | 1994-05-31 | Wahlstrom Sven E | Dynamic control of configurable logic |
JPH06275718A (ja) * | 1993-03-19 | 1994-09-30 | Toshiba Corp | ゲートアレイ回路 |
US5311080A (en) | 1993-03-26 | 1994-05-10 | At&T Bell Laboratories | Field programmable gate array with direct input/output connection |
US5349249A (en) * | 1993-04-07 | 1994-09-20 | Xilinx, Inc. | Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading |
US5381058A (en) * | 1993-05-21 | 1995-01-10 | At&T Corp. | FPGA having PFU with programmable output driver inputs |
US5444394A (en) * | 1993-07-08 | 1995-08-22 | Altera Corporation | PLD with selective inputs from local and global conductors |
US5402014A (en) * | 1993-07-14 | 1995-03-28 | Waferscale Integration, Inc. | Peripheral port with volatile and non-volatile configuration |
US5447167A (en) * | 1993-07-27 | 1995-09-05 | Fleischaker; William J. | Hand pressure level threshold sensor |
JP3708541B2 (ja) | 1993-08-03 | 2005-10-19 | ザイリンクス, インコーポレイテッド | マイクロプロセサをベースとしたfpga |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US5457644A (en) | 1993-08-20 | 1995-10-10 | Actel Corporation | Field programmable digital signal processing array integrated circuit |
US5488317A (en) * | 1993-10-22 | 1996-01-30 | Texas Instruments Incorporated | Wired logic functions on FPGA's |
US5563592A (en) | 1993-11-22 | 1996-10-08 | Altera Corporation | Programmable logic device having a compressed configuration file and associated decompression |
US5394031A (en) * | 1993-12-08 | 1995-02-28 | At&T Corp. | Apparatus and method to improve programming speed of field programmable gate arrays |
EP0734573B1 (en) * | 1993-12-13 | 2002-04-03 | Lattice Semiconductor Corporation | Application specific modules in a programmable logic device |
US5563526A (en) | 1994-01-03 | 1996-10-08 | Texas Instruments Incorporated | Programmable mixed-mode integrated circuit architecture |
US5742179A (en) | 1994-01-27 | 1998-04-21 | Dyna Logic Corporation | High speed programmable logic architecture |
US5572409A (en) | 1994-02-08 | 1996-11-05 | Prolinx Labs Corporation | Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board |
US5590305A (en) | 1994-03-28 | 1996-12-31 | Altera Corporation | Programming circuits and techniques for programming logic |
US5504439A (en) | 1994-04-01 | 1996-04-02 | Xilinx, Inc. | I/O interface cell for use with optional pad |
US5469473A (en) | 1994-04-15 | 1995-11-21 | Texas Instruments Incorporated | Transceiver circuit with transition detection |
US5426378A (en) * | 1994-04-20 | 1995-06-20 | Xilinx, Inc. | Programmable logic device which stores more than one configuration and means for switching configurations |
US5689195A (en) | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
US5424655A (en) | 1994-05-20 | 1995-06-13 | Quicklogic Corporation | Programmable application specific integrated circuit employing antifuses and methods therefor |
US5600267A (en) | 1994-06-24 | 1997-02-04 | Cypress Semiconductor Corporation | Apparatus for a programmable CML to CMOS translator for power/speed adjustment |
US5426379A (en) * | 1994-07-29 | 1995-06-20 | Xilinx, Inc. | Field programmable gate array with built-in bitstream data expansion |
US5559465A (en) | 1994-07-29 | 1996-09-24 | Cypress Semiconductor Corporation | Output preconditioning circuit with an output level latch and a clamp |
JPH0869447A (ja) | 1994-08-31 | 1996-03-12 | Toshiba Corp | データ処理装置 |
US5548228A (en) | 1994-09-28 | 1996-08-20 | Altera Corporation | Reconfigurable programmable logic device having static and non-volatile memory |
US5606266A (en) | 1994-11-04 | 1997-02-25 | Altera Corporation | Programmable logic array integrated circuits with enhanced output routing |
US5559447A (en) | 1994-11-17 | 1996-09-24 | Cypress Semiconductor | Output buffer with variable output impedance |
US5583749A (en) | 1994-11-30 | 1996-12-10 | Altera Corporation | Baseboard and daughtercard apparatus for reconfigurable computing systems |
US5577050A (en) | 1994-12-28 | 1996-11-19 | Lsi Logic Corporation | Method and apparatus for configurable build-in self-repairing of ASIC memories design |
US5581199A (en) | 1995-01-04 | 1996-12-03 | Xilinx, Inc. | Interconnect architecture for field programmable gate array using variable length conductors |
GB2297409B (en) | 1995-01-27 | 1998-08-19 | Altera Corp | Programmable logic devices |
US5493239A (en) * | 1995-01-31 | 1996-02-20 | Motorola, Inc. | Circuit and method of configuring a field programmable gate array |
US5566123A (en) | 1995-02-10 | 1996-10-15 | Xilinx, Inc. | Synchronous dual port ram |
US5537341A (en) | 1995-02-10 | 1996-07-16 | Jonathan Rose | Complementary architecture for field-programmable gate arrays |
US5642262A (en) | 1995-02-23 | 1997-06-24 | Altera Corporation | High-density programmable logic device in a multi-chip module package with improved interconnect scheme |
US5581198A (en) | 1995-02-24 | 1996-12-03 | Xilinx, Inc. | Shadow DRAM for programmable logic devices |
US5847577A (en) | 1995-02-24 | 1998-12-08 | Xilinx, Inc. | DRAM memory cell for programmable logic devices |
US5570040A (en) | 1995-03-22 | 1996-10-29 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US5572148A (en) | 1995-03-22 | 1996-11-05 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US5751162A (en) | 1995-04-06 | 1998-05-12 | Texas Instruments Incorporated | Field programmable gate array logic module configurable as combinational or sequential circuits |
US5530378A (en) | 1995-04-26 | 1996-06-25 | Xilinx, Inc. | Cross point interconnect structure with reduced area |
US5563528A (en) | 1995-05-02 | 1996-10-08 | Xilinx, Inc. | Multiplexer for programmable logic device |
US5600597A (en) | 1995-05-02 | 1997-02-04 | Xilinx, Inc. | Register protection structure for FPGA |
US5850564A (en) | 1995-05-03 | 1998-12-15 | Btr, Inc, | Scalable multiple level tab oriented interconnect architecture |
US5543730A (en) | 1995-05-17 | 1996-08-06 | Altera Corporation | Techniques for programming programmable logic array devices |
US5625301A (en) | 1995-05-18 | 1997-04-29 | Actel Corporation | Flexible FPGA input/output architecture |
US5640106A (en) | 1995-05-26 | 1997-06-17 | Xilinx, Inc. | Method and structure for loading data into several IC devices |
US5671432A (en) | 1995-06-02 | 1997-09-23 | International Business Machines Corporation | Programmable array I/O-routing resource |
US5652529A (en) | 1995-06-02 | 1997-07-29 | International Business Machines Corporation | Programmable array clock/reset resource |
US5521529A (en) | 1995-06-02 | 1996-05-28 | Advanced Micro Devices, Inc. | Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation |
US5646546A (en) | 1995-06-02 | 1997-07-08 | International Business Machines Corporation | Programmable logic cell having configurable gates and multiplexers |
US5646544A (en) | 1995-06-05 | 1997-07-08 | International Business Machines Corporation | System and method for dynamically reconfiguring a programmable gate array |
US5568081A (en) | 1995-06-07 | 1996-10-22 | Cypress Semiconductor, Corporation | Variable slew control for output buffers |
JP3736855B2 (ja) | 1995-07-10 | 2006-01-18 | ジーリンクス インコーポレイテッド | フィールドプログラマブル・ゲートアレイ及びインテリジェント・メモリを含んでいるシステム |
US5559450A (en) | 1995-07-27 | 1996-09-24 | Lucent Technologies Inc. | Field programmable gate array with multi-port RAM |
US5754826A (en) * | 1995-08-04 | 1998-05-19 | Synopsys, Inc. | CAD and simulation system for targeting IC designs to multiple fabrication processes |
US5581501A (en) | 1995-08-17 | 1996-12-03 | Altera Corporation | Nonvolatile SRAM cells and cell arrays |
US5838954A (en) | 1995-08-18 | 1998-11-17 | Xilinx, Inc. | Computer-implemented method of optimizing a time multiplexed programmable logic device |
US5646545A (en) | 1995-08-18 | 1997-07-08 | Xilinx, Inc. | Time multiplexed programmable logic device |
US5583450A (en) | 1995-08-18 | 1996-12-10 | Xilinx, Inc. | Sequencer for a time multiplexed programmable logic device |
US5600263A (en) | 1995-08-18 | 1997-02-04 | Xilinx, Inc. | Configuration modes for a time multiplexed programmable logic device |
US5701441A (en) | 1995-08-18 | 1997-12-23 | Xilinx, Inc. | Computer-implemented method of optimizing a design in a time multiplexed programmable logic device |
US5565793A (en) | 1995-08-22 | 1996-10-15 | Altera Corporation | Programmable logic array integrated circuit devices with regions of enhanced interconnectivity |
US5661685A (en) | 1995-09-25 | 1997-08-26 | Xilinx, Inc. | Programmable logic device with configurable power supply |
US5880492A (en) | 1995-10-16 | 1999-03-09 | Xilinx, Inc. | Dedicated local line interconnect layout |
US5594367A (en) | 1995-10-16 | 1997-01-14 | Xilinx, Inc. | Output multiplexer within input/output circuit for time multiplexing and high speed logic |
US5815004A (en) | 1995-10-16 | 1998-09-29 | Xilinx, Inc. | Multi-buffered configurable logic block output lines in a field programmable gate array |
US5642058A (en) | 1995-10-16 | 1997-06-24 | Xilinx , Inc. | Periphery input/output interconnect structure |
US5600264A (en) | 1995-10-16 | 1997-02-04 | Xilinx, Inc. | Programmable single buffered six pass transistor configuration |
US5583452A (en) | 1995-10-26 | 1996-12-10 | Xilinx, Inc. | Tri-directional buffer |
US5687235A (en) * | 1995-10-26 | 1997-11-11 | Novell, Inc. | Certificate revocation performance optimization |
US5650734A (en) | 1995-12-11 | 1997-07-22 | Altera Corporation | Programming programmable transistor devices using state machines |
US5594690A (en) | 1995-12-15 | 1997-01-14 | Unisys Corporation | Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator |
US5914906A (en) | 1995-12-20 | 1999-06-22 | International Business Machines Corporation | Field programmable memory array |
US5760602A (en) | 1996-01-17 | 1998-06-02 | Hewlett-Packard Company | Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA |
US5870586A (en) | 1996-01-31 | 1999-02-09 | Xilinx, Inc. | Configuration emulation of a programmable logic device |
US5635851A (en) | 1996-02-02 | 1997-06-03 | Xilinx, Inc. | Read and writable data bus particularly for programmable logic devices |
US5737766A (en) | 1996-02-14 | 1998-04-07 | Hewlett Packard Company | Programmable gate array configuration memory which allows sharing with user memory |
US5744980A (en) | 1996-02-16 | 1998-04-28 | Actel Corporation | Flexible, high-performance static RAM architecture for field-programmable gate arrays |
US5835998A (en) | 1996-04-04 | 1998-11-10 | Altera Corporation | Logic cell for programmable logic devices |
US5687325A (en) | 1996-04-19 | 1997-11-11 | Chang; Web | Application specific field programmable gate array |
US5847441A (en) | 1996-05-10 | 1998-12-08 | Micron Technology, Inc. | Semiconductor junction antifuse circuit |
US5825201A (en) | 1996-06-21 | 1998-10-20 | Quicklogic Corporation | Programming architecture for a programmable integrated circuit employing antifuses |
US5828538A (en) | 1996-06-21 | 1998-10-27 | Quicklogic Corporation | Power-up circuit for field programmable gate arrays |
US5859544A (en) | 1996-09-05 | 1999-01-12 | Altera Corporation | Dynamic configurable elements for programmable logic devices |
US5881245A (en) * | 1996-09-10 | 1999-03-09 | Digital Video Systems, Inc. | Method and apparatus for transmitting MPEG data at an adaptive data rate |
US5880597A (en) | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
US5825202A (en) | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
US5883526A (en) | 1997-04-17 | 1999-03-16 | Altera Corporation | Hierarchical interconnect for programmable logic devices |
US5828230A (en) | 1997-01-09 | 1998-10-27 | Xilinx, Inc. | FPGA two turn routing structure with lane changing and minimum diffusion area |
US5880598A (en) | 1997-01-10 | 1999-03-09 | Xilinx, Inc. | Tile-based modular routing resources for high density programmable logic device |
US5821776A (en) | 1997-01-31 | 1998-10-13 | Actel Corporation | Field programmable gate array with mask programmed analog function circuits |
US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6751723B1 (en) * | 2000-09-02 | 2004-06-15 | Actel Corporation | Field programmable gate array and microcontroller system-on-a-chip |
US6825690B1 (en) * | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
US6838902B1 (en) * | 2003-05-28 | 2005-01-04 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US7385419B1 (en) * | 2003-05-30 | 2008-06-10 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
-
1997
- 1997-02-28 US US08/807,455 patent/US6150837A/en not_active Expired - Lifetime
-
1998
- 1998-02-03 EP EP02008837A patent/EP1237281A3/en not_active Withdrawn
- 1998-02-03 JP JP53766198A patent/JP3926398B2/ja not_active Expired - Lifetime
- 1998-02-03 EP EP02008836A patent/EP1237280B1/en not_active Expired - Lifetime
- 1998-02-03 DE DE69838462T patent/DE69838462T2/de not_active Expired - Lifetime
- 1998-02-03 EP EP98906180A patent/EP0901716B1/en not_active Expired - Lifetime
- 1998-02-03 EP EP02008838A patent/EP1229651A3/en not_active Withdrawn
- 1998-02-03 WO PCT/US1998/002280 patent/WO1998038741A1/en active IP Right Grant
- 1998-02-03 KR KR10-1998-0708623A patent/KR100491662B1/ko active IP Right Grant
- 1998-02-03 DE DE69813974T patent/DE69813974T2/de not_active Expired - Lifetime
- 1998-02-03 EP EP02008839A patent/EP1229652A3/en not_active Withdrawn
-
2000
- 2000-09-25 US US09/819,084 patent/US6791353B1/en not_active Expired - Lifetime
-
2004
- 2004-08-10 US US10/916,214 patent/US7382155B2/en not_active Expired - Fee Related
-
2008
- 2008-04-29 US US12/111,660 patent/US7755386B2/en not_active Expired - Fee Related
-
2010
- 2010-06-04 US US12/794,279 patent/US7977970B2/en not_active Expired - Fee Related
-
2011
- 2011-06-10 US US13/158,019 patent/US8258811B2/en not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003531509A (ja) * | 1999-08-31 | 2003-10-21 | クイックロジック コーポレイション | 専用及びプログラム可能論理を有する集積回路 |
JP4673533B2 (ja) * | 1999-08-31 | 2011-04-20 | クイックロジック コーポレイション | 専用及びプログラム可能論理を有する集積回路 |
JP2008042936A (ja) * | 2000-10-02 | 2008-02-21 | Altera Corp | 専用プロセッサ装置を含むプログラマブルロジック集積回路装置 |
JP2012023750A (ja) * | 2000-10-02 | 2012-02-02 | Altera Corp | 専用プロセッサ装置を含むプログラマブルロジック集積回路装置 |
JP2007522576A (ja) * | 2004-02-12 | 2007-08-09 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Io接続部を備えるデジタル信号処理集積回路 |
US7702884B2 (en) | 2005-01-11 | 2010-04-20 | Fujitsu Limited | Semiconductor integrated circuit with selected signal line coupling |
JP2007195191A (ja) * | 2006-01-19 | 2007-08-02 | Altera Corp | モジュール式i/oバンクアーキテクチャ |
JP4621215B2 (ja) * | 2006-01-19 | 2011-01-26 | アルテラ コーポレイション | モジュール式i/oバンクアーキテクチャ |
JP2008016663A (ja) * | 2006-07-06 | 2008-01-24 | Sharp Corp | 再構成可能な集積回路デバイス |
JP2012525706A (ja) * | 2009-05-01 | 2012-10-22 | アルテラ コーポレイション | 埋め込みデジタルストリップチップ |
WO2020144758A1 (ja) * | 2019-01-09 | 2020-07-16 | 三菱電機株式会社 | 秘密計算装置及びクライアント装置 |
JPWO2020144758A1 (ja) * | 2019-01-09 | 2021-03-11 | 三菱電機株式会社 | クライアント装置 |
Also Published As
Publication number | Publication date |
---|---|
DE69813974D1 (de) | 2003-06-05 |
EP1237280A3 (en) | 2005-08-17 |
US20110234258A1 (en) | 2011-09-29 |
WO1998038741A1 (en) | 1998-09-03 |
EP1237280A2 (en) | 2002-09-04 |
US20100244894A1 (en) | 2010-09-30 |
EP1229652A2 (en) | 2002-08-07 |
US7382155B2 (en) | 2008-06-03 |
EP1237280B1 (en) | 2007-09-19 |
US8258811B2 (en) | 2012-09-04 |
EP1229651A2 (en) | 2002-08-07 |
DE69838462T2 (de) | 2008-06-12 |
US7977970B2 (en) | 2011-07-12 |
US6791353B1 (en) | 2004-09-14 |
KR20000065061A (ko) | 2000-11-06 |
DE69838462D1 (de) | 2007-10-31 |
EP1229652A3 (en) | 2005-08-03 |
US20080197878A1 (en) | 2008-08-21 |
EP1229651A3 (en) | 2005-08-03 |
JP3926398B2 (ja) | 2007-06-06 |
KR100491662B1 (ko) | 2005-09-27 |
US7755386B2 (en) | 2010-07-13 |
DE69813974T2 (de) | 2003-11-06 |
EP0901716B1 (en) | 2003-05-02 |
US6150837A (en) | 2000-11-21 |
EP1237281A3 (en) | 2005-08-03 |
EP1237281A2 (en) | 2002-09-04 |
EP0901716A1 (en) | 1999-03-17 |
US20050081177A1 (en) | 2005-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2000509948A (ja) | 集積回路装置 | |
US6838904B1 (en) | Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation | |
JP3372755B2 (ja) | プログラマブル・アレイ | |
KR100413881B1 (ko) | 프로그램가능논리회로를위한상호접속체계및구조 | |
US5701091A (en) | Routing resources for hierarchical FPGA | |
US6216257B1 (en) | FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks | |
US5737235A (en) | FPGA with parallel and serial user interfaces | |
USRE37195E1 (en) | Programmable switch for FPGA input/output signals | |
US6218856B1 (en) | High speed programmable logic architecture | |
JPH11503290A (ja) | フィールド・プログラマブル・ゲートアレイにおける論理セル及びルーチング・アーキテクチャ | |
US6630842B1 (en) | Routing architecture for a programmable logic device | |
US7358766B2 (en) | Mask-programmable logic device with programmable portions | |
US7755388B2 (en) | Interconnect structure enabling indirect routing in programmable logic | |
US6970014B1 (en) | Routing architecture for a programmable logic device | |
US20040263205A1 (en) | Mask-programmable logic devices with programmable gate array sites | |
EP0769223B1 (en) | Programmable switch for fpga input/output signals | |
WO1999059088A2 (en) | A programmable logic device with macrocell controlled by a pla |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041104 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060829 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060818 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061128 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070130 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070228 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110309 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130309 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130309 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140309 Year of fee payment: 7 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |