ITTO20010333A0 - Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile. - Google Patents

Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile.

Info

Publication number
ITTO20010333A0
ITTO20010333A0 IT2001TO000333A ITTO20010333A ITTO20010333A0 IT TO20010333 A0 ITTO20010333 A0 IT TO20010333A0 IT 2001TO000333 A IT2001TO000333 A IT 2001TO000333A IT TO20010333 A ITTO20010333 A IT TO20010333A IT TO20010333 A0 ITTO20010333 A0 IT TO20010333A0
Authority
IT
Italy
Prior art keywords
management
volatile memory
during reading
cycles during
wait cycles
Prior art date
Application number
IT2001TO000333A
Other languages
English (en)
Inventor
Alessandro Francesco Maone
Maurizio Francesco Perroni
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT2001TO000333A priority Critical patent/ITTO20010333A1/it
Publication of ITTO20010333A0 publication Critical patent/ITTO20010333A0/it
Priority to US10/115,888 priority patent/US6917994B2/en
Publication of ITTO20010333A1 publication Critical patent/ITTO20010333A1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Read Only Memory (AREA)
IT2001TO000333A 2001-04-06 2001-04-06 Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile. ITTO20010333A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT2001TO000333A ITTO20010333A1 (it) 2001-04-06 2001-04-06 Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile.
US10/115,888 US6917994B2 (en) 2001-04-06 2002-04-03 Device and method for automatically generating an appropriate number of wait cycles while reading a nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT2001TO000333A ITTO20010333A1 (it) 2001-04-06 2001-04-06 Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile.

Publications (2)

Publication Number Publication Date
ITTO20010333A0 true ITTO20010333A0 (it) 2001-04-06
ITTO20010333A1 ITTO20010333A1 (it) 2002-10-06

Family

ID=11458766

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2001TO000333A ITTO20010333A1 (it) 2001-04-06 2001-04-06 Dispositivo e metodo di gestione dei cicli di attesa durante la lettura di una memoria non volatile.

Country Status (2)

Country Link
US (1) US6917994B2 (it)
IT (1) ITTO20010333A1 (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2870373B1 (fr) * 2004-05-13 2006-07-28 St Microelectronics Sa Gestion du gel d'un module fonctionnel dans un systeme sur une puce
CN100349108C (zh) * 2005-11-21 2007-11-14 北京中星微电子有限公司 与非门快闪存储器的物理接口、接口方法和管理设备
JPWO2007116827A1 (ja) * 2006-03-30 2009-08-20 パナソニック株式会社 半導体記憶装置
US9342445B2 (en) 2009-07-23 2016-05-17 Hgst Technologies Santa Ana, Inc. System and method for performing a direct memory access at a predetermined address in a flash storage
US9405720B2 (en) * 2013-03-15 2016-08-02 Atmel Corporation Managing wait states for memory access
US10042880B1 (en) * 2016-01-06 2018-08-07 Amazon Technologies, Inc. Automated identification of start-of-reading location for ebooks
US11881285B2 (en) 2021-03-23 2024-01-23 Nordic Semiconductor Asa Accessing memory circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6353669A (ja) * 1986-08-22 1988-03-07 Hitachi Micro Comput Eng Ltd マイクロプロセツサ
US5155812A (en) * 1989-05-04 1992-10-13 Texas Instruments Incorporated Devices and method for generating and using systems, software waitstates on address boundaries in data processing
JPH02235156A (ja) * 1989-03-08 1990-09-18 Canon Inc 情報処理装置
JPH03167649A (ja) * 1989-11-28 1991-07-19 Nec Corp ウエイト・サイクル制御装置
US5313621A (en) * 1990-05-18 1994-05-17 Zilog, Inc. Programmable wait states generator for a microprocessor and computer system utilizing it
US5592435A (en) * 1994-06-03 1997-01-07 Intel Corporation Pipelined read architecture for memory
US5563843A (en) * 1995-03-09 1996-10-08 Intel Corporation Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device
US5623648A (en) * 1995-08-30 1997-04-22 National Semiconductor Corporation Controller for initiating insertion of wait states on a signal bus
US5854944A (en) * 1996-05-09 1998-12-29 Motorola, Inc. Method and apparatus for determining wait states on a per cycle basis in a data processing system
US6131127A (en) * 1997-09-24 2000-10-10 Intel Corporation I/O transactions on a low pin count bus
US6119189A (en) * 1997-09-24 2000-09-12 Intel Corporation Bus master transactions on a low pin count bus
US6356987B1 (en) * 1999-03-10 2002-03-12 Atmel Corporation Microprocessing device having programmable wait states
US6742058B2 (en) * 2002-09-27 2004-05-25 Texas Instruments Incorporated Memory controller having a multiplexer selecting either second set of input signals or converted signals from first set of input signals by a bus mode input

Also Published As

Publication number Publication date
ITTO20010333A1 (it) 2002-10-06
US20020184420A1 (en) 2002-12-05
US6917994B2 (en) 2005-07-12

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