ITMI913355A0 - Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabili elettricamente - Google Patents

Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabili elettricamente

Info

Publication number
ITMI913355A0
ITMI913355A0 IT91MI3355A ITMI913355A ITMI913355A0 IT MI913355 A0 ITMI913355 A0 IT MI913355A0 IT 91MI3355 A IT91MI3355 A IT 91MI3355A IT MI913355 A ITMI913355 A IT MI913355A IT MI913355 A0 ITMI913355 A0 IT MI913355A0
Authority
IT
Italy
Prior art keywords
definition
procedure
memory cells
electrically programmable
thin oxide
Prior art date
Application number
IT91MI3355A
Other languages
English (en)
Inventor
Paolo Ghezzi
Federico Pio
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to ITMI913355A priority Critical patent/IT1252214B/it
Publication of ITMI913355A0 publication Critical patent/ITMI913355A0/it
Priority to DE69221090T priority patent/DE69221090T2/de
Priority to EP92119581A priority patent/EP0546353B1/en
Priority to JP4330492A priority patent/JPH05259467A/ja
Priority to US07/988,474 priority patent/US5393684A/en
Publication of ITMI913355A1 publication Critical patent/ITMI913355A1/it
Priority to US08/329,309 priority patent/US5527728A/en
Application granted granted Critical
Publication of IT1252214B publication Critical patent/IT1252214B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
ITMI913355A 1991-12-13 1991-12-13 Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente. IT1252214B (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
ITMI913355A IT1252214B (it) 1991-12-13 1991-12-13 Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente.
DE69221090T DE69221090T2 (de) 1991-12-13 1992-11-17 Verfahren zur Herstellung dünner Oxidschichte für elektrisch löschbare und programmierbare Nurlesespeicherzelle
EP92119581A EP0546353B1 (en) 1991-12-13 1992-11-17 Method for forming thin oxide portions in electrically erasable and programmable read-only memory cells
JP4330492A JPH05259467A (ja) 1991-12-13 1992-12-10 特に電気的消去書込み可能な読み出し専用メモリセルにおいて薄い酸化物部分を形成する方法
US07/988,474 US5393684A (en) 1991-12-13 1992-12-10 Method of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells
US08/329,309 US5527728A (en) 1991-12-13 1994-10-26 Method of making thin oxide portions consisting of gate and tunnel oxides particularly in electrically erasable and programmable read-only memory cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI913355A IT1252214B (it) 1991-12-13 1991-12-13 Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente.

Publications (3)

Publication Number Publication Date
ITMI913355A0 true ITMI913355A0 (it) 1991-12-13
ITMI913355A1 ITMI913355A1 (it) 1993-06-13
IT1252214B IT1252214B (it) 1995-06-05

Family

ID=11361336

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI913355A IT1252214B (it) 1991-12-13 1991-12-13 Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente.

Country Status (5)

Country Link
US (2) US5393684A (it)
EP (1) EP0546353B1 (it)
JP (1) JPH05259467A (it)
DE (1) DE69221090T2 (it)
IT (1) IT1252214B (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6236597B1 (en) 1996-09-16 2001-05-22 Altera Corporation Nonvolatile memory cell with multiple gate oxide thicknesses
US5750428A (en) * 1996-09-27 1998-05-12 United Microelectronics Corp. Self-aligned non-volatile process with differentially grown gate oxide thickness
IT1289524B1 (it) 1996-12-24 1998-10-15 Sgs Thomson Microelectronics Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione
IT1289525B1 (it) * 1996-12-24 1998-10-15 Sgs Thomson Microelectronics Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione
US5895240A (en) * 1997-06-30 1999-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making stepped edge structure of an EEPROM tunneling window
JP4081854B2 (ja) * 1998-05-11 2008-04-30 沖電気工業株式会社 半導体装置の製造方法
US6373094B2 (en) * 1998-09-11 2002-04-16 Texas Instruments Incorporated EEPROM cell using conventional process steps
KR100495090B1 (ko) * 1998-10-02 2005-09-02 삼성전자주식회사 Eeprom의 터널영역 축소방법
KR100481856B1 (ko) * 2002-08-14 2005-04-11 삼성전자주식회사 이이피롬 및 마스크롬을 구비하는 반도체 장치 및 그 제조방법
KR100660903B1 (ko) * 2005-12-23 2006-12-26 삼성전자주식회사 프로그래밍 속도를 개선한 이이피롬, 이의 제조 방법 및이의 동작 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519851A (en) * 1978-07-31 1980-02-12 Hitachi Ltd Manufacture of non-volatile memories
JPS61174774A (ja) * 1985-01-30 1986-08-06 Toshiba Corp 不揮発性半導体メモリ装置の製造方法
JPS61222175A (ja) * 1985-03-01 1986-10-02 Fujitsu Ltd 半導体記憶装置の製造方法
EP0350771B1 (en) * 1988-07-15 1994-10-12 Texas Instruments Incorporated Electrically erasable, electrically programmable read-only memory cell with a self-aligned tunnel window
EP0366423B1 (en) * 1988-10-25 1994-05-25 Matsushita Electronics Corporation Manufacturing method of semiconductor non-volatile memory device
US4957877A (en) * 1988-11-21 1990-09-18 Intel Corporation Process for simultaneously fabricating EEPROM cell and flash EPROM cell
US5215934A (en) * 1989-12-21 1993-06-01 Tzeng Jyh Cherng J Process for reducing program disturbance in eeprom arrays
US5198381A (en) * 1991-09-12 1993-03-30 Vlsi Technology, Inc. Method of making an E2 PROM cell with improved tunneling properties having two implant stages
US5273923A (en) * 1991-10-09 1993-12-28 Motorola, Inc. Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions

Also Published As

Publication number Publication date
EP0546353A3 (en) 1993-08-18
IT1252214B (it) 1995-06-05
DE69221090D1 (de) 1997-09-04
ITMI913355A1 (it) 1993-06-13
JPH05259467A (ja) 1993-10-08
EP0546353A2 (en) 1993-06-16
DE69221090T2 (de) 1998-03-05
US5527728A (en) 1996-06-18
EP0546353B1 (en) 1997-07-23
US5393684A (en) 1995-02-28

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227