DE69221090D1 - Verfahren zur Herstellung dünner Oxidschichte für elektrisch löschbare und programmierbare Nurlesespeicherzelle - Google Patents

Verfahren zur Herstellung dünner Oxidschichte für elektrisch löschbare und programmierbare Nurlesespeicherzelle

Info

Publication number
DE69221090D1
DE69221090D1 DE69221090T DE69221090T DE69221090D1 DE 69221090 D1 DE69221090 D1 DE 69221090D1 DE 69221090 T DE69221090 T DE 69221090T DE 69221090 T DE69221090 T DE 69221090T DE 69221090 D1 DE69221090 D1 DE 69221090D1
Authority
DE
Germany
Prior art keywords
production
memory cells
programmable read
electrically erasable
oxide layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69221090T
Other languages
English (en)
Other versions
DE69221090T2 (de
Inventor
Paolo Ghezzi
Federico Pio
Carlo Riva
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE69221090D1 publication Critical patent/DE69221090D1/de
Application granted granted Critical
Publication of DE69221090T2 publication Critical patent/DE69221090T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
DE69221090T 1991-12-13 1992-11-17 Verfahren zur Herstellung dünner Oxidschichte für elektrisch löschbare und programmierbare Nurlesespeicherzelle Expired - Fee Related DE69221090T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI913355A IT1252214B (it) 1991-12-13 1991-12-13 Procedimento per la definizione di porzioni di ossido sottile particolarmente per celle di memoria a sola lettura programmabili e cancellabile elettricamente.

Publications (2)

Publication Number Publication Date
DE69221090D1 true DE69221090D1 (de) 1997-09-04
DE69221090T2 DE69221090T2 (de) 1998-03-05

Family

ID=11361336

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69221090T Expired - Fee Related DE69221090T2 (de) 1991-12-13 1992-11-17 Verfahren zur Herstellung dünner Oxidschichte für elektrisch löschbare und programmierbare Nurlesespeicherzelle

Country Status (5)

Country Link
US (2) US5393684A (de)
EP (1) EP0546353B1 (de)
JP (1) JPH05259467A (de)
DE (1) DE69221090T2 (de)
IT (1) IT1252214B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6236597B1 (en) 1996-09-16 2001-05-22 Altera Corporation Nonvolatile memory cell with multiple gate oxide thicknesses
US5750428A (en) * 1996-09-27 1998-05-12 United Microelectronics Corp. Self-aligned non-volatile process with differentially grown gate oxide thickness
IT1289525B1 (it) * 1996-12-24 1998-10-15 Sgs Thomson Microelectronics Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione
IT1289524B1 (it) * 1996-12-24 1998-10-15 Sgs Thomson Microelectronics Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione
US5895240A (en) * 1997-06-30 1999-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making stepped edge structure of an EEPROM tunneling window
JP4081854B2 (ja) * 1998-05-11 2008-04-30 沖電気工業株式会社 半導体装置の製造方法
US6373094B2 (en) * 1998-09-11 2002-04-16 Texas Instruments Incorporated EEPROM cell using conventional process steps
KR100495090B1 (ko) * 1998-10-02 2005-09-02 삼성전자주식회사 Eeprom의 터널영역 축소방법
KR100481856B1 (ko) * 2002-08-14 2005-04-11 삼성전자주식회사 이이피롬 및 마스크롬을 구비하는 반도체 장치 및 그 제조방법
KR100660903B1 (ko) * 2005-12-23 2006-12-26 삼성전자주식회사 프로그래밍 속도를 개선한 이이피롬, 이의 제조 방법 및이의 동작 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519851A (en) * 1978-07-31 1980-02-12 Hitachi Ltd Manufacture of non-volatile memories
JPS61174774A (ja) * 1985-01-30 1986-08-06 Toshiba Corp 不揮発性半導体メモリ装置の製造方法
JPS61222175A (ja) * 1985-03-01 1986-10-02 Fujitsu Ltd 半導体記憶装置の製造方法
EP0350771B1 (de) * 1988-07-15 1994-10-12 Texas Instruments Incorporated Elektrisch löschbare und elektrisch programmierbare Nurlesespeicherzelle mit einem selbstjustierten Tunneleffekt-Fenster
DE68915508T2 (de) * 1988-10-25 1994-12-15 Matsushita Electronics Corp Verfahren zur Herstellung einer nicht-flüchtigen Speicheranordnung.
US4957877A (en) * 1988-11-21 1990-09-18 Intel Corporation Process for simultaneously fabricating EEPROM cell and flash EPROM cell
US5215934A (en) * 1989-12-21 1993-06-01 Tzeng Jyh Cherng J Process for reducing program disturbance in eeprom arrays
US5198381A (en) * 1991-09-12 1993-03-30 Vlsi Technology, Inc. Method of making an E2 PROM cell with improved tunneling properties having two implant stages
US5273923A (en) * 1991-10-09 1993-12-28 Motorola, Inc. Process for fabricating an EEPROM cell having a tunnel opening which overlaps field isolation regions

Also Published As

Publication number Publication date
EP0546353A2 (de) 1993-06-16
DE69221090T2 (de) 1998-03-05
EP0546353A3 (en) 1993-08-18
JPH05259467A (ja) 1993-10-08
ITMI913355A0 (it) 1991-12-13
US5393684A (en) 1995-02-28
ITMI913355A1 (it) 1993-06-13
US5527728A (en) 1996-06-18
IT1252214B (it) 1995-06-05
EP0546353B1 (de) 1997-07-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee