IT9009454A0 - Cella di memoria statica ad accesso casuale a quattro transistori - Google Patents

Cella di memoria statica ad accesso casuale a quattro transistori

Info

Publication number
IT9009454A0
IT9009454A0 IT909454A IT945490A IT9009454A0 IT 9009454 A0 IT9009454 A0 IT 9009454A0 IT 909454 A IT909454 A IT 909454A IT 945490 A IT945490 A IT 945490A IT 9009454 A0 IT9009454 A0 IT 9009454A0
Authority
IT
Italy
Prior art keywords
memory cell
random access
static memory
transistor random
access static
Prior art date
Application number
IT909454A
Other languages
English (en)
Other versions
IT9009454A1 (it
IT1245983B (it
Inventor
Frank Wanlass
Original Assignee
Standard Microsyst Smc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Microsyst Smc filed Critical Standard Microsyst Smc
Publication of IT9009454A0 publication Critical patent/IT9009454A0/it
Publication of IT9009454A1 publication Critical patent/IT9009454A1/it
Application granted granted Critical
Publication of IT1245983B publication Critical patent/IT1245983B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
IT00945490A 1989-08-07 1990-08-03 Cella di memoria statica ad accesso casuale a quattro transistori IT1245983B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/390,086 US5020028A (en) 1989-08-07 1989-08-07 Four transistor static RAM cell

Publications (3)

Publication Number Publication Date
IT9009454A0 true IT9009454A0 (it) 1990-08-03
IT9009454A1 IT9009454A1 (it) 1991-02-08
IT1245983B IT1245983B (it) 1994-11-07

Family

ID=23540990

Family Applications (1)

Application Number Title Priority Date Filing Date
IT00945490A IT1245983B (it) 1989-08-07 1990-08-03 Cella di memoria statica ad accesso casuale a quattro transistori

Country Status (7)

Country Link
US (1) US5020028A (it)
JP (1) JPH0482080A (it)
CA (1) CA2012668C (it)
DE (1) DE4014228A1 (it)
FR (1) FR2650694B3 (it)
GB (1) GB2234873B (it)
IT (1) IT1245983B (it)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5264741A (en) * 1992-06-19 1993-11-23 Aptix Corporation Low current, fast, CMOS static pullup circuit for static random-access memories
KR0121992B1 (ko) * 1993-03-03 1997-11-12 모리시다 요이치 반도체장치 및 그 제조방법
US5475633A (en) * 1994-06-01 1995-12-12 Intel Corporation Cache memory utilizing pseudo static four transistor memory cell
US5793671A (en) * 1997-01-21 1998-08-11 Advanced Micro Devices, Inc. Static random access memory cell utilizing enhancement mode N-channel transistors as load elements
US5881010A (en) * 1997-05-15 1999-03-09 Stmicroelectronics, Inc. Multiple transistor dynamic random access memory array architecture with simultaneous refresh of multiple memory cells during a read operation
GB9721654D0 (en) * 1997-10-14 1997-12-10 Willey Robinson Ltd Gas heating apparatus
FR2769746B1 (fr) * 1997-10-14 2000-01-28 St Microelectronics Sa Dispositif de memoire vive dynamique a duree de rafraichissement reduite, et procede correspondant de rafraichissement
US6040991A (en) * 1999-01-04 2000-03-21 International Business Machines Corporation SRAM memory cell having reduced surface area
US6442060B1 (en) * 2000-05-09 2002-08-27 Monolithic System Technology, Inc. High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process
US6370052B1 (en) 2000-07-19 2002-04-09 Monolithic System Technology, Inc. Method and structure of ternary CAM cell in logic process
US6614124B1 (en) 2000-11-28 2003-09-02 International Business Machines Corporation Simple 4T static ram cell for low power CMOS applications
JP4219663B2 (ja) * 2002-11-29 2009-02-04 株式会社ルネサステクノロジ 半導体記憶装置及び半導体集積回路
US7403426B2 (en) * 2005-05-25 2008-07-22 Intel Corporation Memory with dynamically adjustable supply
JP5415672B2 (ja) * 2006-12-19 2014-02-12 ルネサスエレクトロニクス株式会社 半導体装置
US8213257B2 (en) * 2010-08-09 2012-07-03 Faraday Technology Corp. Variation-tolerant word-line under-drive scheme for random access memory
KR102003930B1 (ko) * 2012-07-31 2019-07-25 삼성전자주식회사 불휘발성 메모리 장치의 데이터 라이팅 제어방법 및 웨어레벨링 제어 기능을 가지는 메모리 콘트롤러
US10614877B1 (en) 2019-01-10 2020-04-07 International Business Machines Corporation 4T static random access memory bitcell retention
US10885967B2 (en) * 2019-01-14 2021-01-05 Micron Technology, Inc. Systems and methods for improving power efficiency in refreshing memory banks

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541530A (en) * 1968-01-15 1970-11-17 Ibm Pulsed power four device memory cell
US3836892A (en) * 1972-06-29 1974-09-17 Ibm D.c. stable electronic storage utilizing a.c. stable storage cell
JPS5415736B2 (it) * 1972-11-24 1979-06-16
JPS5615073B2 (it) * 1973-10-11 1981-04-08
JPS5140830A (it) * 1974-10-04 1976-04-06 Nippon Electric Co
US3949383A (en) * 1974-12-23 1976-04-06 Ibm Corporation D. C. Stable semiconductor memory cell
US4023149A (en) * 1975-10-28 1977-05-10 Motorola, Inc. Static storage technique for four transistor IGFET memory cell
US4334293A (en) * 1978-07-19 1982-06-08 Texas Instruments Incorporated Semiconductor memory cell with clocked voltage supply from data lines
JPS62273694A (ja) * 1986-05-22 1987-11-27 Sony Corp センスアンプ
JPS6381694A (ja) * 1986-09-26 1988-04-12 Sony Corp メモリセル回路
US4796227A (en) * 1987-03-17 1989-01-03 Schlumberger Systems And Services, Inc. Computer memory system

Also Published As

Publication number Publication date
FR2650694B3 (fr) 1991-11-29
CA2012668C (en) 2000-08-01
JPH0482080A (ja) 1992-03-16
GB2234873B (en) 1994-07-27
FR2650694A1 (fr) 1991-02-08
US5020028A (en) 1991-05-28
IT9009454A1 (it) 1991-02-08
CA2012668A1 (en) 1991-02-07
DE4014228A1 (de) 1991-02-14
GB9008961D0 (en) 1990-06-20
IT1245983B (it) 1994-11-07
GB2234873A (en) 1991-02-13

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19980828