IT8419086A0 - Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante. - Google Patents

Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante.

Info

Publication number
IT8419086A0
IT8419086A0 IT8419086A IT1908684A IT8419086A0 IT 8419086 A0 IT8419086 A0 IT 8419086A0 IT 8419086 A IT8419086 A IT 8419086A IT 1908684 A IT1908684 A IT 1908684A IT 8419086 A0 IT8419086 A0 IT 8419086A0
Authority
IT
Italy
Prior art keywords
manufacture
integrated circuits
mos transistors
threshold voltages
low threshold
Prior art date
Application number
IT8419086A
Other languages
English (en)
Other versions
IT1213120B (it
Inventor
Livio Baldi
Giuseppe Corda
Giulio Iannuzzi
Danilo Re
Giorgio De Santi
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8419086A priority Critical patent/IT1213120B/it
Publication of IT8419086A0 publication Critical patent/IT8419086A0/it
Priority to US06/689,875 priority patent/US4703552A/en
Priority to DE3500528A priority patent/DE3500528C2/de
Priority to FR8500223A priority patent/FR2558010B1/fr
Priority to GB08500612A priority patent/GB2153146B/en
Priority to NL8500053A priority patent/NL8500053A/nl
Priority to JP60002620A priority patent/JPS60210863A/ja
Application granted granted Critical
Publication of IT1213120B publication Critical patent/IT1213120B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT8419086A 1984-01-10 1984-01-10 Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante. IT1213120B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8419086A IT1213120B (it) 1984-01-10 1984-01-10 Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante.
US06/689,875 US4703552A (en) 1984-01-10 1985-01-09 Fabricating a CMOS transistor having low threshold voltages using self-aligned silicide polysilicon gates and silicide interconnect regions
DE3500528A DE3500528C2 (de) 1984-01-10 1985-01-09 Verfahren zur Bildung eines Paares komplementärer MOS-Transistoren
FR8500223A FR2558010B1 (fr) 1984-01-10 1985-01-09 Procede pour la fabrication de transistors mos complementaires a basses tensions de seuil dans des circuits integres a haute densite et structure resultant de ce procede
GB08500612A GB2153146B (en) 1984-01-10 1985-01-10 Improvements in or relating to manufacture of cmos transistors
NL8500053A NL8500053A (nl) 1984-01-10 1985-01-10 Werkwijze voor de vervaardiging van cmos-transistors met lage drempelspanningen in hoge dichtheid geintegreerde schakelingen, alsmede de daardoor vervaardigde structuur.
JP60002620A JPS60210863A (ja) 1984-01-10 1985-01-10 相補ｍｏｓ集積回路及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8419086A IT1213120B (it) 1984-01-10 1984-01-10 Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante.

Publications (2)

Publication Number Publication Date
IT8419086A0 true IT8419086A0 (it) 1984-01-10
IT1213120B IT1213120B (it) 1989-12-14

Family

ID=11154419

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8419086A IT1213120B (it) 1984-01-10 1984-01-10 Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante.

Country Status (7)

Country Link
US (1) US4703552A (it)
JP (1) JPS60210863A (it)
DE (1) DE3500528C2 (it)
FR (1) FR2558010B1 (it)
GB (1) GB2153146B (it)
IT (1) IT1213120B (it)
NL (1) NL8500053A (it)

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JPS61139058A (ja) * 1984-12-11 1986-06-26 Seiko Epson Corp 半導体製造装置
US5190886A (en) * 1984-12-11 1993-03-02 Seiko Epson Corporation Semiconductor device and method of production
US4782033A (en) * 1985-11-27 1988-11-01 Siemens Aktiengesellschaft Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate
US5066995A (en) * 1987-03-13 1991-11-19 Harris Corporation Double level conductor structure
JPS63239856A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体集積回路装置及びその製造方法
US5059546A (en) * 1987-05-01 1991-10-22 Texas Instruments Incorporated BICMOS process for forming shallow NPN emitters and mosfet source/drains
US4816423A (en) * 1987-05-01 1989-03-28 Texas Instruments Incorporated Bicmos process for forming shallow npn emitters and mosfet source/drains
KR900008868B1 (ko) * 1987-09-30 1990-12-11 삼성전자 주식회사 저항성 접촉을 갖는 반도체 장치의 제조방법
US4786611A (en) * 1987-10-19 1988-11-22 Motorola, Inc. Adjusting threshold voltages by diffusion through refractory metal silicides
DE3817882A1 (de) * 1988-05-26 1989-12-07 Siemens Ag Bipolartransistorstruktur mit reduziertem basiswiderstand und verfahren zur herstellung eines basisanschlussbereiches fuer die bipolartransistorstruktur
US4951113A (en) * 1988-11-07 1990-08-21 Xerox Corporation Simultaneously deposited thin film CMOS TFTs and their method of fabrication
JP2672607B2 (ja) * 1988-11-22 1997-11-05 株式会社東芝 半導体装置の製造方法
JPH0758701B2 (ja) * 1989-06-08 1995-06-21 株式会社東芝 半導体装置の製造方法
JPH03141645A (ja) * 1989-07-10 1991-06-17 Texas Instr Inc <Ti> ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子
US5021356A (en) * 1989-08-24 1991-06-04 Delco Electronics Corporation Method of making MOSFET depletion device
US5095348A (en) * 1989-10-02 1992-03-10 Texas Instruments Incorporated Semiconductor on insulator transistor
US4992391A (en) * 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET
US5021354A (en) * 1989-12-04 1991-06-04 Motorola, Inc. Process for manufacturing a semiconductor device
EP0482232B1 (de) * 1990-10-23 1996-06-05 Siemens Aktiengesellschaft Verfahren zur Herstellung einer dotierten Polyzidschicht auf einem Halbleitersubstrat
US7115902B1 (en) 1990-11-20 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US5849601A (en) 1990-12-25 1998-12-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US7098479B1 (en) * 1990-12-25 2006-08-29 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US7576360B2 (en) 1990-12-25 2009-08-18 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device which comprises thin film transistors and method for manufacturing the same
US5355010A (en) * 1991-06-21 1994-10-11 Matsushita Electric Industrial Co., Ltd. Semiconductor device with a dual type polycide layer comprising a uniformly p-type doped silicide
DE4121051A1 (de) * 1991-06-26 1993-01-07 Eurosil Electronic Gmbh Halbleiteranordnung und verfahren zur herstellung
US5478771A (en) * 1993-05-28 1995-12-26 Sgs-Thomson Microelectronics, Inc. Method of forming local interconnect structure without P-N junction between active elements
EP0637073A1 (en) * 1993-07-29 1995-02-01 STMicroelectronics S.r.l. Process for realizing low threshold P-channel MOS transistors for complementary devices (CMOS)
JP2934738B2 (ja) * 1994-03-18 1999-08-16 セイコーインスツルメンツ株式会社 半導体装置およびその製造方法
US5489797A (en) * 1994-12-19 1996-02-06 Sgs-Thomson Microelectronics, Inc. Local interconnect structure
JPH08264660A (ja) * 1995-03-24 1996-10-11 Nec Corp 半導体装置の製造方法
US5605861A (en) * 1995-05-05 1997-02-25 Texas Instruments Incorporated Thin polysilicon doping by diffusion from a doped silicon dioxide film
US5550079A (en) * 1995-06-15 1996-08-27 Top Team/Microelectronics Corp. Method for fabricating silicide shunt of dual-gate CMOS device
US5780330A (en) * 1996-06-28 1998-07-14 Integrated Device Technology, Inc. Selective diffusion process for forming both n-type and p-type gates with a single masking step
US6171897B1 (en) * 1997-03-28 2001-01-09 Sharp Kabushiki Kaisha Method for manufacturing CMOS semiconductor device
US6956281B2 (en) * 2002-08-21 2005-10-18 Freescale Semiconductor, Inc. Semiconductor device for reducing photovolatic current

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CA934483A (en) * 1970-08-19 1973-09-25 Rca Corporation Fabrication of complementary semiconductor devices
US3749614A (en) * 1970-09-14 1973-07-31 Rca Corp Fabrication of semiconductor devices
US4041518A (en) * 1973-02-24 1977-08-09 Hitachi, Ltd. MIS semiconductor device and method of manufacturing the same
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
NL190710C (nl) * 1978-02-10 1994-07-01 Nec Corp Geintegreerde halfgeleiderketen.
US4333099A (en) * 1978-02-27 1982-06-01 Rca Corporation Use of silicide to bridge unwanted polycrystalline silicon P-N junction
JPS5568675A (en) * 1978-11-17 1980-05-23 Toshiba Corp Fabrication of complementary mos transistor
JPS55134962A (en) 1979-04-09 1980-10-21 Toshiba Corp Semiconductor device
CA1142261A (en) * 1979-06-29 1983-03-01 Siegfried K. Wiedmann Interconnection of opposite conductivity type semiconductor regions
JPS5650535A (en) * 1979-10-01 1981-05-07 Hitachi Ltd Manufacture of semiconductor device
US4336550A (en) * 1980-03-20 1982-06-22 Rca Corporation CMOS Device with silicided sources and drains and method
JPS5736856A (en) * 1980-08-15 1982-02-27 Hitachi Ltd Manufacture of complementary type insulated gate field effect semiconductor device
US4551908A (en) * 1981-06-15 1985-11-12 Nippon Electric Co., Ltd. Process of forming electrodes and interconnections on silicon semiconductor devices
US4617071A (en) * 1981-10-27 1986-10-14 Fairchild Semiconductor Corporation Method of fabricating electrically connected regions of opposite conductivity type in a semiconductor structure
US4422885A (en) * 1981-12-18 1983-12-27 Ncr Corporation Polysilicon-doped-first CMOS process
US4442591A (en) * 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
JPS58175846A (ja) * 1982-04-08 1983-10-15 Toshiba Corp 半導体装置の製造方法
US4558507A (en) * 1982-11-12 1985-12-17 Nec Corporation Method of manufacturing semiconductor device
US4519126A (en) * 1983-12-12 1985-05-28 Rca Corporation Method of fabricating high speed CMOS devices
US4587710A (en) * 1984-06-15 1986-05-13 Gould Inc. Method of fabricating a Schottky barrier field effect transistor
US4561170A (en) * 1984-07-02 1985-12-31 Texas Instruments Incorporated Method of making field-plate isolated CMOS devices

Also Published As

Publication number Publication date
US4703552A (en) 1987-11-03
NL8500053A (nl) 1985-08-01
GB2153146A (en) 1985-08-14
DE3500528C2 (de) 1996-09-12
GB8500612D0 (en) 1985-02-13
FR2558010B1 (fr) 1987-12-18
JPS60210863A (ja) 1985-10-23
IT1213120B (it) 1989-12-14
DE3500528A1 (de) 1985-07-18
FR2558010A1 (fr) 1985-07-12
GB2153146B (en) 1987-09-16

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960129