IT1243676B - Stadio d'ingresso pluricompatibile particolarmente per porte logiche in circuiti integrati - Google Patents
Stadio d'ingresso pluricompatibile particolarmente per porte logiche in circuiti integratiInfo
- Publication number
- IT1243676B IT1243676B IT02098890A IT2098890A IT1243676B IT 1243676 B IT1243676 B IT 1243676B IT 02098890 A IT02098890 A IT 02098890A IT 2098890 A IT2098890 A IT 2098890A IT 1243676 B IT1243676 B IT 1243676B
- Authority
- IT
- Italy
- Prior art keywords
- integrated circuits
- entrance stage
- logic doors
- compatible
- compatible entrance
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Near-Field Transmission Systems (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT02098890A IT1243676B (it) | 1990-07-19 | 1990-07-19 | Stadio d'ingresso pluricompatibile particolarmente per porte logiche in circuiti integrati |
EP19910111986 EP0467352A3 (en) | 1990-07-19 | 1991-07-17 | Multi-compatible input stage particularly for logic gates in integrated circuits |
JP3177864A JPH04242318A (ja) | 1990-07-19 | 1991-07-18 | 特に集積回路内の論理ゲートのための多重互換性入力段 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT02098890A IT1243676B (it) | 1990-07-19 | 1990-07-19 | Stadio d'ingresso pluricompatibile particolarmente per porte logiche in circuiti integrati |
Publications (3)
Publication Number | Publication Date |
---|---|
IT9020988A0 IT9020988A0 (it) | 1990-07-19 |
IT9020988A1 IT9020988A1 (it) | 1992-01-19 |
IT1243676B true IT1243676B (it) | 1994-06-21 |
Family
ID=11175035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT02098890A IT1243676B (it) | 1990-07-19 | 1990-07-19 | Stadio d'ingresso pluricompatibile particolarmente per porte logiche in circuiti integrati |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0467352A3 (it) |
JP (1) | JPH04242318A (it) |
IT (1) | IT1243676B (it) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0590326A1 (de) * | 1992-09-29 | 1994-04-06 | Siemens Aktiengesellschaft | CMOS-Eingangsstufe |
JPH06209252A (ja) * | 1992-09-29 | 1994-07-26 | Siemens Ag | Cmos入力段 |
US5319252A (en) * | 1992-11-05 | 1994-06-07 | Xilinx, Inc. | Load programmable output buffer |
US6356099B1 (en) | 1994-11-10 | 2002-03-12 | Advanced Micro Devices, Inc. | Transmission-line-noise immune input buffer |
US5477172A (en) * | 1994-12-12 | 1995-12-19 | Advanced Micro Devices, Inc. | Configurable input buffer dependent on supply voltage |
CN1183587C (zh) * | 1996-04-08 | 2005-01-05 | 德克萨斯仪器股份有限公司 | 用于把两个集成电路直流上相互隔离的方法和设备 |
JPH09321603A (ja) * | 1996-05-28 | 1997-12-12 | Oki Electric Ind Co Ltd | 多電源半導体集積回路 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01123517A (ja) * | 1987-11-07 | 1989-05-16 | Mitsubishi Electric Corp | シュミットトリガ回路 |
US4904884A (en) * | 1988-04-21 | 1990-02-27 | Western Digital Corporation | Schmitt trigger adapted to interface between different transistor architectures |
-
1990
- 1990-07-19 IT IT02098890A patent/IT1243676B/it active IP Right Grant
-
1991
- 1991-07-17 EP EP19910111986 patent/EP0467352A3/en not_active Withdrawn
- 1991-07-18 JP JP3177864A patent/JPH04242318A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JPH04242318A (ja) | 1992-08-31 |
EP0467352A2 (en) | 1992-01-22 |
EP0467352A3 (en) | 1992-04-29 |
IT9020988A0 (it) | 1990-07-19 |
IT9020988A1 (it) | 1992-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970730 |