DE69428649D1 - LSI-Toranordnung - Google Patents

LSI-Toranordnung

Info

Publication number
DE69428649D1
DE69428649D1 DE69428649T DE69428649T DE69428649D1 DE 69428649 D1 DE69428649 D1 DE 69428649D1 DE 69428649 T DE69428649 T DE 69428649T DE 69428649 T DE69428649 T DE 69428649T DE 69428649 D1 DE69428649 D1 DE 69428649D1
Authority
DE
Germany
Prior art keywords
gate arrangement
lsi gate
lsi
arrangement
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69428649T
Other languages
English (en)
Other versions
DE69428649T2 (de
Inventor
Toru Inoue
Michihiro Amiya
Tadao Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69428649D1 publication Critical patent/DE69428649D1/de
Publication of DE69428649T2 publication Critical patent/DE69428649T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69428649T 1993-08-13 1994-08-04 LSI-Toranordnung Expired - Fee Related DE69428649T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5201566A JPH0758301A (ja) 1993-08-13 1993-08-13 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69428649D1 true DE69428649D1 (de) 2001-11-22
DE69428649T2 DE69428649T2 (de) 2002-06-20

Family

ID=16443187

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69432270T Expired - Fee Related DE69432270T2 (de) 1993-08-13 1994-08-04 LSI-Toranordnung
DE69428649T Expired - Fee Related DE69428649T2 (de) 1993-08-13 1994-08-04 LSI-Toranordnung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69432270T Expired - Fee Related DE69432270T2 (de) 1993-08-13 1994-08-04 LSI-Toranordnung

Country Status (5)

Country Link
US (1) US5506428A (de)
EP (2) EP0827207B1 (de)
JP (1) JPH0758301A (de)
KR (1) KR100303222B1 (de)
DE (2) DE69432270T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0782187B1 (de) * 1995-12-29 2000-06-28 STMicroelectronics S.r.l. Standardzellenbibliothek für den Entwurf von integrierten Schaltungen
JP3178427B2 (ja) * 1998-08-18 2001-06-18 日本電気株式会社 半導体記憶装置
JP2003092355A (ja) 2001-09-19 2003-03-28 Mitsubishi Electric Corp 半導体集積回路装置
JP2006100718A (ja) * 2004-09-30 2006-04-13 Matsushita Electric Ind Co Ltd 半導体集積回路装置の動作解析方法、これに用いられる解析装置およびこれを用いた最適化設計方法
KR100843220B1 (ko) * 2006-12-19 2008-07-02 삼성전자주식회사 동일 평면상 엘.씨 벨런싱이 달성된 인쇄회로기판
FR2968128B1 (fr) 2010-11-26 2013-01-04 St Microelectronics Sa Cellule precaracterisee pour circuit intégré
US8816403B2 (en) * 2011-09-21 2014-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Efficient semiconductor device cell layout utilizing underlying local connective features
EP4060738A4 (de) 2021-02-05 2022-11-30 Changxin Memory Technologies, Inc. Standardzelltemplate und halbleiterstruktur
WO2024122918A1 (ko) * 2022-12-08 2024-06-13 엘지전자 주식회사 거품을 줄이는 방법 및 세탁기

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4514749A (en) * 1983-01-18 1985-04-30 At&T Bell Laboratories VLSI Chip with ground shielding
JPS61230359A (ja) * 1985-04-05 1986-10-14 Nec Ic Microcomput Syst Ltd 半導体記憶装置
JPS6341048A (ja) * 1986-08-06 1988-02-22 Mitsubishi Electric Corp 標準セル方式大規模集積回路
JPH07105445B2 (ja) * 1988-08-15 1995-11-13 株式会社東芝 集積回路の配線構造
JPH0369163A (ja) * 1989-08-08 1991-03-25 Nec Corp 半導体集積回路装置
JPH03177066A (ja) * 1989-12-06 1991-08-01 Nissan Motor Co Ltd 半導体集積回路装置
JPH0677403A (ja) * 1992-08-26 1994-03-18 Mitsubishi Electric Corp 半導体集積回路装置及びその設計方法

Also Published As

Publication number Publication date
JPH0758301A (ja) 1995-03-03
EP0827207B1 (de) 2003-03-12
DE69432270T2 (de) 2003-12-04
EP0638936A1 (de) 1995-02-15
DE69432270D1 (de) 2003-04-17
US5506428A (en) 1996-04-09
DE69428649T2 (de) 2002-06-20
KR950007060A (ko) 1995-03-21
EP0638936B1 (de) 2001-10-17
EP0827207A2 (de) 1998-03-04
KR100303222B1 (ko) 2001-12-01
EP0827207A3 (de) 1998-03-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee