DE3583972D1 - Kanalunterbrecher aus metallsilizid fuer integrierte schaltungen und verfahren zu deren herstellung. - Google Patents

Kanalunterbrecher aus metallsilizid fuer integrierte schaltungen und verfahren zu deren herstellung.

Info

Publication number
DE3583972D1
DE3583972D1 DE8585105719T DE3583972T DE3583972D1 DE 3583972 D1 DE3583972 D1 DE 3583972D1 DE 8585105719 T DE8585105719 T DE 8585105719T DE 3583972 T DE3583972 T DE 3583972T DE 3583972 D1 DE3583972 D1 DE 3583972D1
Authority
DE
Germany
Prior art keywords
production
integrated circuits
metal silicide
interrupter made
channel interrupter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585105719T
Other languages
English (en)
Inventor
George Richard Goth
Thomas Adrian Hansen
Villeto, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3583972D1 publication Critical patent/DE3583972D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/086—Isolated zones

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8585105719T 1984-06-29 1985-05-10 Kanalunterbrecher aus metallsilizid fuer integrierte schaltungen und verfahren zu deren herstellung. Expired - Fee Related DE3583972D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/626,278 US4589193A (en) 1984-06-29 1984-06-29 Metal silicide channel stoppers for integrated circuits and method for making the same

Publications (1)

Publication Number Publication Date
DE3583972D1 true DE3583972D1 (de) 1991-10-10

Family

ID=24509717

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585105719T Expired - Fee Related DE3583972D1 (de) 1984-06-29 1985-05-10 Kanalunterbrecher aus metallsilizid fuer integrierte schaltungen und verfahren zu deren herstellung.

Country Status (4)

Country Link
US (1) US4589193A (de)
EP (1) EP0166142B1 (de)
JP (1) JPS6119145A (de)
DE (1) DE3583972D1 (de)

Families Citing this family (52)

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US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US4663832A (en) * 1984-06-29 1987-05-12 International Business Machines Corporation Method for improving the planarity and passivation in a semiconductor isolation trench arrangement
FR2569055B1 (fr) * 1984-08-07 1986-12-12 Commissariat Energie Atomique Circuit integre cmos et procede de fabrication de zones d'isolation electriques dans ce circuit integre
JPS61191043A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置
US4696097A (en) * 1985-10-08 1987-09-29 Motorola, Inc. Poly-sidewall contact semiconductor device method
US4704368A (en) * 1985-10-30 1987-11-03 International Business Machines Corporation Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor
US4725562A (en) * 1986-03-27 1988-02-16 International Business Machines Corporation Method of making a contact to a trench isolated device
US4713358A (en) * 1986-05-02 1987-12-15 Gte Laboratories Incorporated Method of fabricating recessed gate static induction transistors
US4941026A (en) * 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US5082795A (en) * 1986-12-05 1992-01-21 General Electric Company Method of fabricating a field effect semiconductor device having a self-aligned structure
US4796070A (en) * 1987-01-15 1989-01-03 General Electric Company Lateral charge control semiconductor device and method of fabrication
US4984048A (en) * 1987-07-10 1991-01-08 Hitachi, Ltd. Semiconductor device with buried side contact
US4877757A (en) * 1987-07-16 1989-10-31 Texas Instruments Incorporated Method of sequential cleaning and passivating a GaAs substrate using remote oxygen plasma
US4855804A (en) * 1987-11-17 1989-08-08 Motorola, Inc. Multilayer trench isolation process and structure
US4871689A (en) * 1987-11-17 1989-10-03 Motorola Inc. Multilayer trench isolation process and structure
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
JPH0736424B2 (ja) * 1988-12-17 1995-04-19 日本電気株式会社 読み出し専用半導体記憶装置の製造方法
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate
US5254873A (en) * 1991-12-09 1993-10-19 Motorola, Inc. Trench structure having a germanium silicate region
US5521422A (en) * 1994-12-02 1996-05-28 International Business Machines Corporation Corner protected shallow trench isolation device
US6750091B1 (en) 1996-03-01 2004-06-15 Micron Technology Diode formation method
US5770878A (en) 1996-04-10 1998-06-23 Harris Corporation Trench MOS gate device
US5914280A (en) 1996-12-23 1999-06-22 Harris Corporation Deep trench etch on bonded silicon wafer
US5994202A (en) * 1997-01-23 1999-11-30 International Business Machines Corporation Threshold voltage tailoring of the corner of a MOSFET device
US5933717A (en) * 1997-03-04 1999-08-03 Advanced Micro Devices, Inc. Vertical transistor interconnect structure and fabrication method thereof
US6069384A (en) * 1997-03-04 2000-05-30 Advanced Micro Devices, Inc. Integrated circuit including vertical transistors with spacer gates having selected gate widths
US6387810B2 (en) * 1999-06-28 2002-05-14 International Business Machines Corporation Method for homogenizing device parameters through photoresist planarization
DE10109218A1 (de) * 2001-02-26 2002-06-27 Infineon Technologies Ag Verfahren zur Herstellung eines Speicherkondensators
AU2003288682A1 (en) * 2003-01-31 2004-08-23 Koninklijke Philips Electronics N.V. Trench isolation structure, semiconductor assembly comprising such a trench isolation, and method for forming such a trench isolation
US7812423B2 (en) * 2003-08-12 2010-10-12 Massachusetts Institute Of Technology Optical device comprising crystalline semiconductor layer and reflective element
US7002190B1 (en) * 2004-09-21 2006-02-21 International Business Machines Corporation Method of collector formation in BiCMOS technology
US20070116629A1 (en) * 2005-09-15 2007-05-24 Avetik Harutyunyan Methods for synthesis of high quality carbon single-walled nanotubes
US7335927B2 (en) * 2006-01-30 2008-02-26 Internatioanl Business Machines Corporation Lateral silicided diodes
US7795124B2 (en) 2006-06-23 2010-09-14 Applied Materials, Inc. Methods for contact resistance reduction of advanced CMOS devices
JP2009099815A (ja) * 2007-10-18 2009-05-07 Toshiba Corp 半導体装置の製造方法
US8338265B2 (en) * 2008-11-12 2012-12-25 International Business Machines Corporation Silicided trench contact to buried conductive layer
JP5773624B2 (ja) * 2010-01-08 2015-09-02 キヤノン株式会社 微細構造体の製造方法
JP5585662B2 (ja) * 2010-12-21 2014-09-10 コニカミノルタ株式会社 金属格子の製造方法ならびに該製造方法によって製造された金属格子およびこの金属格子を用いたｘ線撮像装置
US8927423B2 (en) 2011-12-16 2015-01-06 Applied Materials, Inc. Methods for annealing a contact metal layer to form a metal silicidation layer
US8586479B2 (en) 2012-01-23 2013-11-19 Applied Materials, Inc. Methods for forming a contact metal layer in semiconductor devices
US9330939B2 (en) 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
TWI633604B (zh) 2013-09-27 2018-08-21 美商應用材料股份有限公司 實現無縫鈷間隙塡充之方法
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
WO2019036157A1 (en) 2017-08-18 2019-02-21 Applied Materials, Inc. HIGH PRESSURE AND HIGH TEMPERATURE RECOVERY CHAMBER
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
KR102396319B1 (ko) 2017-11-11 2022-05-09 마이크로머티어리얼즈 엘엘씨 고압 프로세싱 챔버를 위한 가스 전달 시스템
JP2021503714A (ja) 2017-11-17 2021-02-12 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 高圧処理システムのためのコンデンサシステム
KR102536820B1 (ko) 2018-03-09 2023-05-24 어플라이드 머티어리얼스, 인코포레이티드 금속 함유 재료들을 위한 고압 어닐링 프로세스
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film

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US3381182A (en) * 1964-10-19 1968-04-30 Philco Ford Corp Microcircuits having buried conductive layers
US3659162A (en) * 1968-12-27 1972-04-25 Nippon Electric Co Semiconductor integrated circuit device having improved wiring layer structure
US3653120A (en) * 1970-07-27 1972-04-04 Gen Electric Method of making low resistance polycrystalline silicon contacts to buried collector regions using refractory metal silicides
JPS4914797A (de) * 1972-06-09 1974-02-08
DE3265339D1 (en) * 1981-03-20 1985-09-19 Toshiba Kk Method for manufacturing semiconductor device
US4446476A (en) * 1981-06-30 1984-05-01 International Business Machines Corporation Integrated circuit having a sublayer electrical contact and fabrication thereof
US4476622A (en) * 1981-12-24 1984-10-16 Gte Laboratories Inc. Recessed gate static induction transistor fabrication
US4473598A (en) * 1982-06-30 1984-09-25 International Business Machines Corporation Method of filling trenches with silicon and structures
US4519128A (en) * 1983-10-05 1985-05-28 International Business Machines Corporation Method of making a trench isolated device
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US4663832A (en) * 1984-06-29 1987-05-12 International Business Machines Corporation Method for improving the planarity and passivation in a semiconductor isolation trench arrangement

Also Published As

Publication number Publication date
US4589193A (en) 1986-05-20
EP0166142A2 (de) 1986-01-02
JPS6119145A (ja) 1986-01-28
EP0166142A3 (en) 1988-09-21
EP0166142B1 (de) 1991-09-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee