IT1258284B - Struttura di interconnessione di un dispositivo a circuito integrato asemicondutture e suo prcedimento di fabbricazione - Google Patents
Struttura di interconnessione di un dispositivo a circuito integrato asemicondutture e suo prcedimento di fabbricazioneInfo
- Publication number
- IT1258284B IT1258284B ITMI920845A ITMI920845A IT1258284B IT 1258284 B IT1258284 B IT 1258284B IT MI920845 A ITMI920845 A IT MI920845A IT MI920845 A ITMI920845 A IT MI920845A IT 1258284 B IT1258284 B IT 1258284B
- Authority
- IT
- Italy
- Prior art keywords
- asemiconductures
- integrated circuit
- manufacturing process
- circuit device
- interconnection structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Professional, Industrial, Or Sporting Protective Garments (AREA)
Abstract
Un copriletto ad elevata adattabilità posizionabile al disopra di un letto provvisto di relativi cuscini, il quale viene realizzato in almeno un pezzo di tessuto elastico e/o non elastico e comprende essenzialmente una prima parte principale di copertura diretta del letto ed una seconda parte minore di copertura dei cuscini, la prima parte principale lungo suoi bordi longitudinali essendo dotata di plissettature o pieghettature atte ad attestarsi lungo spigoli longitudinali del letto.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3076544A JP2533414B2 (ja) | 1991-04-09 | 1991-04-09 | 半導体集積回路装置の配線接続構造およびその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI920845A0 ITMI920845A0 (it) | 1992-04-07 |
ITMI920845A1 ITMI920845A1 (it) | 1993-10-07 |
IT1258284B true IT1258284B (it) | 1996-02-22 |
Family
ID=13608211
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI920845A IT1258284B (it) | 1991-04-09 | 1992-04-07 | Struttura di interconnessione di un dispositivo a circuito integrato asemicondutture e suo prcedimento di fabbricazione |
Country Status (5)
Country | Link |
---|---|
US (2) | US5341026A (it) |
JP (1) | JP2533414B2 (it) |
KR (1) | KR960009099B1 (it) |
DE (1) | DE4207916C2 (it) |
IT (1) | IT1258284B (it) |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2811126B2 (ja) * | 1991-05-02 | 1998-10-15 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
US5627345A (en) * | 1991-10-24 | 1997-05-06 | Kawasaki Steel Corporation | Multilevel interconnect structure |
JP2755035B2 (ja) * | 1992-03-28 | 1998-05-20 | ヤマハ株式会社 | 多層配線形成法 |
US5635763A (en) * | 1993-03-22 | 1997-06-03 | Sanyo Electric Co., Ltd. | Semiconductor device having cap-metal layer |
JP3401843B2 (ja) * | 1993-06-21 | 2003-04-28 | ソニー株式会社 | 半導体装置における多層配線の形成方法 |
JPH07135188A (ja) * | 1993-11-11 | 1995-05-23 | Toshiba Corp | 半導体装置の製造方法 |
KR970007967B1 (en) * | 1994-05-11 | 1997-05-19 | Hyundai Electronics Ind | Fabrication method and semiconductor device |
JP3599199B2 (ja) | 1994-08-31 | 2004-12-08 | 富士通株式会社 | 多層配線を有する半導体装置の製造方法 |
JP2663887B2 (ja) * | 1994-11-29 | 1997-10-15 | 日本電気株式会社 | 不揮発性半導体記憶装置 |
TW287313B (it) * | 1995-02-20 | 1996-10-01 | Matsushita Electric Ind Co Ltd | |
US5858184A (en) * | 1995-06-07 | 1999-01-12 | Applied Materials, Inc. | Process for forming improved titanium-containing barrier layers |
US5518959A (en) * | 1995-08-24 | 1996-05-21 | Taiwan Semiconductor Manufacturing Company | Method for selectively depositing silicon oxide spacer layers |
US6726776B1 (en) | 1995-11-21 | 2004-04-27 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US5877087A (en) | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
US6066358A (en) * | 1995-11-21 | 2000-05-23 | Applied Materials, Inc. | Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer |
US6077781A (en) * | 1995-11-21 | 2000-06-20 | Applied Materials, Inc. | Single step process for blanket-selective CVD aluminum deposition |
US6825132B1 (en) | 1996-02-29 | 2004-11-30 | Sanyo Electric Co., Ltd. | Manufacturing method of semiconductor device including an insulation film on a conductive layer |
JP3015752B2 (ja) * | 1996-02-29 | 2000-03-06 | 三洋電機株式会社 | 半導体装置の製造方法 |
FR2747511B1 (fr) * | 1996-04-10 | 1998-09-04 | Sgs Thomson Microelectronics | Interconnexions multicouches a faible capacite parasite laterale |
US5843839A (en) * | 1996-04-29 | 1998-12-01 | Chartered Semiconductor Manufacturing, Ltd. | Formation of a metal via using a raised metal plug structure |
JPH1064902A (ja) * | 1996-07-12 | 1998-03-06 | Applied Materials Inc | アルミニウム材料の成膜方法及び成膜装置 |
US5693565A (en) * | 1996-07-15 | 1997-12-02 | Dow Corning Corporation | Semiconductor chips suitable for known good die testing |
JPH1065118A (ja) * | 1996-08-19 | 1998-03-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
KR100383498B1 (ko) | 1996-08-30 | 2003-08-19 | 산요 덴키 가부시키가이샤 | 반도체 장치 제조방법 |
US6288438B1 (en) | 1996-09-06 | 2001-09-11 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6001420A (en) * | 1996-09-23 | 1999-12-14 | Applied Materials, Inc. | Semi-selective chemical vapor deposition |
JP3015767B2 (ja) * | 1996-12-25 | 2000-03-06 | 三洋電機株式会社 | 半導体装置の製造方法及び半導体装置 |
US6537905B1 (en) | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
US5844318A (en) | 1997-02-18 | 1998-12-01 | Micron Technology, Inc. | Aluminum film for semiconductive devices |
US6096637A (en) * | 1997-02-25 | 2000-08-01 | Compaq Computer Corporation | Electromigration-resistant via structure |
US6139905A (en) * | 1997-04-11 | 2000-10-31 | Applied Materials, Inc. | Integrated CVD/PVD Al planarization using ultra-thin nucleation layers |
EP0875923A3 (en) * | 1997-04-30 | 1999-11-03 | International Business Machines Corporation | Multilayer metallization structure comprising a group IVA metal |
US5932928A (en) * | 1997-07-03 | 1999-08-03 | Micron Technology, Inc. | Semiconductor circuit interconnections and methods of making such interconnections |
US6081033A (en) * | 1997-07-29 | 2000-06-27 | Micron Technology, Inc. | Interconnections for semiconductor circuits |
US5989623A (en) | 1997-08-19 | 1999-11-23 | Applied Materials, Inc. | Dual damascene metallization |
US6828230B2 (en) | 1997-09-12 | 2004-12-07 | Micron Technology, Inc. | Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same |
US5994775A (en) * | 1997-09-17 | 1999-11-30 | Lsi Logic Corporation | Metal-filled via/contact opening with thin barrier layers in integrated circuit structure for fast response, and process for making same |
JP2975934B2 (ja) | 1997-09-26 | 1999-11-10 | 三洋電機株式会社 | 半導体装置の製造方法及び半導体装置 |
US6690084B1 (en) | 1997-09-26 | 2004-02-10 | Sanyo Electric Co., Ltd. | Semiconductor device including insulation film and fabrication method thereof |
US6120842A (en) * | 1997-10-21 | 2000-09-19 | Texas Instruments Incorporated | TiN+Al films and processes |
US6376369B1 (en) | 1998-02-12 | 2002-04-23 | Micron Technology, Inc. | Robust pressure aluminum fill process |
US6794283B2 (en) | 1998-05-29 | 2004-09-21 | Sanyo Electric Co., Ltd. | Semiconductor device and fabrication method thereof |
US6136670A (en) * | 1998-09-03 | 2000-10-24 | Micron Technology, Inc. | Semiconductor processing methods of forming contacts between electrically conductive materials |
US6278153B1 (en) * | 1998-10-19 | 2001-08-21 | Nec Corporation | Thin film capacitor formed in via |
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
JP3179065B2 (ja) * | 1999-02-02 | 2001-06-25 | 宮崎沖電気株式会社 | 半導体素子の製造方法 |
US6833623B2 (en) * | 1999-08-11 | 2004-12-21 | Micron Technology, Inc. | Enhanced barrier liner formation for via |
US6207558B1 (en) | 1999-10-21 | 2001-03-27 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
DE19958200B4 (de) * | 1999-12-02 | 2006-07-06 | Infineon Technologies Ag | Mikroelektronische Struktur und Verfahren zu deren Herstellung |
US6459156B1 (en) * | 1999-12-22 | 2002-10-01 | Motorola, Inc. | Semiconductor device, a process for a semiconductor device, and a process for making a masking database |
US6794705B2 (en) * | 2000-12-28 | 2004-09-21 | Infineon Technologies Ag | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials |
JP2003068848A (ja) * | 2001-08-29 | 2003-03-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6917110B2 (en) * | 2001-12-07 | 2005-07-12 | Sanyo Electric Co., Ltd. | Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer |
US6797620B2 (en) * | 2002-04-16 | 2004-09-28 | Applied Materials, Inc. | Method and apparatus for improved electroplating fill of an aperture |
KR100463178B1 (ko) * | 2002-04-19 | 2004-12-23 | 아남반도체 주식회사 | 반도체 소자의 금속배선 적층구조 형성 방법 |
KR100669688B1 (ko) * | 2003-03-12 | 2007-01-18 | 삼성에스디아이 주식회사 | 박막트랜지스터 및 이를 구비한 평판표시소자 |
JP4038485B2 (ja) * | 2003-03-12 | 2008-01-23 | 三星エスディアイ株式会社 | 薄膜トランジスタを備えた平板表示素子 |
KR100506943B1 (ko) * | 2003-09-09 | 2005-08-05 | 삼성전자주식회사 | 식각정지막으로 연결홀의 저측면에 경사를 갖는 반도체소자의 제조 방법들 |
US7170176B2 (en) * | 2003-11-04 | 2007-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
TWI475667B (zh) * | 2005-03-28 | 2015-03-01 | Semiconductor Energy Lab | 記憶裝置和其製造方法 |
US8003536B2 (en) * | 2009-03-18 | 2011-08-23 | International Business Machines Corporation | Electromigration resistant aluminum-based metal interconnect structure |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4300149A (en) * | 1979-09-04 | 1981-11-10 | International Business Machines Corporation | Gold-tantalum-titanium/tungsten alloy contact for semiconductor devices and having a gold/tantalum intermetallic barrier region intermediate the gold and alloy elements |
JPS58137231A (ja) * | 1982-02-09 | 1983-08-15 | Nec Corp | 集積回路装置 |
JPS59212107A (ja) * | 1983-05-18 | 1984-12-01 | Ishikawajima Harima Heavy Ind Co Ltd | ロ−ルの温度制御装置 |
JPS6190445A (ja) * | 1984-10-09 | 1986-05-08 | Nec Corp | 半導体装置 |
US5278099A (en) * | 1985-05-13 | 1994-01-11 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having wiring electrodes |
JP2581097B2 (ja) * | 1987-08-31 | 1997-02-12 | ソニー株式会社 | 半導体装置 |
JP2598335B2 (ja) * | 1990-08-28 | 1997-04-09 | 三菱電機株式会社 | 半導体集積回路装置の配線接続構造およびその製造方法 |
-
1991
- 1991-04-09 JP JP3076544A patent/JP2533414B2/ja not_active Expired - Lifetime
-
1992
- 1992-02-26 US US07/842,019 patent/US5341026A/en not_active Expired - Lifetime
- 1992-03-12 DE DE4207916A patent/DE4207916C2/de not_active Expired - Lifetime
- 1992-04-07 IT ITMI920845A patent/IT1258284B/it active IP Right Grant
- 1992-04-08 KR KR1019920005800A patent/KR960009099B1/ko not_active IP Right Cessation
-
1994
- 1994-06-03 US US08/254,085 patent/US5480836A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE4207916C2 (de) | 1994-06-30 |
US5480836A (en) | 1996-01-02 |
ITMI920845A1 (it) | 1993-10-07 |
ITMI920845A0 (it) | 1992-04-07 |
DE4207916A1 (de) | 1992-10-15 |
KR960009099B1 (ko) | 1996-07-10 |
JP2533414B2 (ja) | 1996-09-11 |
US5341026A (en) | 1994-08-23 |
KR920020620A (ko) | 1992-11-21 |
JPH04311058A (ja) | 1992-11-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
IT1258284B (it) | Struttura di interconnessione di un dispositivo a circuito integrato asemicondutture e suo prcedimento di fabbricazione | |
DE69231179D1 (de) | Polstermatraze gegen das wundliegen | |
ATE218828T1 (de) | Streugut eingeschlossen in elastisch laminierten, wasserfesten und wasserundurchlässigen allergieschranken | |
AT385647B (de) | Matratze | |
NO840027L (no) | Understoettelse for kroppsleie | |
DE50003336D1 (de) | Liegefläche mit Lamellenrost | |
ITMI911315A1 (it) | Corpo di cuscino e procedimento per la formazione del medesimo | |
IT9003393A0 (it) | Imbottitura per cuscini e materassi | |
DE59207975D1 (de) | Flächiger Polsterkörper, insbesondere Matratze | |
AT388093B (de) | Federkern fuer matratzen und polstermoebel | |
IT8448446A0 (it) | Dispositivo per regolare l'inclinazione delle sezioni del piano di un letto, particolarmente per letti delle case di cura e simili | |
SE9102264D0 (sv) | Patientanordning vid saeng | |
GB2013489A (en) | Improvements in or Relating to Beds | |
NO884608D0 (no) | Underlagsmadrass for konvensjonelle madrasser. | |
KR920003903U (ko) | 침대의 매트리스 받침대 | |
IT1240892B (it) | Lettino per bambini a spondina laterale mobile | |
KR960003844U (ko) | 침대용 매트리스의 모서리 보조스프링 | |
ITMI912270A1 (it) | Cuccetta convertibile in poltrona | |
IT219525Z2 (it) | Attacco per cinghie o nastri elastici in particolare per mobili imbottiti | |
KR920017577U (ko) | 하절용 침대 매트리스 | |
ITMI930969U1 (it) | Corredo per letti ad elevata confortevolezza e semplicita' di impiego | |
ITUD940177A0 (it) | Gruppo a copiare per levigatura di bordi perimetrali di tavoli e/o sedili sedie | |
ES1015193Y (es) | Dispositivo para elevacion parcial de colchones en camas. | |
SE9600882D0 (sv) | Säng med nattduksbord | |
SE9700372D0 (sv) | Säng med nattduksbord |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970429 |