IT1255431B - Moltiplicatore controllato in tecnologia mosfet - Google Patents

Moltiplicatore controllato in tecnologia mosfet

Info

Publication number
IT1255431B
IT1255431B ITMI921727A ITMI921727A IT1255431B IT 1255431 B IT1255431 B IT 1255431B IT MI921727 A ITMI921727 A IT MI921727A IT MI921727 A ITMI921727 A IT MI921727A IT 1255431 B IT1255431 B IT 1255431B
Authority
IT
Italy
Prior art keywords
mosfet
voltage
input voltage
symmetrical
linear
Prior art date
Application number
ITMI921727A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of ITMI921727A0 publication Critical patent/ITMI921727A0/it
Publication of ITMI921727A1 publication Critical patent/ITMI921727A1/it
Application granted granted Critical
Publication of IT1255431B publication Critical patent/IT1255431B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Software Systems (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Power Engineering (AREA)
  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Abstract

L'invenzione riguarda un moltiplicatore controllato in tecnologia MOSFET destinato ad ottenere la funzione precisa della moltiplicazione operazionale, compensando la tensione di offset del MOSFET, così da eliminare la corrente non lineare del MOSFET utilizzando delle sorgenti di tensione simmetriche ed uno specchio di corrente. Il moltiplicatore controllato MOSFET usa un mezzo lineare MOSFET per variare linearmente la corrente di uscita I da un nodo A, dipendente da una tensione di ingresso proveniente da una sorgente di tensione di ingresso Vg e da una tensione di ingresso simmetrica, proveniente dalle sorgenti di tensione Vx e -Vx. La tensione di ingresso proveniente dalla sorgente di ingresso Vg è associata operativamente alla tensione di ingresso simmetrica proveniente dalle sorgenti di tensione Vx e -Vx. Un elemento di impedenza Z, collegato tra il nodo A del mezzo lineare MOSFET e terra, produce una tensione Vo.
ITMI921727A 1991-11-01 1992-07-16 Moltiplicatore controllato in tecnologia mosfet IT1255431B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019375A KR940004430B1 (ko) 1991-11-01 1991-11-01 Mosfet 저항성 제어형 곱셈연산기

Publications (3)

Publication Number Publication Date
ITMI921727A0 ITMI921727A0 (it) 1992-07-16
ITMI921727A1 ITMI921727A1 (it) 1994-01-16
IT1255431B true IT1255431B (it) 1995-10-31

Family

ID=19322149

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921727A IT1255431B (it) 1991-11-01 1992-07-16 Moltiplicatore controllato in tecnologia mosfet

Country Status (18)

Country Link
US (1) US5237289A (it)
JP (1) JPH0690736B2 (it)
KR (1) KR940004430B1 (it)
AT (1) AT398010B (it)
BE (1) BE1005270A5 (it)
CH (1) CH684665A5 (it)
DE (1) DE4222846C2 (it)
DK (1) DK81992A (it)
ES (1) ES2040659B1 (it)
FR (1) FR2683353B1 (it)
GB (1) GB2261093B (it)
GR (1) GR1002150B (it)
IT (1) IT1255431B (it)
LU (1) LU88148A1 (it)
MC (1) MC2322A1 (it)
NL (1) NL9201248A (it)
PT (1) PT100693A (it)
SE (1) SE9201883L (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0548354A (ja) * 1991-08-19 1993-02-26 Matsushita Electric Ind Co Ltd 利得制御回路および半導体装置
EP0766187B1 (en) * 1995-09-27 2001-11-28 STMicroelectronics S.r.l. Low-power, low-voltage four-quadrant analog multiplier, particularly for neural applications
US5720004A (en) * 1995-09-29 1998-02-17 United Microelectronics Corporation Current-mode hamming neural network
US5917368A (en) * 1996-05-08 1999-06-29 Telefonatiebolaget Lm Ericsson Voltage-to-current converter
KR100219036B1 (ko) * 1996-09-30 1999-09-01 이계철 저전압형 모스펫 콘트롤링 곱셈기
KR100219037B1 (ko) * 1996-10-01 1999-09-01 이계철 선형화된 저항성을 이용한 모스펫 아날로그 곱셈기
JP3545142B2 (ja) * 1996-11-25 2004-07-21 三菱電機株式会社 差動増幅器
FR2769388B1 (fr) * 1997-10-07 2001-08-03 Korea Telecomm Authority Multiplieur et synapse de reseau neuronal utilisant un miroir de courant comportant des transistors a effet de champ mos de faible puissance

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4032767A (en) * 1976-02-26 1977-06-28 The United States Of America As Represented By The Secretary Of The Navy High-frequency ccd adder and multiplier
US4156923A (en) * 1977-10-17 1979-05-29 Westinghouse Electric Corp. Method and apparatus for performing matrix multiplication or analog signal correlation
US4760349A (en) * 1986-08-19 1988-07-26 Regents Of The University Of Minnesota CMOS analog standard cell arrays using linear transconductance elements
US4837527A (en) * 1987-12-23 1989-06-06 Rca Licensing Corporation Switched capacitor arrangement
US4825174A (en) * 1988-06-20 1989-04-25 American Telephone And Telegraph Company, At&T Bell Laboratories Symmetric integrated amplifier with controlled DC offset voltage
US4931674A (en) * 1988-11-16 1990-06-05 United States Of America As Represented By The Secretary Of The Navy Programmable analog voltage multiplier circuit means
US4906873A (en) * 1989-01-12 1990-03-06 The United States Of America As Represented By The Secretary Of The Navy CMOS analog four-quadrant multiplier
JPH02287670A (ja) * 1989-04-27 1990-11-27 Mitsubishi Electric Corp 半導体神経回路網
JPH02311972A (ja) * 1989-05-29 1990-12-27 Matsushita Electric Ind Co Ltd ニューロン素子回路
JPH04500424A (ja) * 1989-06-15 1992-01-23 ゼネラル・エレクトリック・カンパニイ 入力又は出力線及び差別的な感知又は被動出力又は入力線の対を接続する容量性構造を用いた神経網
US4978873A (en) * 1989-10-11 1990-12-18 The United States Of America As Represented By The Secretary Of The Navy CMOS analog four-quadrant multiplier
US5061866A (en) * 1990-08-06 1991-10-29 The Ohio State University Research Foundation Analog, continuous time vector scalar multiplier circuits and programmable feedback neural network using them
US5097156A (en) * 1991-04-11 1992-03-17 The United States Of America As Represented By The Secretary Of The Navy Circuitry for compensating for transistor parameter mismatches in a CMOS analog four-quadrant multiplier

Also Published As

Publication number Publication date
FR2683353B1 (fr) 1997-03-28
ES2040659B1 (es) 1996-11-01
DK81992A (da) 1993-05-02
BE1005270A5 (fr) 1993-06-15
ES2040659R (it) 1996-03-01
DE4222846C2 (de) 1995-06-22
GB2261093A (en) 1993-05-05
SE9201883L (sv) 1993-05-02
NL9201248A (nl) 1993-06-01
ES2040659A2 (es) 1993-10-16
DK81992D0 (da) 1992-06-22
SE9201883D0 (sv) 1992-06-18
FR2683353A1 (fr) 1993-05-07
US5237289A (en) 1993-08-17
LU88148A1 (fr) 1993-02-15
GB9213382D0 (en) 1992-08-05
JPH05225365A (ja) 1993-09-03
AT398010B (de) 1994-08-25
MC2322A1 (fr) 1993-10-25
GR920100399A (el) 1993-07-30
ATA144692A (de) 1993-12-15
KR930011429A (ko) 1993-06-24
JPH0690736B2 (ja) 1994-11-14
GB2261093B (en) 1995-06-21
ITMI921727A0 (it) 1992-07-16
GR1002150B (en) 1996-02-20
ITMI921727A1 (it) 1994-01-16
KR940004430B1 (ko) 1994-05-25
CH684665A5 (de) 1994-11-15
DE4222846A1 (de) 1993-05-06
PT100693A (pt) 1994-05-31

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730