IT1244971B - Mezzi a ridondanza per un dispositivo di memoria a semiconduttori e relativo procedimento - Google Patents
Mezzi a ridondanza per un dispositivo di memoria a semiconduttori e relativo procedimentoInfo
- Publication number
- IT1244971B IT1244971B ITRM910243A ITRM910243A IT1244971B IT 1244971 B IT1244971 B IT 1244971B IT RM910243 A ITRM910243 A IT RM910243A IT RM910243 A ITRM910243 A IT RM910243A IT 1244971 B IT1244971 B IT 1244971B
- Authority
- IT
- Italy
- Prior art keywords
- array
- cells
- signal
- redundant
- redundancy
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
Landscapes
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Viene illustrato un dispositivo ridondante per un dispositivo di memoria a semiconduttori comprendente una molteplicità di schiere di celle normali ciascuna avente amplificatore di percezione comprendente una porta di isolamento per isolare o collegare le linee di bit tra quelle adiacenti delle schiere di celle normali in risposta ad un segnale di isolamento, una schiera di celle a ridondanza collegata soltanto con una delle schiere adiacenti di celle ridondanti, un dispositivo di generazione di segnale di controllo per generare il segnale di isolamento ed un segnale di percezione per controllare rispettivamente gli amplificatori di percezione corrispondenti alla schiera di celle normali collegate con la schiera di celle ridondanti e la schiera di celle normali non collegate con la schiera di celle ridondanti, e un dispositivo per generare un segnale di controllo di ridondanza in risposta ad un difetto di un segnale di indirizzo impostato dall'esterno ed un segnale per selezionare una linea di parola della schiera di celle ridondanti.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900021502A KR940008208B1 (ko) | 1990-12-22 | 1990-12-22 | 반도체 메모리장치의 리던던트 장치 및 방법 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITRM910243A0 ITRM910243A0 (it) | 1991-04-10 |
ITRM910243A1 ITRM910243A1 (it) | 1992-10-10 |
IT1244971B true IT1244971B (it) | 1994-09-13 |
Family
ID=19308222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITRM910243A IT1244971B (it) | 1990-12-22 | 1991-04-10 | Mezzi a ridondanza per un dispositivo di memoria a semiconduttori e relativo procedimento |
Country Status (9)
Country | Link |
---|---|
US (1) | US5255234A (it) |
JP (1) | JPH076598A (it) |
KR (1) | KR940008208B1 (it) |
CN (1) | CN1023266C (it) |
DE (1) | DE4111708A1 (it) |
FR (1) | FR2670943B1 (it) |
GB (1) | GB2251101B (it) |
IT (1) | IT1244971B (it) |
NL (1) | NL9100620A (it) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950001837B1 (ko) * | 1992-07-13 | 1995-03-03 | 삼성전자주식회사 | 퓨우즈 박스를 공유하는 로우 리던던시 회로 |
US5557618A (en) * | 1993-01-19 | 1996-09-17 | Tektronix, Inc. | Signal sampling circuit with redundancy |
JP3257860B2 (ja) * | 1993-05-17 | 2002-02-18 | 株式会社日立製作所 | 半導体メモリ装置 |
JP3273440B2 (ja) * | 1994-10-19 | 2002-04-08 | マイクロン・テクノロジー・インコーポレーテッド | 部分的に良好なメモリ集積回路から使用可能な部分を得るための効率的な方法 |
KR0140177B1 (ko) * | 1994-12-29 | 1998-07-15 | 김광호 | 반도체메모리소자의 메모리셀어레이의 배열방법 |
JP3036411B2 (ja) * | 1995-10-18 | 2000-04-24 | 日本電気株式会社 | 半導体記憶集積回路装置 |
US5946257A (en) * | 1996-07-24 | 1999-08-31 | Micron Technology, Inc. | Selective power distribution circuit for an integrated circuit |
US5970013A (en) * | 1998-02-26 | 1999-10-19 | Lucent Technologies Inc. | Adaptive addressable circuit redundancy method and apparatus with broadcast write |
US6011733A (en) * | 1998-02-26 | 2000-01-04 | Lucent Technologies Inc. | Adaptive addressable circuit redundancy method and apparatus |
US6438672B1 (en) | 1999-06-03 | 2002-08-20 | Agere Systems Guardian Corp. | Memory aliasing method and apparatus |
US6188624B1 (en) * | 1999-07-12 | 2001-02-13 | Winbond Electronics Corporation | Low latency memory sensing circuits |
US7095642B1 (en) * | 2003-03-27 | 2006-08-22 | Cypress Semiconductor Corporation | Method and circuit for reducing defect current from array element failures in random access memories |
EP1720172B1 (en) * | 2004-02-20 | 2012-06-06 | Spansion LLc | Semiconductor storage device and redundancy control method for semiconductor storage device |
WO2005081260A1 (ja) * | 2004-02-20 | 2005-09-01 | Spansion Llc | 半導体記憶装置および半導体記憶装置の冗長方法 |
US8072834B2 (en) | 2005-08-25 | 2011-12-06 | Cypress Semiconductor Corporation | Line driver circuit and method with standby mode of operation |
JP4781783B2 (ja) * | 2005-10-31 | 2011-09-28 | エルピーダメモリ株式会社 | 半導体記憶装置 |
KR100675299B1 (ko) * | 2006-02-15 | 2007-01-29 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 데이터 라이트 및 리드방법 |
US7505319B2 (en) * | 2007-01-31 | 2009-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for high efficiency redundancy scheme for multi-segment SRAM |
US20110134707A1 (en) * | 2007-11-02 | 2011-06-09 | Saeng Hwan Kim | Block isolation control circuit |
JP5539916B2 (ja) * | 2011-03-04 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9478316B1 (en) * | 2016-01-08 | 2016-10-25 | SK Hynix Inc. | Memory device |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4228528B2 (en) * | 1979-02-09 | 1992-10-06 | Memory with redundant rows and columns | |
JPS563499A (en) * | 1979-06-25 | 1981-01-14 | Fujitsu Ltd | Semiconductor memory device |
US4281398A (en) * | 1980-02-12 | 1981-07-28 | Mostek Corporation | Block redundancy for memory array |
US4389715A (en) * | 1980-10-06 | 1983-06-21 | Inmos Corporation | Redundancy scheme for a dynamic RAM |
JPS6141186A (ja) * | 1984-08-01 | 1986-02-27 | 松下電器産業株式会社 | カラ−デ−タ同時書込み装置 |
IE58219B1 (en) * | 1984-11-07 | 1993-08-11 | Procter & Gamble | Liquid detergent compositions |
JPS6226695A (ja) * | 1985-07-26 | 1987-02-04 | Nec Corp | 半導体メモリ |
JP2590897B2 (ja) * | 1987-07-20 | 1997-03-12 | 日本電気株式会社 | 半導体メモリ |
JPH01119995A (ja) * | 1987-11-02 | 1989-05-12 | Toshiba Corp | 半導体メモリ |
US4807191A (en) * | 1988-01-04 | 1989-02-21 | Motorola, Inc. | Redundancy for a block-architecture memory |
US5022006A (en) * | 1988-04-01 | 1991-06-04 | International Business Machines Corporation | Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells |
FR2644924A1 (fr) * | 1989-03-23 | 1990-09-28 | Sgs Thomson Microelectronics | Circuit de selection d'une colonne redondante dans une memoire integree avec redondance de colonnes de donnees |
-
1990
- 1990-12-22 KR KR1019900021502A patent/KR940008208B1/ko not_active IP Right Cessation
-
1991
- 1991-03-25 US US07/674,387 patent/US5255234A/en not_active Expired - Lifetime
- 1991-04-02 FR FR9103948A patent/FR2670943B1/fr not_active Expired - Lifetime
- 1991-04-09 NL NL9100620A patent/NL9100620A/nl not_active Application Discontinuation
- 1991-04-10 IT ITRM910243A patent/IT1244971B/it active IP Right Grant
- 1991-04-10 GB GB9107618A patent/GB2251101B/en not_active Expired - Lifetime
- 1991-04-10 DE DE4111708A patent/DE4111708A1/de active Granted
- 1991-04-10 CN CN91102517A patent/CN1023266C/zh not_active Expired - Lifetime
- 1991-11-22 JP JP3307539A patent/JPH076598A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
ITRM910243A1 (it) | 1992-10-10 |
GB2251101B (en) | 1995-03-22 |
FR2670943B1 (fr) | 1994-05-13 |
DE4111708C2 (it) | 1993-04-22 |
KR940008208B1 (ko) | 1994-09-08 |
GB2251101A (en) | 1992-06-24 |
DE4111708A1 (de) | 1992-07-02 |
JPH076598A (ja) | 1995-01-10 |
KR920013470A (ko) | 1992-07-29 |
GB9107618D0 (en) | 1991-05-29 |
CN1062613A (zh) | 1992-07-08 |
NL9100620A (nl) | 1992-07-16 |
FR2670943A1 (fr) | 1992-06-26 |
ITRM910243A0 (it) | 1991-04-10 |
US5255234A (en) | 1993-10-19 |
CN1023266C (zh) | 1993-12-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970328 |