IT1241318B - Dispositivo di indirizzamento di memoria - Google Patents

Dispositivo di indirizzamento di memoria

Info

Publication number
IT1241318B
IT1241318B IT67903A IT6790390A IT1241318B IT 1241318 B IT1241318 B IT 1241318B IT 67903 A IT67903 A IT 67903A IT 6790390 A IT6790390 A IT 6790390A IT 1241318 B IT1241318 B IT 1241318B
Authority
IT
Italy
Prior art keywords
memory addressing
addressing device
memory
addressing
Prior art date
Application number
IT67903A
Other languages
English (en)
Other versions
IT9067903A0 (it
IT9067903A1 (it
Inventor
Walter Cerutti
Original Assignee
Olivetti & Co Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti & Co Spa filed Critical Olivetti & Co Spa
Priority to IT67903A priority Critical patent/IT1241318B/it
Publication of IT9067903A0 publication Critical patent/IT9067903A0/it
Priority to EP91310505A priority patent/EP0487254B1/en
Priority to DE69129524T priority patent/DE69129524T2/de
Priority to JP3303328A priority patent/JPH04302041A/ja
Publication of IT9067903A1 publication Critical patent/IT9067903A1/it
Application granted granted Critical
Publication of IT1241318B publication Critical patent/IT1241318B/it
Priority to US08/344,634 priority patent/US5526513A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
IT67903A 1990-11-19 1990-11-19 Dispositivo di indirizzamento di memoria IT1241318B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT67903A IT1241318B (it) 1990-11-19 1990-11-19 Dispositivo di indirizzamento di memoria
EP91310505A EP0487254B1 (en) 1990-11-19 1991-11-14 Memory addressing device
DE69129524T DE69129524T2 (de) 1990-11-19 1991-11-14 Gerät zur Speicheradressierung
JP3303328A JPH04302041A (ja) 1990-11-19 1991-11-19 メモリーのアドレス指定デバイス
US08/344,634 US5526513A (en) 1990-11-19 1994-11-17 Memory addressing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67903A IT1241318B (it) 1990-11-19 1990-11-19 Dispositivo di indirizzamento di memoria

Publications (3)

Publication Number Publication Date
IT9067903A0 IT9067903A0 (it) 1990-11-19
IT9067903A1 IT9067903A1 (it) 1992-05-20
IT1241318B true IT1241318B (it) 1994-01-10

Family

ID=11306235

Family Applications (1)

Application Number Title Priority Date Filing Date
IT67903A IT1241318B (it) 1990-11-19 1990-11-19 Dispositivo di indirizzamento di memoria

Country Status (5)

Country Link
US (1) US5526513A (it)
EP (1) EP0487254B1 (it)
JP (1) JPH04302041A (it)
DE (1) DE69129524T2 (it)
IT (1) IT1241318B (it)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3579461B2 (ja) * 1993-10-15 2004-10-20 株式会社ルネサステクノロジ データ処理システム及びデータ処理装置
JP3153078B2 (ja) * 1994-09-09 2001-04-03 日本電気株式会社 データ処理装置
JP2630271B2 (ja) * 1994-09-14 1997-07-16 日本電気株式会社 情報処理装置
US5596731A (en) * 1995-04-21 1997-01-21 Cyrix Corporation Single clock bus transfers during burst and non-burst cycles
US5664140A (en) * 1995-05-19 1997-09-02 Micron Electronics, Inc. Processor to memory interface logic for use in a computer system using a multiplexed memory address
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6243768B1 (en) 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5893917A (en) * 1996-09-30 1999-04-13 Intel Corporation Memory controller and method of closing a page of system memory
US7146469B2 (en) * 2002-10-24 2006-12-05 Sony Corporation Method, apparatus, and system for improving memory access speed
US10931682B2 (en) 2015-06-30 2021-02-23 Microsoft Technology Licensing, Llc Privileged identity management
CN107221349B (zh) * 2017-08-03 2023-05-16 深圳市博巨兴微电子科技有限公司 一种基于flash存储器的微控制器芯片

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134699A (en) * 1988-06-24 1992-07-28 Advanced Micro Devices, Inc. Programmable burst data transfer apparatus and technique
US4912630A (en) * 1988-07-29 1990-03-27 Ncr Corporation Cache address comparator with sram having burst addressing control
US5131083A (en) * 1989-04-05 1992-07-14 Intel Corporation Method of transferring burst data in a microprocessor
US5170481A (en) * 1989-06-19 1992-12-08 International Business Machines Corporation Microprocessor hold and lock circuitry
US5321827A (en) * 1989-08-02 1994-06-14 Advanced Logic Research, Inc. Computer system with modular upgrade capability
EP0428149A3 (en) * 1989-11-13 1992-07-08 Matra Design Semiconductor, Inc. Cache controller
DE69123987T2 (de) * 1990-01-31 1997-04-30 Hewlett Packard Co Stossbetrieb für Mikroprozessor mit externem Systemspeicher
US5210845A (en) * 1990-11-28 1993-05-11 Intel Corporation Controller for two-way set associative cache
US5291580A (en) * 1991-10-04 1994-03-01 Bull Hn Information Systems Inc. High performance burst read data transfer operation

Also Published As

Publication number Publication date
IT9067903A0 (it) 1990-11-19
IT9067903A1 (it) 1992-05-20
JPH04302041A (ja) 1992-10-26
DE69129524T2 (de) 1998-11-12
EP0487254A3 (en) 1993-03-31
US5526513A (en) 1996-06-11
EP0487254A2 (en) 1992-05-27
EP0487254B1 (en) 1998-06-03
DE69129524D1 (de) 1998-07-09

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129