IN168174B - - Google Patents

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Publication number
IN168174B
IN168174B IN195/CAL/87A IN195CA1987A IN168174B IN 168174 B IN168174 B IN 168174B IN 195CA1987 A IN195CA1987 A IN 195CA1987A IN 168174 B IN168174 B IN 168174B
Authority
IN
India
Application number
IN195/CAL/87A
Other languages
English (en)
Inventor
Herbert Dr Schwarzbauer
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of IN168174B publication Critical patent/IN168174B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827Materials
    • H01L23/4828Conductive organic material or pastes, e.g. conductive adhesives, inks
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S148/00Metal treatment
    • Y10S148/012Bonding, e.g. electrostatic for strain gauges
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/054Flat sheets-substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)
IN195/CAL/87A 1986-04-22 1987-03-10 IN168174B (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3613572 1986-04-22

Publications (1)

Publication Number Publication Date
IN168174B true IN168174B (nl) 1991-02-16

Family

ID=6299247

Family Applications (1)

Application Number Title Priority Date Filing Date
IN195/CAL/87A IN168174B (nl) 1986-04-22 1987-03-10

Country Status (6)

Country Link
US (1) US4810672A (nl)
EP (1) EP0242626B1 (nl)
JP (1) JP2515708B2 (nl)
BR (1) BR8701876A (nl)
DE (1) DE3770683D1 (nl)
IN (1) IN168174B (nl)

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DE3917765C2 (de) * 1989-05-31 1996-05-30 Siemens Ag Verfahren zum Verbinden von zwei scheibenförmigen Körpern aus Materialien unterschiedlicher thermischer Ausdehnungskoeffizienten und dessen Verwendung
CA2030865C (en) * 1989-11-30 1993-01-12 Kenichi Fuse Method of forming a solder layer on pads of a circuit board and method of mounting an electronic part on a circuit board
EP0460286A3 (en) * 1990-06-06 1992-02-26 Siemens Aktiengesellschaft Method and arrangement for bonding a semiconductor component to a substrate or for finishing a semiconductor/substrate connection by contactless pressing
EP0477600A1 (de) * 1990-09-26 1992-04-01 Siemens Aktiengesellschaft Verfahren zum Befestigen eines mit wenigstens einem Halbleiterbauelement versehenen Halbleiterkörpers auf einem Substrat
US5693574A (en) * 1991-02-22 1997-12-02 Deutsche Aerospace Ag Process for the laminar joining of silicon semiconductor slices
DE4110318C2 (de) * 1991-03-28 2001-10-11 Bosch Gmbh Robert Verfahren zum Zusammenlöten zweier Bauteile
DE59209470D1 (de) * 1991-06-24 1998-10-01 Siemens Ag Halbleiterbauelement und Verfahren zu seiner Herstellung
US5403783A (en) * 1992-12-28 1995-04-04 Hitachi, Ltd. Integrated circuit substrate with cooling accelerator substrate
DE4315272A1 (de) * 1993-05-07 1994-11-10 Siemens Ag Leistungshalbleiterbauelement mit Pufferschicht
JPH08242009A (ja) * 1994-12-02 1996-09-17 Eurec Europ G Fur Leistungshalbleiter Mbh & Co Kg パワー半導体デバイス
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DE59611448D1 (de) * 1995-09-11 2007-12-06 Infineon Technologies Ag Verfahren zur Befestigung elektronischer Bauelemente auf einem Substrat durch Drucksintern
US5967030A (en) * 1995-11-17 1999-10-19 Micron Technology, Inc. Global planarization method and apparatus
JP3928753B2 (ja) 1996-08-06 2007-06-13 日立化成工業株式会社 マルチチップ実装法、および接着剤付チップの製造方法
DE19639934A1 (de) * 1996-09-27 1998-04-09 Siemens Ag Verfahren zur Flipchip-Kontaktierung eines Halbleiterchips mit geringer Anschlußzahl
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US6331488B1 (en) * 1997-05-23 2001-12-18 Micron Technology, Inc. Planarization process for semiconductor substrates
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DE10016129A1 (de) * 2000-03-31 2001-10-18 Siemens Ag Verfahren zum Herstellen einer wärmeleitenden Verbindung zwischen zwei Werkstücken
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BR8701876A (pt) 1988-01-26
US4810672A (en) 1989-03-07
DE3770683D1 (de) 1991-07-18
JPS62254439A (ja) 1987-11-06
EP0242626A3 (en) 1989-01-25
JP2515708B2 (ja) 1996-07-10
EP0242626A2 (de) 1987-10-28
EP0242626B1 (de) 1991-06-12

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