US4709347A
(en)
*
|
1984-12-17 |
1987-11-24 |
Honeywell Inc. |
Method and apparatus for synchronizing the timing subsystems of the physical modules of a local area network
|
US4941088A
(en)
*
|
1985-02-05 |
1990-07-10 |
Digital Equipment Corporation |
Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses
|
US4875155A
(en)
*
|
1985-06-28 |
1989-10-17 |
International Business Machines Corporation |
Peripheral subsystem having read/write cache with record access
|
US4980845A
(en)
*
|
1985-08-23 |
1990-12-25 |
Snap-On Tools Corporation |
Digital engine analyzer
|
US4785395A
(en)
*
|
1986-06-27 |
1988-11-15 |
Honeywell Bull Inc. |
Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
|
US4768148A
(en)
*
|
1986-06-27 |
1988-08-30 |
Honeywell Bull Inc. |
Read in process memory apparatus
|
JP2561261B2
(ja)
*
|
1987-02-18 |
1996-12-04 |
株式会社日立製作所 |
バッファ記憶アクセス方法
|
US5276853A
(en)
*
|
1987-05-18 |
1994-01-04 |
Fujitsu Limited |
Cache system
|
US4833601A
(en)
*
|
1987-05-28 |
1989-05-23 |
Bull Hn Information Systems Inc. |
Cache resiliency in processing a variety of address faults
|
US4926323A
(en)
*
|
1988-03-03 |
1990-05-15 |
Advanced Micro Devices, Inc. |
Streamlined instruction processor
|
US5148536A
(en)
*
|
1988-07-25 |
1992-09-15 |
Digital Equipment Corporation |
Pipeline having an integral cache which processes cache misses and loads data in parallel
|
US5029070A
(en)
*
|
1988-08-25 |
1991-07-02 |
Edge Computer Corporation |
Coherent cache structures and methods
|
US4928225A
(en)
*
|
1988-08-25 |
1990-05-22 |
Edgcore Technology, Inc. |
Coherent cache structures and methods
|
US5027270A
(en)
*
|
1988-10-11 |
1991-06-25 |
Mips Computer Systems, Inc. |
Processor controlled interface with instruction streaming
|
EP0365731B1
(en)
*
|
1988-10-28 |
1994-07-27 |
International Business Machines Corporation |
Method and apparatus for transferring messages between source and destination users through a shared memory
|
US5226146A
(en)
*
|
1988-10-28 |
1993-07-06 |
Hewlett-Packard Company |
Duplicate tag store purge queue
|
US5163142A
(en)
*
|
1988-10-28 |
1992-11-10 |
Hewlett-Packard Company |
Efficient cache write technique through deferred tag modification
|
US5081609A
(en)
*
|
1989-01-10 |
1992-01-14 |
Bull Hn Information Systems Inc. |
Multiprocessor controller having time shared control store
|
US5222223A
(en)
*
|
1989-02-03 |
1993-06-22 |
Digital Equipment Corporation |
Method and apparatus for ordering and queueing multiple memory requests
|
JPH0719222B2
(ja)
*
|
1989-03-30 |
1995-03-06 |
日本電気株式会社 |
ストアバッフア
|
GB2234613B
(en)
*
|
1989-08-03 |
1993-07-07 |
Sun Microsystems Inc |
Method and apparatus for switching context of state elements in a microprocessor
|
US5574912A
(en)
*
|
1990-05-04 |
1996-11-12 |
Digital Equipment Corporation |
Lattice scheduler method for reducing the impact of covert-channel countermeasures
|
US5249284A
(en)
*
|
1990-06-04 |
1993-09-28 |
Ncr Corporation |
Method and system for maintaining data coherency between main and cache memories
|
JP2677706B2
(ja)
*
|
1990-10-19 |
1997-11-17 |
富士通株式会社 |
メモリアクセス制御回路
|
US5287473A
(en)
*
|
1990-12-14 |
1994-02-15 |
International Business Machines Corporation |
Non-blocking serialization for removing data from a shared cache
|
US5537574A
(en)
*
|
1990-12-14 |
1996-07-16 |
International Business Machines Corporation |
Sysplex shared data coherency method
|
US5249283A
(en)
*
|
1990-12-24 |
1993-09-28 |
Ncr Corporation |
Cache coherency method and apparatus for a multiple path interconnection network
|
US5428810A
(en)
*
|
1991-03-15 |
1995-06-27 |
Hewlett-Packard Company |
Allocation of resources of a pipelined processor by clock phase for parallel execution of dependent processes
|
US5530835A
(en)
*
|
1991-09-18 |
1996-06-25 |
Ncr Corporation |
Computer memory data merging technique for computers with write-back caches
|
US5724549A
(en)
*
|
1992-04-06 |
1998-03-03 |
Cyrix Corporation |
Cache coherency without bus master arbitration signals
|
JPH06318174A
(ja)
*
|
1992-04-29 |
1994-11-15 |
Sun Microsyst Inc |
キャッシュ・メモリ・システム及び主メモリに記憶されているデータのサブセットをキャッシュする方法
|
US5821940A
(en)
*
|
1992-08-03 |
1998-10-13 |
Ball Corporation |
Computer graphics vertex index cache system for polygons
|
US5430857A
(en)
*
|
1993-01-04 |
1995-07-04 |
Intel Corporation |
Method and apparatus for translating logical addresses into physical addresses using odd/even translation tables
|
US5689680A
(en)
*
|
1993-07-15 |
1997-11-18 |
Unisys Corp. |
Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
|
JPH0756815A
(ja)
*
|
1993-07-28 |
1995-03-03 |
Internatl Business Mach Corp <Ibm> |
キャッシュ動作方法及びキャッシュ
|
US5581734A
(en)
*
|
1993-08-02 |
1996-12-03 |
International Business Machines Corporation |
Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
|
JPH07129456A
(ja)
*
|
1993-10-28 |
1995-05-19 |
Toshiba Corp |
コンピュータシステム
|
DE69530720T2
(de)
*
|
1994-03-09 |
2003-11-27 |
Sun Microsystems, Inc. |
Verzögertes Cachespeicherschreiben eines Speicherungsbefehls
|
GB2307072B
(en)
|
1994-06-10 |
1998-05-13 |
Advanced Risc Mach Ltd |
Interoperability with multiple instruction sets
|
US5606688A
(en)
*
|
1994-08-31 |
1997-02-25 |
International Business Machines Corporation |
Method and apparatus for dynamic cache memory allocation via single-reference residency times
|
US5752264A
(en)
*
|
1995-03-31 |
1998-05-12 |
International Business Machines Corporation |
Computer architecture incorporating processor clusters and hierarchical cache memories
|
US5903910A
(en)
*
|
1995-11-20 |
1999-05-11 |
Advanced Micro Devices, Inc. |
Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline
|
US5838631A
(en)
|
1996-04-19 |
1998-11-17 |
Integrated Device Technology, Inc. |
Fully synchronous pipelined ram
|
US5819060A
(en)
*
|
1996-10-08 |
1998-10-06 |
Lsi Logic Corporation |
Instruction swapping in dual pipeline microprocessor
|
US5860158A
(en)
*
|
1996-11-15 |
1999-01-12 |
Samsung Electronics Company, Ltd. |
Cache control unit with a cache request transaction-oriented protocol
|
US6061755A
(en)
*
|
1997-04-14 |
2000-05-09 |
International Business Machines Corporation |
Method of layering cache and architectural specific functions to promote operation symmetry
|
US6032226A
(en)
*
|
1997-04-14 |
2000-02-29 |
International Business Machines Corporation |
Method and apparatus for layering cache and architectural specific functions to expedite multiple design
|
US6061762A
(en)
*
|
1997-04-14 |
2000-05-09 |
International Business Machines Corporation |
Apparatus and method for separately layering cache and architectural specific functions in different operational controllers
|
US5909694A
(en)
*
|
1997-06-12 |
1999-06-01 |
International Business Machines Corporation |
Multiway associative external microprocessor cache
|
US7581077B2
(en)
|
1997-10-30 |
2009-08-25 |
Commvault Systems, Inc. |
Method and system for transferring data in a storage operation
|
US6418478B1
(en)
|
1997-10-30 |
2002-07-09 |
Commvault Systems, Inc. |
Pipelined high speed data transfer mechanism
|
US6532468B2
(en)
*
|
1997-12-25 |
2003-03-11 |
Kawasaki Microelectronics, Inc. |
Binary data search method for selecting from among candidate data, and apparatus therefor
|
US6115320A
(en)
|
1998-02-23 |
2000-09-05 |
Integrated Device Technology, Inc. |
Separate byte control on fully synchronous pipelined SRAM
|
US7013305B2
(en)
|
2001-10-01 |
2006-03-14 |
International Business Machines Corporation |
Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
|
US20020108022A1
(en)
*
|
1999-04-28 |
2002-08-08 |
Hong-Yi Hubert Chen |
System and method for allowing back to back write operations in a processing system utilizing a single port cache
|
US6542991B1
(en)
*
|
1999-05-11 |
2003-04-01 |
Sun Microsystems, Inc. |
Multiple-thread processor with single-thread interface shared among threads
|
US7069406B2
(en)
|
1999-07-02 |
2006-06-27 |
Integrated Device Technology, Inc. |
Double data rate synchronous SRAM with 100% bus utilization
|
US6618048B1
(en)
|
1999-10-28 |
2003-09-09 |
Nintendo Co., Ltd. |
3D graphics rendering system for performing Z value clamping in near-Z range to maximize scene resolution of visually important Z components
|
US7119813B1
(en)
|
2000-06-02 |
2006-10-10 |
Nintendo Co., Ltd. |
Variable bit field encoding
|
US6622217B2
(en)
*
|
2000-06-10 |
2003-09-16 |
Hewlett-Packard Development Company, L.P. |
Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system
|
US6867781B1
(en)
|
2000-08-23 |
2005-03-15 |
Nintendo Co., Ltd. |
Graphics pipeline token synchronization
|
US7576748B2
(en)
|
2000-11-28 |
2009-08-18 |
Nintendo Co. Ltd. |
Graphics system with embedded frame butter having reconfigurable pixel formats
|
US6937245B1
(en)
|
2000-08-23 |
2005-08-30 |
Nintendo Co., Ltd. |
Graphics system with embedded frame buffer having reconfigurable pixel formats
|
US6811489B1
(en)
|
2000-08-23 |
2004-11-02 |
Nintendo Co., Ltd. |
Controller interface for a graphics system
|
US6700586B1
(en)
|
2000-08-23 |
2004-03-02 |
Nintendo Co., Ltd. |
Low cost graphics with stitching processing hardware support for skeletal animation
|
US6980218B1
(en)
|
2000-08-23 |
2005-12-27 |
Nintendo Co., Ltd. |
Method and apparatus for efficient generation of texture coordinate displacements for implementing emboss-style bump mapping in a graphics rendering system
|
US6707458B1
(en)
|
2000-08-23 |
2004-03-16 |
Nintendo Co., Ltd. |
Method and apparatus for texture tiling in a graphics system
|
US6636214B1
(en)
|
2000-08-23 |
2003-10-21 |
Nintendo Co., Ltd. |
Method and apparatus for dynamically reconfiguring the order of hidden surface processing based on rendering mode
|
US6825851B1
(en)
|
2000-08-23 |
2004-11-30 |
Nintendo Co., Ltd. |
Method and apparatus for environment-mapped bump-mapping in a graphics system
|
US7061502B1
(en)
|
2000-08-23 |
2006-06-13 |
Nintendo Co., Ltd. |
Method and apparatus for providing logical combination of N alpha operations within a graphics system
|
US7538772B1
(en)
|
2000-08-23 |
2009-05-26 |
Nintendo Co., Ltd. |
Graphics processing system with enhanced memory controller
|
US7034828B1
(en)
|
2000-08-23 |
2006-04-25 |
Nintendo Co., Ltd. |
Recirculating shade tree blender for a graphics system
|
US7002591B1
(en)
|
2000-08-23 |
2006-02-21 |
Nintendo Co., Ltd. |
Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system
|
US7184059B1
(en)
|
2000-08-23 |
2007-02-27 |
Nintendo Co., Ltd. |
Graphics system with copy out conversions between embedded frame buffer and main memory
|
US20060111072A1
(en)
*
|
2002-05-31 |
2006-05-25 |
Silicon Laboratories Inc. |
Wireless communication system and method using clock swapping during image rejection calibration
|
US8370542B2
(en)
|
2002-09-16 |
2013-02-05 |
Commvault Systems, Inc. |
Combined stream auxiliary copy system and method
|
US7583946B2
(en)
*
|
2003-09-29 |
2009-09-01 |
Silicon Laboratories, Inc. |
Wireless communication system and method using clock swapping during image rejection calibration
|
CA2544063C
(en)
|
2003-11-13 |
2013-09-10 |
Commvault Systems, Inc. |
System and method for combining data streams in pilelined storage operations in a storage network
|
JP4680851B2
(ja)
*
|
2006-08-18 |
2011-05-11 |
富士通株式会社 |
システムコントローラ,同一アドレスリクエストキューイング防止方法および情報処理装置
|
JP5011885B2
(ja)
*
|
2006-08-18 |
2012-08-29 |
富士通株式会社 |
スヌープタグの制御装置
|
JP4912789B2
(ja)
*
|
2006-08-18 |
2012-04-11 |
富士通株式会社 |
マルチプロセッサシステム,システムボードおよびキャッシュリプレース要求処理方法
|
US8195890B1
(en)
*
|
2006-08-22 |
2012-06-05 |
Sawyer Law Group, P.C. |
Method for maintaining cache coherence using a distributed directory with event driven updates
|
US8332590B1
(en)
*
|
2008-06-25 |
2012-12-11 |
Marvell Israel (M.I.S.L.) Ltd. |
Multi-stage command processing pipeline and method for shared cache access
|
US8407420B2
(en)
*
|
2010-06-23 |
2013-03-26 |
International Business Machines Corporation |
System, apparatus and method utilizing early access to shared cache pipeline for latency reduction
|
US9898213B2
(en)
|
2015-01-23 |
2018-02-20 |
Commvault Systems, Inc. |
Scalable auxiliary copy processing using media agent resources
|
US9904481B2
(en)
|
2015-01-23 |
2018-02-27 |
Commvault Systems, Inc. |
Scalable auxiliary copy processing in a storage management system using media agent resources
|
KR20170012629A
(ko)
*
|
2015-07-21 |
2017-02-03 |
에스케이하이닉스 주식회사 |
메모리 시스템 및 메모리 시스템의 동작 방법
|
US11010261B2
(en)
|
2017-03-31 |
2021-05-18 |
Commvault Systems, Inc. |
Dynamically allocating streams during restoration of data
|