IE53851B1 - Manufacture of integrated circuits by master slice methods - Google Patents

Manufacture of integrated circuits by master slice methods

Info

Publication number
IE53851B1
IE53851B1 IE2222/82A IE222282A IE53851B1 IE 53851 B1 IE53851 B1 IE 53851B1 IE 2222/82 A IE2222/82 A IE 2222/82A IE 222282 A IE222282 A IE 222282A IE 53851 B1 IE53851 B1 IE 53851B1
Authority
IE
Ireland
Prior art keywords
cells
unit
feeder
integrated circuit
feeder lines
Prior art date
Application number
IE2222/82A
Other languages
English (en)
Other versions
IE822222L (en
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=15327225&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=IE53851(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of IE822222L publication Critical patent/IE822222L/xx
Publication of IE53851B1 publication Critical patent/IE53851B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IE2222/82A 1981-09-10 1982-09-10 Manufacture of integrated circuits by master slice methods IE53851B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56142942A JPS5844743A (ja) 1981-09-10 1981-09-10 半導体集積回路

Publications (2)

Publication Number Publication Date
IE822222L IE822222L (en) 1983-03-10
IE53851B1 true IE53851B1 (en) 1989-03-29

Family

ID=15327225

Family Applications (1)

Application Number Title Priority Date Filing Date
IE2222/82A IE53851B1 (en) 1981-09-10 1982-09-10 Manufacture of integrated circuits by master slice methods

Country Status (5)

Country Link
US (1) US4499484A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0074825B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS5844743A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3276285D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IE (1) IE53851B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984542A (ja) * 1982-11-08 1984-05-16 Nec Corp 高周波半導体集積回路
JPS59167049A (ja) * 1983-03-14 1984-09-20 Nec Corp 半導体装置
US4583111A (en) * 1983-09-09 1986-04-15 Fairchild Semiconductor Corporation Integrated circuit chip wiring arrangement providing reduced circuit inductance and controlled voltage gradients
JPS60101951A (ja) * 1983-11-08 1985-06-06 Sanyo Electric Co Ltd ゲ−トアレイ
DE3579344D1 (de) * 1984-03-29 1990-10-04 Sanyo Electric Co Integrierter halbleiter-schaltkreis mit mehrschichtigen verbindungen.
US4570176A (en) * 1984-04-16 1986-02-11 At&T Bell Laboratories CMOS Cell array with transistor isolation
US4774559A (en) * 1984-12-03 1988-09-27 International Business Machines Corporation Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets
JPS61181144A (ja) * 1985-02-06 1986-08-13 Nec Corp モノリシツク集積回路
JPS61241964A (ja) * 1985-04-19 1986-10-28 Hitachi Ltd 半導体装置
US4977441A (en) * 1985-12-25 1990-12-11 Hitachi, Ltd. Semiconductor device and tape carrier
JP2650133B2 (ja) * 1986-08-08 1997-09-03 富士通株式会社 半導体集積回路装置
JPH083633B2 (ja) * 1987-05-08 1996-01-17 タムラ化研株式会社 耐熱性皮膜形成用感光性組成物
JPS6435934A (en) * 1987-07-30 1989-02-07 Hitachi Ltd Semiconductor integrated circuit device
KR920005863B1 (ko) * 1988-08-12 1992-07-23 산요덴끼 가부시끼가이샤 반도체 집적회로
EP0382948B1 (en) * 1989-02-14 2003-10-08 Koninklijke Philips Electronics N.V. Supply pin rearrangement for an integrated circuit
US5126822A (en) * 1989-02-14 1992-06-30 North American Philips Corporation Supply pin rearrangement for an I.C.
JPH0364735A (ja) * 1989-08-03 1991-03-20 Sharp Corp アクティブマトリクス表示装置
WO1995017007A1 (en) * 1993-12-14 1995-06-22 Oki America, Inc. Efficient routing method and resulting structure for integrated circuits
JP2954165B1 (ja) * 1998-05-20 1999-09-27 日本電気アイシーマイコンシステム株式会社 半導体装置
US6586828B2 (en) * 2001-10-17 2003-07-01 International Business Machines Corporation Integrated circuit bus grid having wires with pre-selected variable widths

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US26803A (en) * 1860-01-10 Clapboard
US3225261A (en) 1963-11-19 1965-12-21 Fairchild Camera Instr Co High frequency power transistor
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
US4006492A (en) * 1975-06-23 1977-02-01 International Business Machines Corporation High density semiconductor chip organization
US4161662A (en) * 1976-01-22 1979-07-17 Motorola, Inc. Standardized digital logic chip
US4249193A (en) * 1978-05-25 1981-02-03 International Business Machines Corporation LSI Semiconductor device and fabrication thereof
JPS5543840A (en) * 1978-09-25 1980-03-27 Hitachi Ltd Power distributing structure of iil element
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method

Also Published As

Publication number Publication date
JPS5844743A (ja) 1983-03-15
EP0074825B1 (en) 1987-05-06
JPS643057B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1989-01-19
US4499484A (en) 1985-02-12
EP0074825B2 (en) 1990-03-21
DE3276285D1 (en) 1987-06-11
EP0074825A3 (en) 1985-01-30
EP0074825A2 (en) 1983-03-23
IE822222L (en) 1983-03-10

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Legal Events

Date Code Title Description
MM4A Patent lapsed