IE51987B1 - Decoder circuit - Google Patents
Decoder circuitInfo
- Publication number
- IE51987B1 IE51987B1 IE237/81A IE23781A IE51987B1 IE 51987 B1 IE51987 B1 IE 51987B1 IE 237/81 A IE237/81 A IE 237/81A IE 23781 A IE23781 A IE 23781A IE 51987 B1 IE51987 B1 IE 51987B1
- Authority
- IE
- Ireland
- Prior art keywords
- selection circuit
- high level
- outputs
- circuit
- low level
- Prior art date
Links
- 230000008878 coupling Effects 0.000 claims abstract description 38
- 238000010168 coupling process Methods 0.000 claims abstract description 38
- 238000005859 coupling reaction Methods 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000010586 diagram Methods 0.000 description 11
- 239000011159 matrix material Substances 0.000 description 5
- 230000003111 delayed effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 206010004966 Bite Diseases 0.000 description 1
- 102100026533 Cytochrome P450 1A2 Human genes 0.000 description 1
- 101000855342 Homo sapiens Cytochrome P450 1A2 Proteins 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
- H03M7/005—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
- G11C11/415—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1457680A JPS56112122A (en) | 1980-02-08 | 1980-02-08 | Decoder circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| IE810237L IE810237L (en) | 1981-08-08 |
| IE51987B1 true IE51987B1 (en) | 1987-05-13 |
Family
ID=11864981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IE237/81A IE51987B1 (en) | 1980-02-08 | 1981-02-06 | Decoder circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4369503A (cg-RX-API-DMAC7.html) |
| EP (1) | EP0035326A3 (cg-RX-API-DMAC7.html) |
| JP (1) | JPS56112122A (cg-RX-API-DMAC7.html) |
| CA (1) | CA1150838A (cg-RX-API-DMAC7.html) |
| IE (1) | IE51987B1 (cg-RX-API-DMAC7.html) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS592291A (ja) * | 1982-06-28 | 1984-01-07 | Fujitsu Ltd | プログラマブル・リ−ドオンリ・メモリ装置 |
| JPS5960794A (ja) * | 1982-09-29 | 1984-04-06 | Fujitsu Ltd | ダイナミツク型半導体記憶装置 |
| JPS5990291A (ja) * | 1982-11-16 | 1984-05-24 | Nec Corp | メモリ |
| JPS59124092A (ja) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | メモリ装置 |
| US4660178A (en) * | 1983-09-21 | 1987-04-21 | Inmos Corporation | Multistage decoding |
| JPS60254484A (ja) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | ２段デコーダ回路 |
| US4613774A (en) * | 1984-07-09 | 1986-09-23 | Advanced Micro Devices, Inc. | Unitary multiplexer-decoder circuit |
| EP0176908B1 (de) * | 1984-09-24 | 1990-01-24 | Siemens Aktiengesellschaft | UND-Gatter für ECL-Schaltungen |
| DE3575059D1 (de) * | 1984-09-24 | 1990-02-01 | Siemens Ag | Und-gatter fuer ecl-schaltungen. |
| US4633220A (en) * | 1984-11-29 | 1986-12-30 | American Microsystems, Inc. | Decoder using pass-transistor networks |
| FR2580420B1 (fr) * | 1985-04-16 | 1991-05-31 | Radiotechnique Compelec | Decodeur a diodes notamment utilisable dans une memoire bipolaire |
| JPS6453395A (en) * | 1987-08-25 | 1989-03-01 | Mitsubishi Electric Corp | Semiconductor memory device |
| JPH01285090A (ja) * | 1988-05-11 | 1989-11-16 | Nippon Telegr & Teleph Corp <Ntt> | バイポーラｃｍｏｓ番地選択回路 |
| JPH0250621A (ja) * | 1988-08-12 | 1990-02-20 | Toshiba Corp | 論理回路 |
| DE3883389T2 (de) * | 1988-10-28 | 1994-03-17 | Ibm | Zweistufige Adressendekodierschaltung für Halbleiterspeicher. |
| JPH02107267U (cg-RX-API-DMAC7.html) * | 1989-02-13 | 1990-08-27 | ||
| JP2504571B2 (ja) * | 1989-08-04 | 1996-06-05 | 富士通株式会社 | 半導体集積回路装置 |
| US5402386A (en) * | 1992-10-14 | 1995-03-28 | Sun Microsystems, Inc. | Word line decoder/driver circuit and method |
| EP2492668B1 (en) * | 2011-02-28 | 2013-08-28 | C.R.F. Società Consortile per Azioni | System and method for monitoring painting quality of components, in particular of motor-vehicle bodies |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3736574A (en) * | 1971-12-30 | 1973-05-29 | Ibm | Pseudo-hierarchy memory system |
| US4027285A (en) * | 1973-12-26 | 1977-05-31 | Motorola, Inc. | Decode circuitry for bipolar random access memory |
| US4007451A (en) * | 1975-05-30 | 1977-02-08 | International Business Machines Corporation | Method and circuit arrangement for operating a highly integrated monolithic information store |
| DE2658523A1 (de) * | 1976-12-23 | 1978-06-29 | Siemens Ag | Halbleiterspeicher |
| JPS53120233A (en) * | 1977-03-30 | 1978-10-20 | Toshiba Corp | Address decoder |
| US4167727A (en) * | 1977-07-08 | 1979-09-11 | Motorola, Inc. | Logic circuits incorporating a dual function input |
| DE2904457C3 (de) * | 1979-02-06 | 1981-11-05 | Siemens AG, 1000 Berlin und 8000 München | Adressdecoder |
| JPS5833634B2 (ja) * | 1979-02-28 | 1983-07-21 | 富士通株式会社 | メモリセルアレイの駆動方式 |
| JPS5631137A (en) * | 1979-08-22 | 1981-03-28 | Fujitsu Ltd | Decoder circuit |
-
1980
- 1980-02-08 JP JP1457680A patent/JPS56112122A/ja active Granted
-
1981
- 1981-02-05 EP EP81300487A patent/EP0035326A3/en not_active Ceased
- 1981-02-06 IE IE237/81A patent/IE51987B1/en not_active IP Right Cessation
- 1981-02-06 US US06/232,008 patent/US4369503A/en not_active Expired - Fee Related
- 1981-02-06 CA CA000370290A patent/CA1150838A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4369503A (en) | 1983-01-18 |
| EP0035326A3 (en) | 1981-09-23 |
| JPS56112122A (en) | 1981-09-04 |
| CA1150838A (en) | 1983-07-26 |
| IE810237L (en) | 1981-08-08 |
| EP0035326A2 (en) | 1981-09-09 |
| JPS6261177B2 (cg-RX-API-DMAC7.html) | 1987-12-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Patent lapsed |