HK1205352A1 - 磁屏蔽、半導體器件和半導體封裝 - Google Patents

磁屏蔽、半導體器件和半導體封裝

Info

Publication number
HK1205352A1
HK1205352A1 HK15105378.4A HK15105378A HK1205352A1 HK 1205352 A1 HK1205352 A1 HK 1205352A1 HK 15105378 A HK15105378 A HK 15105378A HK 1205352 A1 HK1205352 A1 HK 1205352A1
Authority
HK
Hong Kong
Prior art keywords
magnetic shield
semiconductor
semiconductor device
semiconductor package
package
Prior art date
Application number
HK15105378.4A
Other languages
English (en)
Inventor
Tetsuhiro Suzuki
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of HK1205352A1 publication Critical patent/HK1205352A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/11—Magnetic recording head
    • Y10T428/1107—Magnetoresistive

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Thin Magnetic Films (AREA)
HK15105378.4A 2013-06-25 2015-06-05 磁屏蔽、半導體器件和半導體封裝 HK1205352A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013132750A JP6122353B2 (ja) 2013-06-25 2013-06-25 半導体パッケージ

Publications (1)

Publication Number Publication Date
HK1205352A1 true HK1205352A1 (zh) 2015-12-11

Family

ID=52110210

Family Applications (1)

Application Number Title Priority Date Filing Date
HK15105378.4A HK1205352A1 (zh) 2013-06-25 2015-06-05 磁屏蔽、半導體器件和半導體封裝

Country Status (4)

Country Link
US (2) US9837601B2 (zh)
JP (1) JP6122353B2 (zh)
CN (2) CN104253209B (zh)
HK (1) HK1205352A1 (zh)

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* Cited by examiner, † Cited by third party
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CN107978531A (zh) * 2016-10-25 2018-05-01 上海磁宇信息科技有限公司 磁存储芯片封装的磁屏蔽方法
JP6767922B2 (ja) * 2017-05-16 2020-10-14 株式会社東芝 半導体装置
JP6921691B2 (ja) * 2017-09-13 2021-08-18 株式会社東芝 半導体装置
JP7325964B2 (ja) 2019-01-11 2023-08-15 株式会社東芝 電磁波減衰体及び電子装置
JP7160705B2 (ja) * 2019-01-28 2022-10-25 株式会社東芝 電磁波減衰体及び電子装置
US11276649B2 (en) * 2019-06-28 2022-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Devices and methods having magnetic shielding layer
US11710707B2 (en) * 2020-03-26 2023-07-25 Shibaura Mechatronics Corporation Electromagnetic wave attenuator, electronic device, film formation apparatus, and film formation method
JP2022138916A (ja) * 2021-03-11 2022-09-26 キオクシア株式会社 磁気メモリ
CN115149662A (zh) * 2021-03-30 2022-10-04 苹果公司 用于无线充电系统的屏蔽结构

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US5838521A (en) * 1995-04-17 1998-11-17 Read-Rite Corporation Magnetoresistive transducer having laminated magnetic shields
JP4391010B2 (ja) * 2000-12-27 2009-12-24 高橋 研 磁気記録媒体、その製造方法および磁気記録装置
JP2003115578A (ja) 2001-10-05 2003-04-18 Canon Inc 不揮発固体磁気メモリ装置、該不揮発固体磁気メモリ装置の製造方法およびマルチ・チップ・パッケージ
JP4013140B2 (ja) * 2003-01-15 2007-11-28 ソニー株式会社 磁気メモリ装置
JP2004221289A (ja) * 2003-01-15 2004-08-05 Sony Corp 磁気メモリ装置
US7265543B2 (en) * 2003-04-15 2007-09-04 Honeywell International Inc. Integrated set/reset driver and magneto-resistive sensor
US7602000B2 (en) 2003-11-19 2009-10-13 International Business Machines Corporation Spin-current switched magnetic memory element suitable for circuit integration and method of fabricating the memory element
US6992359B2 (en) 2004-02-26 2006-01-31 Grandis, Inc. Spin transfer magnetic element with free layers having high perpendicular anisotropy and in-plane equilibrium magnetization
RU2008107340A (ru) * 2005-07-27 2009-09-10 Инджениа Текнолоджи Лимитед (Gb) Аутентификация рецепта с использованием спекл-структур
US7791844B2 (en) * 2005-12-14 2010-09-07 Hitachi Global Storage Technologies Netherlands B.V. Magnetoresistive sensor having a magnetically stable free layer with a positive magnetostriction
US7974048B2 (en) * 2007-11-28 2011-07-05 Tdk Corporation Magneto-resistive effect device of CPP type having shield layers coupled with ferromagnetic layers
JP4998292B2 (ja) * 2008-01-31 2012-08-15 Ｔｄｋ株式会社 磁性薄膜および薄膜磁気デバイス
WO2009104428A1 (ja) * 2008-02-19 2009-08-27 日本電気株式会社 磁気ランダムアクセスメモリ
JP5224959B2 (ja) * 2008-07-29 2013-07-03 株式会社東芝 キャッシュシステム
JP5343261B2 (ja) * 2008-11-18 2013-11-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5425461B2 (ja) * 2008-12-26 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2010258980A (ja) * 2009-04-28 2010-11-11 Alps Green Devices Co Ltd 磁気結合型アイソレータ
US8437105B2 (en) * 2009-07-08 2013-05-07 Seagate Technology Llc Magnetic sensor with composite magnetic shield
JP2011096356A (ja) * 2009-10-28 2011-05-12 Seagate Technology Llc 多層硬質磁石、データ記憶装置のための読取書込ヘッド、および硬質磁石の製造方法
JP5483281B2 (ja) * 2010-03-31 2014-05-07 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置アセンブリ
US8953285B2 (en) * 2010-05-05 2015-02-10 Headway Technologies, Inc. Side shielded magnetoresistive (MR) read head with perpendicular magnetic free layer
JP5085703B2 (ja) * 2010-09-17 2012-11-28 株式会社東芝 磁気記録素子および不揮発性記憶装置
KR101831931B1 (ko) * 2011-08-10 2018-02-26 삼성전자주식회사 외인성 수직 자화 구조를 구비하는 자기 메모리 장치
JP5673951B2 (ja) * 2011-08-23 2015-02-18 独立行政法人産業技術総合研究所 電界強磁性共鳴励起方法及びそれを用いた磁気機能素子
JP5982795B2 (ja) * 2011-11-30 2016-08-31 ソニー株式会社 記憶素子、記憶装置
JP5571142B2 (ja) * 2012-09-25 2014-08-13 株式会社東芝 磁気メモリ
US9082960B2 (en) * 2013-04-16 2015-07-14 Headway Technologies, Inc. Fully compensated synthetic antiferromagnet for spintronics applications

Also Published As

Publication number Publication date
CN109004086A (zh) 2018-12-14
JP2015008216A (ja) 2015-01-15
CN104253209B (zh) 2018-07-31
US9837601B2 (en) 2017-12-05
JP6122353B2 (ja) 2017-04-26
US20180047892A1 (en) 2018-02-15
CN109004086B (zh) 2022-05-27
US20140374860A1 (en) 2014-12-25
CN104253209A (zh) 2014-12-31
US10305024B2 (en) 2019-05-28

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20220623