HK1091941A1 - Fixed phase clock and strobe signals in daisy chained chips - Google Patents

Fixed phase clock and strobe signals in daisy chained chips

Info

Publication number
HK1091941A1
HK1091941A1 HK06111135.7A HK06111135A HK1091941A1 HK 1091941 A1 HK1091941 A1 HK 1091941A1 HK 06111135 A HK06111135 A HK 06111135A HK 1091941 A1 HK1091941 A1 HK 1091941A1
Authority
HK
Hong Kong
Prior art keywords
fixed phase
phase clock
strobe signals
daisy chained
received
Prior art date
Application number
HK06111135.7A
Other languages
English (en)
Inventor
Stephen R Mooney
Joseph T Kennedy
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1091941A1 publication Critical patent/HK1091941A1/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)
HK06111135.7A 2003-12-30 2006-10-10 Fixed phase clock and strobe signals in daisy chained chips HK1091941A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/749,677 US7031221B2 (en) 2003-12-30 2003-12-30 Fixed phase clock and strobe signals in daisy chained chips
PCT/US2004/043426 WO2005066966A1 (en) 2003-12-30 2004-12-23 Fixed phase clock and strobe signals in daisy chained chips

Publications (1)

Publication Number Publication Date
HK1091941A1 true HK1091941A1 (en) 2007-01-26

Family

ID=34711113

Family Applications (1)

Application Number Title Priority Date Filing Date
HK06111135.7A HK1091941A1 (en) 2003-12-30 2006-10-10 Fixed phase clock and strobe signals in daisy chained chips

Country Status (9)

Country Link
US (1) US7031221B2 (zh)
EP (1) EP1700308B1 (zh)
KR (1) KR100806465B1 (zh)
CN (1) CN1890754B (zh)
AT (1) ATE444555T1 (zh)
DE (1) DE602004023423D1 (zh)
HK (1) HK1091941A1 (zh)
TW (1) TWI269950B (zh)
WO (1) WO2005066966A1 (zh)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US6961862B2 (en) 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
US11948629B2 (en) 2005-09-30 2024-04-02 Mosaid Technologies Incorporated Non-volatile memory device with concurrent bank operations
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
WO2007036050A1 (en) 2005-09-30 2007-04-05 Mosaid Technologies Incorporated Memory with output control
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
TWI460736B (zh) * 2005-09-30 2014-11-11 Conversant Intellectual Property Man Inc 獨立連結與記憶庫選擇
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7555670B2 (en) * 2005-10-26 2009-06-30 Intel Corporation Clocking architecture using a bidirectional clock port
US8284881B2 (en) * 2005-11-03 2012-10-09 Nxp B.V. Data interface and method of seeking synchronization
KR100870536B1 (ko) 2005-12-19 2008-11-26 삼성전자주식회사 고속 인터페이스 방식의 반도체 장치, 반도체 시스템, 및 그 방법
US20070290333A1 (en) * 2006-06-16 2007-12-20 Intel Corporation Chip stack with a higher power chip on the outside of the stack
DE102006036823B4 (de) * 2006-08-07 2008-10-02 Qimonda Ag Datensynchronisier- und -pufferschaltung zur Synchronisation von seriell empfangenen Datensignalen
US8407395B2 (en) 2006-08-22 2013-03-26 Mosaid Technologies Incorporated Scalable memory system
US7904639B2 (en) 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
EP2487794A3 (en) * 2006-08-22 2013-02-13 Mosaid Technologies Incorporated Modular command structure for memory and memory system
US7752364B2 (en) * 2006-12-06 2010-07-06 Mosaid Technologies Incorporated Apparatus and method for communicating with semiconductor devices of a serial interconnection
TWI457944B (zh) * 2006-12-06 2014-10-21 Mosaid Technologies Inc 與串聯互連之半導體裝置通訊的設備、方法與系統
US7925854B2 (en) * 2006-12-06 2011-04-12 Mosaid Technologies Incorporated System and method of operating memory devices of mixed type
US8433874B2 (en) * 2006-12-06 2013-04-30 Mosaid Technologies Incorporated Address assignment and type recognition of serially interconnected memory devices of mixed type
KR101441280B1 (ko) * 2006-12-06 2014-09-17 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드 혼합된 유형의 메모리 장치를 동작시키는 시스템 및 방법
US7554855B2 (en) * 2006-12-20 2009-06-30 Mosaid Technologies Incorporated Hybrid solid-state memory system having volatile and non-volatile memory
US8122202B2 (en) 2007-02-16 2012-02-21 Peter Gillingham Reduced pin count interface
CN101617371B (zh) * 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
WO2008101316A1 (en) 2007-02-22 2008-08-28 Mosaid Technologies Incorporated Apparatus and method for using a page buffer of a memory device as a temporary cache
US8086785B2 (en) 2007-02-22 2011-12-27 Mosaid Technologies Incorporated System and method of page buffer operation for memory devices
KR100885915B1 (ko) * 2007-02-27 2009-02-26 삼성전자주식회사 내부 통신이 가능한 멀티 메모리 칩 및 이를 구비하는시스템
US7865756B2 (en) * 2007-03-12 2011-01-04 Mosaid Technologies Incorporated Methods and apparatus for clock signal synchronization in a configuration of series-connected semiconductor devices
US7904859B2 (en) * 2007-05-09 2011-03-08 Synopsys, Inc. Method and apparatus for determining a phase relationship between asynchronous clock signals
US7688652B2 (en) * 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
WO2009062280A1 (en) * 2007-11-15 2009-05-22 Mosaid Technologies Incorporated Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices
US8825939B2 (en) * 2007-12-12 2014-09-02 Conversant Intellectual Property Management Inc. Semiconductor memory device suitable for interconnection in a ring topology
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8291248B2 (en) * 2007-12-21 2012-10-16 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
CA2701180A1 (en) 2007-12-21 2009-07-02 Mosaid Technologies Incorporated Non-volatile semiconductor memory device with power saving feature
US8594110B2 (en) 2008-01-11 2013-11-26 Mosaid Technologies Incorporated Ring-of-clusters network topologies
US8139390B2 (en) * 2008-07-08 2012-03-20 Mosaid Technologies Incorporated Mixed data rates in memory devices and systems
US8161313B2 (en) * 2008-09-30 2012-04-17 Mosaid Technologies Incorporated Serial-connected memory system with duty cycle correction
US8181056B2 (en) * 2008-09-30 2012-05-15 Mosaid Technologies Incorporated Serial-connected memory system with output delay adjustment
US8134852B2 (en) * 2008-10-14 2012-03-13 Mosaid Technologies Incorporated Bridge device architecture for connecting discrete memory devices to a system
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
US8549209B2 (en) * 2008-11-04 2013-10-01 Mosaid Technologies Incorporated Bridging device having a configurable virtual page size
US20100115172A1 (en) * 2008-11-04 2010-05-06 Mosaid Technologies Incorporated Bridge device having a virtual page buffer
US8194481B2 (en) 2008-12-18 2012-06-05 Mosaid Technologies Incorporated Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
US8037235B2 (en) * 2008-12-18 2011-10-11 Mosaid Technologies Incorporated Device and method for transferring data to a non-volatile memory device
US8521980B2 (en) 2009-07-16 2013-08-27 Mosaid Technologies Incorporated Simultaneous read and write data transfer
KR101086875B1 (ko) 2009-09-30 2011-11-25 주식회사 하이닉스반도체 데이터 전송회로 및 이를 포함하는 반도체 장치
US8284621B2 (en) * 2010-02-15 2012-10-09 International Business Machines Corporation Strobe offset in bidirectional memory strobe configurations
US8582382B2 (en) * 2010-03-23 2013-11-12 Mosaid Technologies Incorporated Memory system having a plurality of serially connected devices
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
US9471484B2 (en) 2012-09-19 2016-10-18 Novachips Canada Inc. Flash memory controller having dual mode pin-out
TWI493566B (zh) * 2012-10-15 2015-07-21 Via Tech Inc 資料儲存裝置、儲存媒體控制器與控制方法
US9571908B2 (en) * 2014-12-23 2017-02-14 Raytheon Company Extendable synchronous low power telemetry system for distributed sensors
US10431268B2 (en) 2016-09-13 2019-10-01 Samsung Electronics Co., Ltd. Semiconductor device and memory controller receiving differential signal
US10635357B2 (en) 2018-07-03 2020-04-28 Nvidia Corporation Method for overlapping memory accesses
KR102675825B1 (ko) * 2018-11-05 2024-06-18 에스케이하이닉스 주식회사 반도체 장치 및 이를 이용한 반도체 시스템 및 동작 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US112119A (en) * 1871-02-28 Improvement in self-centering chucks for lathes
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US5195056A (en) * 1987-05-21 1993-03-16 Texas Instruments, Incorporated Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits
JPH04216392A (ja) * 1990-12-18 1992-08-06 Mitsubishi Electric Corp ブロックライト機能を備える半導体記憶装置
US5546023A (en) * 1995-06-26 1996-08-13 Intel Corporation Daisy chained clock distribution scheme
US5604450A (en) * 1995-07-27 1997-02-18 Intel Corporation High speed bidirectional signaling scheme
US7024518B2 (en) 1998-02-13 2006-04-04 Intel Corporation Dual-port buffer-to-memory interface
US6742098B1 (en) * 2000-10-03 2004-05-25 Intel Corporation Dual-port buffer-to-memory interface
US6697888B1 (en) * 2000-09-29 2004-02-24 Intel Corporation Buffering and interleaving data transfer between a chipset and memory modules
US6658509B1 (en) * 2000-10-03 2003-12-02 Intel Corporation Multi-tier point-to-point ring memory interface
US6934785B2 (en) * 2000-12-22 2005-08-23 Micron Technology, Inc. High speed interface with looped bus
US6437601B1 (en) * 2000-12-26 2002-08-20 Intel Corporation Using a timing strobe for synchronization and validation in a digital logic device
US6373289B1 (en) * 2000-12-26 2002-04-16 Intel Corporation Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe
US6493250B2 (en) * 2000-12-28 2002-12-10 Intel Corporation Multi-tier point-to-point buffered memory interface
US6832325B2 (en) * 2000-12-29 2004-12-14 Intel Corporation Device on a source synchronous bus sending data in quadrature phase relationship and receiving data in phase with the bus clock signal
US6747474B2 (en) * 2001-02-28 2004-06-08 Intel Corporation Integrated circuit stubs in a point-to-point system
US6847617B2 (en) 2001-03-26 2005-01-25 Intel Corporation Systems for interchip communication
US6536025B2 (en) * 2001-05-14 2003-03-18 Intel Corporation Receiver deskewing of multiple source synchronous bits from a parallel bus

Also Published As

Publication number Publication date
TW200525319A (en) 2005-08-01
KR100806465B1 (ko) 2008-02-21
ATE444555T1 (de) 2009-10-15
EP1700308A1 (en) 2006-09-13
US7031221B2 (en) 2006-04-18
WO2005066966A1 (en) 2005-07-21
KR20060101786A (ko) 2006-09-26
CN1890754A (zh) 2007-01-03
US20050146980A1 (en) 2005-07-07
EP1700308B1 (en) 2009-09-30
DE602004023423D1 (de) 2009-11-12
TWI269950B (en) 2007-01-01
CN1890754B (zh) 2010-05-26

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20181223