DE10334779A1 - Halbleiterspeichermodul - Google Patents

Halbleiterspeichermodul Download PDF

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Publication number
DE10334779A1
DE10334779A1 DE10334779A DE10334779A DE10334779A1 DE 10334779 A1 DE10334779 A1 DE 10334779A1 DE 10334779 A DE10334779 A DE 10334779A DE 10334779 A DE10334779 A DE 10334779A DE 10334779 A1 DE10334779 A1 DE 10334779A1
Authority
DE
Germany
Prior art keywords
loop
row
buffer chip
semiconductor memory
memory module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10334779A
Other languages
English (en)
Other versions
DE10334779B4 (de
Inventor
Hermann Ruckerbauer
Maksim Kuzmenka
Andreas Jakobs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10334779A priority Critical patent/DE10334779B4/de
Priority to US10/909,205 priority patent/US6972981B2/en
Publication of DE10334779A1 publication Critical patent/DE10334779A1/de
Application granted granted Critical
Publication of DE10334779B4 publication Critical patent/DE10334779B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Die Erfindung betrifft ein Halbleiterspeichermodul (100) mit mehreren Speicherchips (1-8) und wenigstens einem Taktsignale (CLK) und Befehls- und Adresssignale (C/A) zu den Speicherchips (1-8) sowie Datensignale (Daten) zu und von den Speicherchips (1-8) über einen modulinternen Takt-, Adress-, Befehls- und Datensignalbus treibenden/empfangenden Pufferchip (10), der eine Schnittstelle zu einem äußeren Speicherhauptbus bildet, wobei die Speicherchips (1-8), ausgehend vom Pufferchip (10), in wenigstens einer Reihe (I, II) angeordnet und mit diesem durch den modulinternen Bus verbunden sind. Die Speicherchips (1-8) weisen jeweils getrennte Schreib- und Lesetaktsignaleingänge zum Empfang der Taktsignale (CLK) auf und die Taktsignalleitungen (CLK) sind in mindestens einer Schleife (S) vom Pufferchip (10) über die Speicherchips (1-8) bis zum Ende jeder Reihe (I, II) und von dort zurück zum Pufferchip (10) geführt, wobei die Speicherchips (1-8) beim Datenschreiben durch die vom Pufferchip (10) abgehenden Taktsignale (CLK), die an ihren Schreibtaktsignaleingängen empfangen werden, getaktet und beim Datenlesen durch die zum Pufferchip (10) zurücklaufenden Taktsignale, die an den Lesetaktsignaleingängen der Speicherchips (1-8) empfangen werden, getaktet werden.
DE10334779A 2003-07-30 2003-07-30 Halbleiterspeichermodul Expired - Fee Related DE10334779B4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10334779A DE10334779B4 (de) 2003-07-30 2003-07-30 Halbleiterspeichermodul
US10/909,205 US6972981B2 (en) 2003-07-30 2004-07-30 Semiconductor memory module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10334779A DE10334779B4 (de) 2003-07-30 2003-07-30 Halbleiterspeichermodul

Publications (2)

Publication Number Publication Date
DE10334779A1 true DE10334779A1 (de) 2005-03-10
DE10334779B4 DE10334779B4 (de) 2005-09-29

Family

ID=34177238

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10334779A Expired - Fee Related DE10334779B4 (de) 2003-07-30 2003-07-30 Halbleiterspeichermodul

Country Status (2)

Country Link
US (1) US6972981B2 (de)
DE (1) DE10334779B4 (de)

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DE112005002261B4 (de) 2004-09-30 2019-04-11 Intel Corporation Gepufferter kontinuierlicher Mehrpunkt-Taktring

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KR100468761B1 (ko) * 2002-08-23 2005-01-29 삼성전자주식회사 분할된 시스템 데이터 버스에 연결되는 메모리 모듈을구비하는 반도체 메모리 시스템
US7387827B2 (en) 2002-12-17 2008-06-17 Intel Corporation Interconnection designs and materials having improved strength and fatigue life
US7210059B2 (en) 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7310752B2 (en) 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7216196B2 (en) 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
US7310748B2 (en) 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US7386656B2 (en) * 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US7472220B2 (en) * 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US7392338B2 (en) * 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7515453B2 (en) * 2005-06-24 2009-04-07 Metaram, Inc. Integrated memory core and memory interface circuit
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
DE112006002300B4 (de) 2005-09-02 2013-12-19 Google, Inc. Vorrichtung zum Stapeln von DRAMs
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20070189049A1 (en) * 2006-02-16 2007-08-16 Srdjan Djordjevic Semiconductor memory module
US20080028135A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US7724589B2 (en) * 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
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DE112005002261B4 (de) 2004-09-30 2019-04-11 Intel Corporation Gepufferter kontinuierlicher Mehrpunkt-Taktring

Also Published As

Publication number Publication date
DE10334779B4 (de) 2005-09-29
US20050078532A1 (en) 2005-04-14
US6972981B2 (en) 2005-12-06

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee