TW200731280A - Multi-port memory device with serial input/output interface - Google Patents
Multi-port memory device with serial input/output interfaceInfo
- Publication number
- TW200731280A TW200731280A TW095136302A TW95136302A TW200731280A TW 200731280 A TW200731280 A TW 200731280A TW 095136302 A TW095136302 A TW 095136302A TW 95136302 A TW95136302 A TW 95136302A TW 200731280 A TW200731280 A TW 200731280A
- Authority
- TW
- Taiwan
- Prior art keywords
- memory device
- data
- port memory
- output interface
- serial input
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the first ports via a plurality of first data buses; and a second port for performing a parallel I/O data communication with the external devices through the parallel I/O data pads and a serial I/O data communication with the first ports via a plurality of second data buses, during a test mode.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20050090916 | 2005-09-29 | ||
KR1020060032947A KR100719146B1 (en) | 2005-09-29 | 2006-04-11 | Multi port memory device with serial input/output interface |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200731280A true TW200731280A (en) | 2007-08-16 |
TWI303070B TWI303070B (en) | 2008-11-11 |
Family
ID=37959235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095136302A TWI303070B (en) | 2005-09-29 | 2006-09-29 | Multi-port memory device with serial input/output interface |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR100719146B1 (en) |
CN (1) | CN1941167B (en) |
TW (1) | TWI303070B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100915832B1 (en) * | 2008-08-08 | 2009-09-07 | 주식회사 하이닉스반도체 | Control circuit of read operation for semiconductor memory apparatus |
CN102096650B (en) * | 2009-12-09 | 2012-11-21 | 炬力集成电路设计有限公司 | Interface device |
CN104363448A (en) * | 2014-12-01 | 2015-02-18 | 重庆洪深现代视声技术有限公司 | Television signal generator |
KR102707981B1 (en) * | 2017-02-21 | 2024-09-23 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
KR102139299B1 (en) * | 2018-08-23 | 2020-07-29 | 한국수력원자력 주식회사 | Integration system and method of input and output information of multiple calculation module |
CN110021334B (en) * | 2019-04-19 | 2021-08-27 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4710933A (en) * | 1985-10-23 | 1987-12-01 | Texas Instruments Incorporated | Parallel/serial scan system for testing logic circuits |
US4890224A (en) * | 1986-06-27 | 1989-12-26 | Hewlett-Packard Company | Method and apparatus for fault tolerant communication within a computing system |
KR100582821B1 (en) * | 2003-08-29 | 2006-05-23 | 주식회사 하이닉스반도체 | Multi-port memory device |
-
2006
- 2006-04-11 KR KR1020060032947A patent/KR100719146B1/en not_active IP Right Cessation
- 2006-09-29 TW TW095136302A patent/TWI303070B/en not_active IP Right Cessation
- 2006-09-29 CN CN2006101317245A patent/CN1941167B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20070036609A (en) | 2007-04-03 |
TWI303070B (en) | 2008-11-11 |
CN1941167B (en) | 2011-12-21 |
KR100719146B1 (en) | 2007-05-18 |
CN1941167A (en) | 2007-04-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |